drivers/net/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sh_eth.c - Driver for Renesas ethernet controller.
   4  *
   5  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   6  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   7  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   8  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <cpu_func.h>
  14 #include <env.h>
  15 #include <log.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <netdev.h>
  19 #include <miiphy.h>
  20 #include <asm/cache.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <asm/global_data.h>
  24 #include <asm/io.h>
  25
  26 #ifdef CONFIG_DM_ETH
  27 #include <clk.h>
  28 #include <dm.h>
  29 #include <linux/mii.h>
  30 #include <asm/gpio.h>
  31 #endif
  32
  33 #include "sh_eth.h"
  34
  35 #ifndef CONFIG_SH_ETHER_USE_PORT
  36 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  37 #endif
  38 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  39 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  40 #endif
  41
  42 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  43         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  44 #define flush_cache_wback(addr, len)    \
  45                 flush_dcache_range((unsigned long)addr, \
  46                 (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  47 #else
  48 #define flush_cache_wback(...)
  49 #endif
  50
  51 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  52 #define invalidate_cache(addr, len)             \
  53         {       \
  54                 unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;  \
  55                 unsigned long start, end;       \
  56                 \
  57                 start = (unsigned long)addr;    \
  58                 end = start + len;              \
  59                 start &= ~(line_size - 1);      \
  60                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  61                 \
  62                 invalidate_dcache_range(start, end);    \
  63         }
  64 #else
  65 #define invalidate_cache(...)
  66 #endif
  67
  68 #define TIMEOUT_CNT 1000
  69
  70 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  71 {
  72         int ret = 0, timeout;
  73         struct sh_eth_info *port_info = &eth->port_info[eth->port];
  74
  75         if (!packet || len > 0xffff) {
  76                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  77                 ret = -EINVAL;
  78                 goto err;
  79         }
  80
  81         /* packet must be a 4 byte boundary */
  82         if ((uintptr_t)packet & 3) {
  83                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  84                                 , __func__);
  85                 ret = -EFAULT;
  86                 goto err;
  87         }
  88
  89         /* Update tx descriptor */
  90         flush_cache_wback(packet, len);
  91         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  92         port_info->tx_desc_cur->td1 = len << 16;
  93         /* Must preserve the end of descriptor list indication */
  94         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  95                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  96         else
  97                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  98
  99         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
 100
 101         /* Restart the transmitter if disabled */
 102         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
 103                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
 104
 105         /* Wait until packet is transmitted */
 106         timeout = TIMEOUT_CNT;
 107         do {
 108                 invalidate_cache(port_info->tx_desc_cur,
 109                                  sizeof(struct tx_desc_s));
 110                 udelay(100);
 111         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 112
 113         if (timeout < 0) {
 114                 printf(SHETHER_NAME ": transmit timeout\n");
 115                 ret = -ETIMEDOUT;
 116                 goto err;
 117         }
 118
 119         port_info->tx_desc_cur++;
 120         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 121                 port_info->tx_desc_cur = port_info->tx_desc_base;
 122
 123 err:
 124         return ret;
 125 }
 126
 127 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 128 {
 129         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 130
 131         /* Check if the rx descriptor is ready */
 132         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 133         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 134                 return -EINVAL;
 135
 136         /* Check for errors */
 137         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 138                 return -EINVAL;
 139
 140         return port_info->rx_desc_cur->rd1 & 0xffff;
 141 }
 142
 143 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 144 {
 145         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 146
 147         /* Make current descriptor available again */
 148         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 149                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 150         else
 151                 port_info->rx_desc_cur->rd0 = RD_RACT;
 152
 153         flush_cache_wback(port_info->rx_desc_cur,
 154                           sizeof(struct rx_desc_s));
 155
 156         /* Point to the next descriptor */
 157         port_info->rx_desc_cur++;
 158         if (port_info->rx_desc_cur >=
 159             port_info->rx_desc_base + NUM_RX_DESC)
 160                 port_info->rx_desc_cur = port_info->rx_desc_base;
 161 }
 162
 163 static int sh_eth_reset(struct sh_eth_dev *eth)
 164 {
 165         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 166 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 167         int ret = 0, i;
 168
 169         /* Start e-dmac transmitter and receiver */
 170         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 171
 172         /* Perform a software reset and wait for it to complete */
 173         sh_eth_write(port_info, EDMR_SRST, EDMR);
 174         for (i = 0; i < TIMEOUT_CNT; i++) {
 175                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 176                         break;
 177                 udelay(1000);
 178         }
 179
 180         if (i == TIMEOUT_CNT) {
 181                 printf(SHETHER_NAME  ": Software reset timeout\n");
 182                 ret = -EIO;
 183         }
 184
 185         return ret;
 186 #else
 187         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 188         mdelay(3);
 189         sh_eth_write(port_info,
 190                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 191
 192         return 0;
 193 #endif
 194 }
 195
 196 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 197 {
 198         int i, ret = 0;
 199         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 200         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 201         struct tx_desc_s *cur_tx_desc;
 202
 203         /*
 204          * Allocate rx descriptors. They must be aligned to size of struct
 205          * tx_desc_s.
 206          */
 207         port_info->tx_desc_alloc =
 208                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 209         if (!port_info->tx_desc_alloc) {
 210                 printf(SHETHER_NAME ": memalign failed\n");
 211                 ret = -ENOMEM;
 212                 goto err;
 213         }
 214
 215         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 216
 217         /* Make sure we use a P2 address (non-cacheable) */
 218         port_info->tx_desc_base =
 219                 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
 220         port_info->tx_desc_cur = port_info->tx_desc_base;
 221
 222         /* Initialize all descriptors */
 223         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 224              cur_tx_desc++, i++) {
 225                 cur_tx_desc->td0 = 0x00;
 226                 cur_tx_desc->td1 = 0x00;
 227                 cur_tx_desc->td2 = 0x00;
 228         }
 229
 230         /* Mark the end of the descriptors */
 231         cur_tx_desc--;
 232         cur_tx_desc->td0 |= TD_TDLE;
 233
 234         /*
 235          * Point the controller to the tx descriptor list. Must use physical
 236          * addresses
 237          */
 238         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 239 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 240         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 241         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 242         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 243 #endif
 244
 245 err:
 246         return ret;
 247 }
 248
 249 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 250 {
 251         int i, ret = 0;
 252         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 253         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 254         struct rx_desc_s *cur_rx_desc;
 255         u8 *rx_buf;
 256
 257         /*
 258          * Allocate rx descriptors. They must be aligned to size of struct
 259          * rx_desc_s.
 260          */
 261         port_info->rx_desc_alloc =
 262                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 263         if (!port_info->rx_desc_alloc) {
 264                 printf(SHETHER_NAME ": memalign failed\n");
 265                 ret = -ENOMEM;
 266                 goto err;
 267         }
 268
 269         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 270
 271         /* Make sure we use a P2 address (non-cacheable) */
 272         port_info->rx_desc_base =
 273                 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 274
 275         port_info->rx_desc_cur = port_info->rx_desc_base;
 276
 277         /*
 278          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 279          * aligned and in P2 area.
 280          */
 281         port_info->rx_buf_alloc =
 282                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 283         if (!port_info->rx_buf_alloc) {
 284                 printf(SHETHER_NAME ": alloc failed\n");
 285                 ret = -ENOMEM;
 286                 goto err_buf_alloc;
 287         }
 288
 289         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 290
 291         /* Initialize all descriptors */
 292         for (cur_rx_desc = port_info->rx_desc_base,
 293              rx_buf = port_info->rx_buf_base, i = 0;
 294              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 295                 cur_rx_desc->rd0 = RD_RACT;
 296                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 297                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 298         }
 299
 300         /* Mark the end of the descriptors */
 301         cur_rx_desc--;
 302         cur_rx_desc->rd0 |= RD_RDLE;
 303
 304         /* Point the controller to the rx descriptor list */
 305         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 306 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 307         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 308         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 309         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 310 #endif
 311
 312         return ret;
 313
 314 err_buf_alloc:
 315         free(port_info->rx_desc_alloc);
 316         port_info->rx_desc_alloc = NULL;
 317
 318 err:
 319         return ret;
 320 }
 321
 322 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 323 {
 324         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 325
 326         if (port_info->tx_desc_alloc) {
 327                 free(port_info->tx_desc_alloc);
 328                 port_info->tx_desc_alloc = NULL;
 329         }
 330 }
 331
 332 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 333 {
 334         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 335
 336         if (port_info->rx_desc_alloc) {
 337                 free(port_info->rx_desc_alloc);
 338                 port_info->rx_desc_alloc = NULL;
 339         }
 340
 341         if (port_info->rx_buf_alloc) {
 342                 free(port_info->rx_buf_alloc);
 343                 port_info->rx_buf_alloc = NULL;
 344         }
 345 }
 346
 347 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 348 {
 349         int ret = 0;
 350
 351         ret = sh_eth_tx_desc_init(eth);
 352         if (ret)
 353                 goto err_tx_init;
 354
 355         ret = sh_eth_rx_desc_init(eth);
 356         if (ret)
 357                 goto err_rx_init;
 358
 359         return ret;
 360 err_rx_init:
 361         sh_eth_tx_desc_free(eth);
 362
 363 err_tx_init:
 364         return ret;
 365 }
 366
 367 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
 368                                 unsigned char *mac)
 369 {
 370         u32 val;
 371
 372         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 373         sh_eth_write(port_info, val, MAHR);
 374
 375         val = (mac[4] << 8) | mac[5];
 376         sh_eth_write(port_info, val, MALR);
 377 }
 378
 379 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 380 {
 381         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 382         unsigned long edmr;
 383
 384         /* Configure e-dmac registers */
 385         edmr = sh_eth_read(port_info, EDMR);
 386         edmr &= ~EMDR_DESC_R;
 387         edmr |= EMDR_DESC | EDMR_EL;
 388 #if defined(CONFIG_R8A77980)
 389         edmr |= EDMR_NBST;
 390 #endif
 391         sh_eth_write(port_info, edmr, EDMR);
 392
 393         sh_eth_write(port_info, 0, EESIPR);
 394         sh_eth_write(port_info, 0, TRSCER);
 395         sh_eth_write(port_info, 0, TFTR);
 396         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 397         sh_eth_write(port_info, RMCR_RST, RMCR);
 398 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 399         sh_eth_write(port_info, 0, RPADIR);
 400 #endif
 401         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 402
 403         /* Configure e-mac registers */
 404         sh_eth_write(port_info, 0, ECSIPR);
 405
 406         /* Set Mac address */
 407         sh_eth_write_hwaddr(port_info, mac);
 408
 409         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 410 #if defined(SH_ETH_TYPE_GETHER)
 411         sh_eth_write(port_info, 0, PIPR);
 412 #endif
 413 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 414         sh_eth_write(port_info, APR_AP, APR);
 415         sh_eth_write(port_info, MPR_MP, MPR);
 416         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 417 #endif
 418
 419 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 420         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 421 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 422         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 423 #endif
 424 }
 425
 426 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
 427 {
 428         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 429         struct phy_device *phy = port_info->phydev;
 430         int ret = 0;
 431         u32 val = 0;
 432
 433         /* Set the transfer speed */
 434         if (phy->speed == 100) {
 435                 printf(SHETHER_NAME ": 100Base/");
 436 #if defined(SH_ETH_TYPE_GETHER)
 437                 sh_eth_write(port_info, GECMR_100B, GECMR);
 438 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 439                 sh_eth_write(port_info, 1, RTRATE);
 440 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 441                 val = ECMR_RTM;
 442 #endif
 443         } else if (phy->speed == 10) {
 444                 printf(SHETHER_NAME ": 10Base/");
 445 #if defined(SH_ETH_TYPE_GETHER)
 446                 sh_eth_write(port_info, GECMR_10B, GECMR);
 447 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 448                 sh_eth_write(port_info, 0, RTRATE);
 449 #endif
 450         }
 451 #if defined(SH_ETH_TYPE_GETHER)
 452         else if (phy->speed == 1000) {
 453                 printf(SHETHER_NAME ": 1000Base/");
 454                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 455         }
 456 #endif
 457
 458         /* Check if full duplex mode is supported by the phy */
 459         if (phy->duplex) {
 460                 printf("Full\n");
 461                 sh_eth_write(port_info,
 462                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 463                              ECMR);
 464         } else {
 465                 printf("Half\n");
 466                 sh_eth_write(port_info,
 467                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 468                              ECMR);
 469         }
 470
 471         return ret;
 472 }
 473
 474 static void sh_eth_start(struct sh_eth_dev *eth)
 475 {
 476         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 477
 478         /*
 479          * Enable the e-dmac receiver only. The transmitter will be enabled when
 480          * we have something to transmit
 481          */
 482         sh_eth_write(port_info, EDRRR_R, EDRRR);
 483 }
 484
 485 static void sh_eth_stop(struct sh_eth_dev *eth)
 486 {
 487         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 488
 489         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 490 }
 491
 492 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
 493 {
 494         int ret = 0;
 495
 496         ret = sh_eth_reset(eth);
 497         if (ret)
 498                 return ret;
 499
 500         ret = sh_eth_desc_init(eth);
 501         if (ret)
 502                 return ret;
 503
 504         sh_eth_mac_regs_config(eth, mac);
 505
 506         return 0;
 507 }
 508
 509 static int sh_eth_start_common(struct sh_eth_dev *eth)
 510 {
 511         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 512         int ret;
 513
 514         ret = phy_startup(port_info->phydev);
 515         if (ret) {
 516                 printf(SHETHER_NAME ": phy startup failure\n");
 517                 return ret;
 518         }
 519
 520         ret = sh_eth_phy_regs_config(eth);
 521         if (ret)
 522                 return ret;
 523
 524         sh_eth_start(eth);
 525
 526         return 0;
 527 }
 528
 529 #ifndef CONFIG_DM_ETH
 530 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
 531 {
 532         int ret = 0;
 533         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 534         struct eth_device *dev = port_info->dev;
 535         struct phy_device *phydev;
 536
 537         phydev = phy_connect(
 538                         miiphy_get_dev_by_name(dev->name),
 539                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 540         port_info->phydev = phydev;
 541         phy_config(phydev);
 542
 543         return ret;
 544 }
 545
 546 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
 547 {
 548         struct sh_eth_dev *eth = dev->priv;
 549
 550         return sh_eth_send_common(eth, packet, len);
 551 }
 552
 553 static int sh_eth_recv_common(struct sh_eth_dev *eth)
 554 {
 555         int len = 0;
 556         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 557         uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 558
 559         len = sh_eth_recv_start(eth);
 560         if (len > 0) {
 561                 invalidate_cache(packet, len);
 562                 net_process_received_packet(packet, len);
 563                 sh_eth_recv_finish(eth);
 564         } else
 565                 len = 0;
 566
 567         /* Restart the receiver if disabled */
 568         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 569                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 570
 571         return len;
 572 }
 573
 574 static int sh_eth_recv_legacy(struct eth_device *dev)
 575 {
 576         struct sh_eth_dev *eth = dev->priv;
 577
 578         return sh_eth_recv_common(eth);
 579 }
 580
 581 static int sh_eth_init_legacy(struct eth_device *dev, struct bd_info *bd)
 582 {
 583         struct sh_eth_dev *eth = dev->priv;
 584         int ret;
 585
 586         ret = sh_eth_init_common(eth, dev->enetaddr);
 587         if (ret)
 588                 return ret;
 589
 590         ret = sh_eth_phy_config_legacy(eth);
 591         if (ret) {
 592                 printf(SHETHER_NAME ": phy config timeout\n");
 593                 goto err_start;
 594         }
 595
 596         ret = sh_eth_start_common(eth);
 597         if (ret)
 598                 goto err_start;
 599
 600         return 0;
 601
 602 err_start:
 603         sh_eth_tx_desc_free(eth);
 604         sh_eth_rx_desc_free(eth);
 605         return ret;
 606 }
 607
 608 void sh_eth_halt_legacy(struct eth_device *dev)
 609 {
 610         struct sh_eth_dev *eth = dev->priv;
 611
 612         sh_eth_stop(eth);
 613 }
 614
 615 int sh_eth_initialize(struct bd_info *bd)
 616 {
 617         int ret = 0;
 618         struct sh_eth_dev *eth = NULL;
 619         struct eth_device *dev = NULL;
 620         struct mii_dev *mdiodev;
 621
 622         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 623         if (!eth) {
 624                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 625                 ret = -ENOMEM;
 626                 goto err;
 627         }
 628
 629         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 630         if (!dev) {
 631                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 632                 ret = -ENOMEM;
 633                 goto err;
 634         }
 635         memset(dev, 0, sizeof(struct eth_device));
 636         memset(eth, 0, sizeof(struct sh_eth_dev));
 637
 638         eth->port = CONFIG_SH_ETHER_USE_PORT;
 639         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 640         eth->port_info[eth->port].iobase =
 641                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 642
 643         dev->priv = (void *)eth;
 644         dev->iobase = 0;
 645         dev->init = sh_eth_init_legacy;
 646         dev->halt = sh_eth_halt_legacy;
 647         dev->send = sh_eth_send_legacy;
 648         dev->recv = sh_eth_recv_legacy;
 649         eth->port_info[eth->port].dev = dev;
 650
 651         strcpy(dev->name, SHETHER_NAME);
 652
 653         /* Register Device to EtherNet subsystem  */
 654         eth_register(dev);
 655
 656         bb_miiphy_buses[0].priv = eth;
 657         mdiodev = mdio_alloc();
 658         if (!mdiodev)
 659                 return -ENOMEM;
 660         strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 661         mdiodev->read = bb_miiphy_read;
 662         mdiodev->write = bb_miiphy_write;
 663
 664         ret = mdio_register(mdiodev);
 665         if (ret < 0)
 666                 return ret;
 667
 668         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 669                 puts("Please set MAC address\n");
 670
 671         return ret;
 672
 673 err:
 674         if (dev)
 675                 free(dev);
 676
 677         if (eth)
 678                 free(eth);
 679
 680         printf(SHETHER_NAME ": Failed\n");
 681         return ret;
 682 }
 683
 684 #else /* CONFIG_DM_ETH */
 685
 686 struct sh_ether_priv {
 687         struct sh_eth_dev       shdev;
 688
 689         struct mii_dev          *bus;
 690         phys_addr_t             iobase;
 691         struct clk              clk;
 692         struct gpio_desc        reset_gpio;
 693 };
 694
 695 static int sh_ether_send(struct udevice *dev, void *packet, int len)
 696 {
 697         struct sh_ether_priv *priv = dev_get_priv(dev);
 698         struct sh_eth_dev *eth = &priv->shdev;
 699
 700         return sh_eth_send_common(eth, packet, len);
 701 }
 702
 703 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 704 {
 705         struct sh_ether_priv *priv = dev_get_priv(dev);
 706         struct sh_eth_dev *eth = &priv->shdev;
 707         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 708         uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
 709         int len;
 710
 711         len = sh_eth_recv_start(eth);
 712         if (len > 0) {
 713                 invalidate_cache(packet, len);
 714                 *packetp = packet;
 715
 716                 return len;
 717         } else {
 718                 len = 0;
 719
 720                 /* Restart the receiver if disabled */
 721                 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 722                         sh_eth_write(port_info, EDRRR_R, EDRRR);
 723
 724                 return -EAGAIN;
 725         }
 726 }
 727
 728 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
 729 {
 730         struct sh_ether_priv *priv = dev_get_priv(dev);
 731         struct sh_eth_dev *eth = &priv->shdev;
 732         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 733
 734         sh_eth_recv_finish(eth);
 735
 736         /* Restart the receiver if disabled */
 737         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 738                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 739
 740         return 0;
 741 }
 742
 743 static int sh_ether_write_hwaddr(struct udevice *dev)
 744 {
 745         struct sh_ether_priv *priv = dev_get_priv(dev);
 746         struct sh_eth_dev *eth = &priv->shdev;
 747         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 748         struct eth_pdata *pdata = dev_get_plat(dev);
 749
 750         sh_eth_write_hwaddr(port_info, pdata->enetaddr);
 751
 752         return 0;
 753 }
 754
 755 static int sh_eth_phy_config(struct udevice *dev)
 756 {
 757         struct sh_ether_priv *priv = dev_get_priv(dev);
 758         struct eth_pdata *pdata = dev_get_plat(dev);
 759         struct sh_eth_dev *eth = &priv->shdev;
 760         int ret = 0;
 761         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 762         struct phy_device *phydev;
 763         int mask = 0xffffffff;
 764
 765         phydev = phy_find_by_mask(priv->bus, mask);
 766         if (!phydev)
 767                 return -ENODEV;
 768
 769         phy_connect_dev(phydev, dev, pdata->phy_interface);
 770
 771         port_info->phydev = phydev;
 772         phy_config(phydev);
 773
 774         return ret;
 775 }
 776
 777 static int sh_ether_start(struct udevice *dev)
 778 {
 779         struct sh_ether_priv *priv = dev_get_priv(dev);
 780         struct eth_pdata *pdata = dev_get_plat(dev);
 781         struct sh_eth_dev *eth = &priv->shdev;
 782         int ret;
 783
 784         ret = sh_eth_init_common(eth, pdata->enetaddr);
 785         if (ret)
 786                 return ret;
 787
 788         ret = sh_eth_start_common(eth);
 789         if (ret)
 790                 goto err_start;
 791
 792         return 0;
 793
 794 err_start:
 795         sh_eth_tx_desc_free(eth);
 796         sh_eth_rx_desc_free(eth);
 797         return ret;
 798 }
 799
 800 static void sh_ether_stop(struct udevice *dev)
 801 {
 802         struct sh_ether_priv *priv = dev_get_priv(dev);
 803         struct sh_eth_dev *eth = &priv->shdev;
 804         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 805
 806         phy_shutdown(port_info->phydev);
 807         sh_eth_stop(&priv->shdev);
 808 }
 809
 810 static int sh_ether_probe(struct udevice *udev)
 811 {
 812         struct eth_pdata *pdata = dev_get_plat(udev);
 813         struct sh_ether_priv *priv = dev_get_priv(udev);
 814         struct sh_eth_dev *eth = &priv->shdev;
 815         struct ofnode_phandle_args phandle_args;
 816         struct mii_dev *mdiodev;
 817         int ret;
 818
 819         priv->iobase = pdata->iobase;
 820
 821 #if CONFIG_IS_ENABLED(CLK)
 822         ret = clk_get_by_index(udev, 0, &priv->clk);
 823         if (ret < 0)
 824                 return ret;
 825 #endif
 826
 827         ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
 828         if (!ret) {
 829                 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
 830                                            &priv->reset_gpio, GPIOD_IS_OUT);
 831         }
 832
 833         if (!dm_gpio_is_valid(&priv->reset_gpio)) {
 834                 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
 835                                      GPIOD_IS_OUT);
 836         }
 837
 838         mdiodev = mdio_alloc();
 839         if (!mdiodev) {
 840                 ret = -ENOMEM;
 841                 return ret;
 842         }
 843
 844         mdiodev->read = bb_miiphy_read;
 845         mdiodev->write = bb_miiphy_write;
 846         bb_miiphy_buses[0].priv = eth;
 847         snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 848
 849         ret = mdio_register(mdiodev);
 850         if (ret < 0)
 851                 goto err_mdio_register;
 852
 853         priv->bus = miiphy_get_dev_by_name(udev->name);
 854
 855         eth->port = CONFIG_SH_ETHER_USE_PORT;
 856         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 857         eth->port_info[eth->port].iobase =
 858                 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 859
 860 #if CONFIG_IS_ENABLED(CLK)
 861         ret = clk_enable(&priv->clk);
 862         if (ret)
 863                 goto err_mdio_register;
 864 #endif
 865
 866         ret = sh_eth_init_common(eth, pdata->enetaddr);
 867         if (ret)
 868                 goto err_phy_config;
 869
 870         ret = sh_eth_phy_config(udev);
 871         if (ret) {
 872                 printf(SHETHER_NAME ": phy config timeout\n");
 873                 goto err_phy_config;
 874         }
 875
 876         return 0;
 877
 878 err_phy_config:
 879 #if CONFIG_IS_ENABLED(CLK)
 880         clk_disable(&priv->clk);
 881 #endif
 882 err_mdio_register:
 883         mdio_free(mdiodev);
 884         return ret;
 885 }
 886
 887 static int sh_ether_remove(struct udevice *udev)
 888 {
 889         struct sh_ether_priv *priv = dev_get_priv(udev);
 890         struct sh_eth_dev *eth = &priv->shdev;
 891         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 892
 893 #if CONFIG_IS_ENABLED(CLK)
 894         clk_disable(&priv->clk);
 895 #endif
 896         free(port_info->phydev);
 897         mdio_unregister(priv->bus);
 898         mdio_free(priv->bus);
 899
 900         if (dm_gpio_is_valid(&priv->reset_gpio))
 901                 dm_gpio_free(udev, &priv->reset_gpio);
 902
 903         return 0;
 904 }
 905
 906 static const struct eth_ops sh_ether_ops = {
 907         .start                  = sh_ether_start,
 908         .send                   = sh_ether_send,
 909         .recv                   = sh_ether_recv,
 910         .free_pkt               = sh_ether_free_pkt,
 911         .stop                   = sh_ether_stop,
 912         .write_hwaddr           = sh_ether_write_hwaddr,
 913 };
 914
 915 int sh_ether_of_to_plat(struct udevice *dev)
 916 {
 917         struct eth_pdata *pdata = dev_get_plat(dev);
 918         const fdt32_t *cell;
 919
 920         pdata->iobase = dev_read_addr(dev);
 921
 922         pdata->phy_interface = dev_read_phy_mode(dev);
 923         if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
 924                 return -EINVAL;
 925
 926         pdata->max_speed = 1000;
 927         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
 928         if (cell)
 929                 pdata->max_speed = fdt32_to_cpu(*cell);
 930
 931         sprintf(bb_miiphy_buses[0].name, dev->name);
 932
 933         return 0;
 934 }
 935
 936 static const struct udevice_id sh_ether_ids[] = {
 937         { .compatible = "renesas,ether-r7s72100" },
 938         { .compatible = "renesas,ether-r8a7790" },
 939         { .compatible = "renesas,ether-r8a7791" },
 940         { .compatible = "renesas,ether-r8a7793" },
 941         { .compatible = "renesas,ether-r8a7794" },
 942         { .compatible = "renesas,gether-r8a77980" },
 943         { }
 944 };
 945
 946 U_BOOT_DRIVER(eth_sh_ether) = {
 947         .name           = "sh_ether",
 948         .id             = UCLASS_ETH,
 949         .of_match       = sh_ether_ids,
 950         .of_to_plat = sh_ether_of_to_plat,
 951         .probe          = sh_ether_probe,
 952         .remove         = sh_ether_remove,
 953         .ops            = &sh_ether_ops,
 954         .priv_auto      = sizeof(struct sh_ether_priv),
 955         .plat_auto      = sizeof(struct eth_pdata),
 956         .flags          = DM_FLAG_ALLOC_PRIV_DMA,
 957 };
 958 #endif
 959
 960 /******* for bb_miiphy *******/
 961 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 962 {
 963         return 0;
 964 }
 965
 966 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 967 {
 968         struct sh_eth_dev *eth = bus->priv;
 969         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 970
 971         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 972
 973         return 0;
 974 }
 975
 976 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 977 {
 978         struct sh_eth_dev *eth = bus->priv;
 979         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 980
 981         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 982
 983         return 0;
 984 }
 985
 986 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 987 {
 988         struct sh_eth_dev *eth = bus->priv;
 989         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 990
 991         if (v)
 992                 sh_eth_write(port_info,
 993                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 994         else
 995                 sh_eth_write(port_info,
 996                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
 997
 998         return 0;
 999 }
1000
1001 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
1002 {
1003         struct sh_eth_dev *eth = bus->priv;
1004         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1005
1006         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
1007
1008         return 0;
1009 }
1010
1011 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1012 {
1013         struct sh_eth_dev *eth = bus->priv;
1014         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1015
1016         if (v)
1017                 sh_eth_write(port_info,
1018                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1019         else
1020                 sh_eth_write(port_info,
1021                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1022
1023         return 0;
1024 }
1025
1026 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1027 {
1028         udelay(10);
1029
1030         return 0;
1031 }
1032
1033 struct bb_miiphy_bus bb_miiphy_buses[] = {
1034         {
1035                 .name           = "sh_eth",
1036                 .init           = sh_eth_bb_init,
1037                 .mdio_active    = sh_eth_bb_mdio_active,
1038                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
1039                 .set_mdio       = sh_eth_bb_set_mdio,
1040                 .get_mdio       = sh_eth_bb_get_mdio,
1041                 .set_mdc        = sh_eth_bb_set_mdc,
1042                 .delay          = sh_eth_bb_delay,
1043         }
1044 };
1045
1046 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);