drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/i2c-algo-bit.h>
  18 #include "net_driver.h"
  19 #include "bitfield.h"
  20 #include "efx.h"
  21 #include "mac.h"
  22 #include "gmii.h"
  23 #include "spi.h"
  24 #include "falcon.h"
  25 #include "falcon_hwdefs.h"
  26 #include "falcon_io.h"
  27 #include "mdio_10g.h"
  28 #include "phy.h"
  29 #include "boards.h"
  30 #include "workarounds.h"
  31
  32 /* Falcon hardware control.
  33  * Falcon is the internal codename for the SFC4000 controller that is
  34  * present in SFE400X evaluation boards
  35  */
  36
  37 /**
  38  * struct falcon_nic_data - Falcon NIC state
  39  * @next_buffer_table: First available buffer table id
  40  * @pci_dev2: The secondary PCI device if present
  41  * @i2c_data: Operations and state for I2C bit-bashing algorithm
  42  */
  43 struct falcon_nic_data {
  44         unsigned next_buffer_table;
  45         struct pci_dev *pci_dev2;
  46         struct i2c_algo_bit_data i2c_data;
  47 };
  48
  49 /**************************************************************************
  50  *
  51  * Configurable values
  52  *
  53  **************************************************************************
  54  */
  55
  56 static int disable_dma_stats;
  57
  58 /* This is set to 16 for a good reason.  In summary, if larger than
  59  * 16, the descriptor cache holds more than a default socket
  60  * buffer's worth of packets (for UDP we can only have at most one
  61  * socket buffer's worth outstanding).  This combined with the fact
  62  * that we only get 1 TX event per descriptor cache means the NIC
  63  * goes idle.
  64  */
  65 #define TX_DC_ENTRIES 16
  66 #define TX_DC_ENTRIES_ORDER 0
  67 #define TX_DC_BASE 0x130000
  68
  69 #define RX_DC_ENTRIES 64
  70 #define RX_DC_ENTRIES_ORDER 2
  71 #define RX_DC_BASE 0x100000
  72
  73 /* RX FIFO XOFF watermark
  74  *
  75  * When the amount of the RX FIFO increases used increases past this
  76  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  77  * This also has an effect on RX/TX arbitration
  78  */
  79 static int rx_xoff_thresh_bytes = -1;
  80 module_param(rx_xoff_thresh_bytes, int, 0644);
  81 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  82
  83 /* RX FIFO XON watermark
  84  *
  85  * When the amount of the RX FIFO used decreases below this
  86  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
  87  * This also has an effect on RX/TX arbitration
  88  */
  89 static int rx_xon_thresh_bytes = -1;
  90 module_param(rx_xon_thresh_bytes, int, 0644);
  91 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
  92
  93 /* TX descriptor ring size - min 512 max 4k */
  94 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
  95 #define FALCON_TXD_RING_SIZE 1024
  96 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
  97
  98 /* RX descriptor ring size - min 512 max 4k */
  99 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
 100 #define FALCON_RXD_RING_SIZE 1024
 101 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
 102
 103 /* Event queue size - max 32k */
 104 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
 105 #define FALCON_EVQ_SIZE 4096
 106 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
 107
 108 /* Max number of internal errors. After this resets will not be performed */
 109 #define FALCON_MAX_INT_ERRORS 4
 110
 111 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
 112  */
 113 #define FALCON_FLUSH_INTERVAL 10
 114 #define FALCON_FLUSH_POLL_COUNT 100
 115
 116 /**************************************************************************
 117  *
 118  * Falcon constants
 119  *
 120  **************************************************************************
 121  */
 122
 123 /* DMA address mask */
 124 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
 125
 126 /* TX DMA length mask (13-bit) */
 127 #define FALCON_TX_DMA_MASK (4096 - 1)
 128
 129 /* Size and alignment of special buffers (4KB) */
 130 #define FALCON_BUF_SIZE 4096
 131
 132 /* Dummy SRAM size code */
 133 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
 134
 135 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
 136 #define PCI_EXP_DEVCAP_PWR_VAL_LBN      18
 137 #define PCI_EXP_DEVCAP_PWR_SCL_LBN      26
 138 #define PCI_EXP_DEVCTL_PAYLOAD_LBN      5
 139 #define PCI_EXP_LNKSTA_LNK_WID          0x3f0
 140 #define PCI_EXP_LNKSTA_LNK_WID_LBN      4
 141
 142 #define FALCON_IS_DUAL_FUNC(efx)                \
 143         (falcon_rev(efx) < FALCON_REV_B0)
 144
 145 /**************************************************************************
 146  *
 147  * Falcon hardware access
 148  *
 149  **************************************************************************/
 150
 151 /* Read the current event from the event queue */
 152 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
 153                                         unsigned int index)
 154 {
 155         return (((efx_qword_t *) (channel->eventq.addr)) + index);
 156 }
 157
 158 /* See if an event is present
 159  *
 160  * We check both the high and low dword of the event for all ones.  We
 161  * wrote all ones when we cleared the event, and no valid event can
 162  * have all ones in either its high or low dwords.  This approach is
 163  * robust against reordering.
 164  *
 165  * Note that using a single 64-bit comparison is incorrect; even
 166  * though the CPU read will be atomic, the DMA write may not be.
 167  */
 168 static inline int falcon_event_present(efx_qword_t *event)
 169 {
 170         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 171                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
 172 }
 173
 174 /**************************************************************************
 175  *
 176  * I2C bus - this is a bit-bashing interface using GPIO pins
 177  * Note that it uses the output enables to tristate the outputs
 178  * SDA is the data pin and SCL is the clock
 179  *
 180  **************************************************************************
 181  */
 182 static void falcon_setsda(void *data, int state)
 183 {
 184         struct efx_nic *efx = (struct efx_nic *)data;
 185         efx_oword_t reg;
 186
 187         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 188         EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
 189         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
 190 }
 191
 192 static void falcon_setscl(void *data, int state)
 193 {
 194         struct efx_nic *efx = (struct efx_nic *)data;
 195         efx_oword_t reg;
 196
 197         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 198         EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
 199         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
 200 }
 201
 202 static int falcon_getsda(void *data)
 203 {
 204         struct efx_nic *efx = (struct efx_nic *)data;
 205         efx_oword_t reg;
 206
 207         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 208         return EFX_OWORD_FIELD(reg, GPIO3_IN);
 209 }
 210
 211 static int falcon_getscl(void *data)
 212 {
 213         struct efx_nic *efx = (struct efx_nic *)data;
 214         efx_oword_t reg;
 215
 216         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 217         return EFX_OWORD_FIELD(reg, GPIO0_IN);
 218 }
 219
 220 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 221         .setsda         = falcon_setsda,
 222         .setscl         = falcon_setscl,
 223         .getsda         = falcon_getsda,
 224         .getscl         = falcon_getscl,
 225         .udelay         = 5,
 226         /* Wait up to 50 ms for slave to let us pull SCL high */
 227         .timeout        = DIV_ROUND_UP(HZ, 20),
 228 };
 229
 230 /**************************************************************************
 231  *
 232  * Falcon special buffer handling
 233  * Special buffers are used for event queues and the TX and RX
 234  * descriptor rings.
 235  *
 236  *************************************************************************/
 237
 238 /*
 239  * Initialise a Falcon special buffer
 240  *
 241  * This will define a buffer (previously allocated via
 242  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
 243  * it to be used for event queues, descriptor rings etc.
 244  */
 245 static void
 246 falcon_init_special_buffer(struct efx_nic *efx,
 247                            struct efx_special_buffer *buffer)
 248 {
 249         efx_qword_t buf_desc;
 250         int index;
 251         dma_addr_t dma_addr;
 252         int i;
 253
 254         EFX_BUG_ON_PARANOID(!buffer->addr);
 255
 256         /* Write buffer descriptors to NIC */
 257         for (i = 0; i < buffer->entries; i++) {
 258                 index = buffer->index + i;
 259                 dma_addr = buffer->dma_addr + (i * 4096);
 260                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
 261                         index, (unsigned long long)dma_addr);
 262                 EFX_POPULATE_QWORD_4(buf_desc,
 263                                      IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
 264                                      BUF_ADR_REGION, 0,
 265                                      BUF_ADR_FBUF, (dma_addr >> 12),
 266                                      BUF_OWNER_ID_FBUF, 0);
 267                 falcon_write_sram(efx, &buf_desc, index);
 268         }
 269 }
 270
 271 /* Unmaps a buffer from Falcon and clears the buffer table entries */
 272 static void
 273 falcon_fini_special_buffer(struct efx_nic *efx,
 274                            struct efx_special_buffer *buffer)
 275 {
 276         efx_oword_t buf_tbl_upd;
 277         unsigned int start = buffer->index;
 278         unsigned int end = (buffer->index + buffer->entries - 1);
 279
 280         if (!buffer->entries)
 281                 return;
 282
 283         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
 284                 buffer->index, buffer->index + buffer->entries - 1);
 285
 286         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 287                              BUF_UPD_CMD, 0,
 288                              BUF_CLR_CMD, 1,
 289                              BUF_CLR_END_ID, end,
 290                              BUF_CLR_START_ID, start);
 291         falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
 292 }
 293
 294 /*
 295  * Allocate a new Falcon special buffer
 296  *
 297  * This allocates memory for a new buffer, clears it and allocates a
 298  * new buffer ID range.  It does not write into Falcon's buffer table.
 299  *
 300  * This call will allocate 4KB buffers, since Falcon can't use 8KB
 301  * buffers for event queues and descriptor rings.
 302  */
 303 static int falcon_alloc_special_buffer(struct efx_nic *efx,
 304                                        struct efx_special_buffer *buffer,
 305                                        unsigned int len)
 306 {
 307         struct falcon_nic_data *nic_data = efx->nic_data;
 308
 309         len = ALIGN(len, FALCON_BUF_SIZE);
 310
 311         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 312                                             &buffer->dma_addr);
 313         if (!buffer->addr)
 314                 return -ENOMEM;
 315         buffer->len = len;
 316         buffer->entries = len / FALCON_BUF_SIZE;
 317         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
 318
 319         /* All zeros is a potentially valid event so memset to 0xff */
 320         memset(buffer->addr, 0xff, len);
 321
 322         /* Select new buffer ID */
 323         buffer->index = nic_data->next_buffer_table;
 324         nic_data->next_buffer_table += buffer->entries;
 325
 326         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
 327                 "(virt %p phys %lx)\n", buffer->index,
 328                 buffer->index + buffer->entries - 1,
 329                 (unsigned long long)buffer->dma_addr, len,
 330                 buffer->addr, virt_to_phys(buffer->addr));
 331
 332         return 0;
 333 }
 334
 335 static void falcon_free_special_buffer(struct efx_nic *efx,
 336                                        struct efx_special_buffer *buffer)
 337 {
 338         if (!buffer->addr)
 339                 return;
 340
 341         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
 342                 "(virt %p phys %lx)\n", buffer->index,
 343                 buffer->index + buffer->entries - 1,
 344                 (unsigned long long)buffer->dma_addr, buffer->len,
 345                 buffer->addr, virt_to_phys(buffer->addr));
 346
 347         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
 348                             buffer->dma_addr);
 349         buffer->addr = NULL;
 350         buffer->entries = 0;
 351 }
 352
 353 /**************************************************************************
 354  *
 355  * Falcon generic buffer handling
 356  * These buffers are used for interrupt status and MAC stats
 357  *
 358  **************************************************************************/
 359
 360 static int falcon_alloc_buffer(struct efx_nic *efx,
 361                                struct efx_buffer *buffer, unsigned int len)
 362 {
 363         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 364                                             &buffer->dma_addr);
 365         if (!buffer->addr)
 366                 return -ENOMEM;
 367         buffer->len = len;
 368         memset(buffer->addr, 0, len);
 369         return 0;
 370 }
 371
 372 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 373 {
 374         if (buffer->addr) {
 375                 pci_free_consistent(efx->pci_dev, buffer->len,
 376                                     buffer->addr, buffer->dma_addr);
 377                 buffer->addr = NULL;
 378         }
 379 }
 380
 381 /**************************************************************************
 382  *
 383  * Falcon TX path
 384  *
 385  **************************************************************************/
 386
 387 /* Returns a pointer to the specified transmit descriptor in the TX
 388  * descriptor queue belonging to the specified channel.
 389  */
 390 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
 391                                                unsigned int index)
 392 {
 393         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
 394 }
 395
 396 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 397 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
 398 {
 399         unsigned write_ptr;
 400         efx_dword_t reg;
 401
 402         write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
 403         EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
 404         falcon_writel_page(tx_queue->efx, &reg,
 405                            TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
 406 }
 407
 408
 409 /* For each entry inserted into the software descriptor ring, create a
 410  * descriptor in the hardware TX descriptor ring (in host memory), and
 411  * write a doorbell.
 412  */
 413 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
 414 {
 415
 416         struct efx_tx_buffer *buffer;
 417         efx_qword_t *txd;
 418         unsigned write_ptr;
 419
 420         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 421
 422         do {
 423                 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
 424                 buffer = &tx_queue->buffer[write_ptr];
 425                 txd = falcon_tx_desc(tx_queue, write_ptr);
 426                 ++tx_queue->write_count;
 427
 428                 /* Create TX descriptor ring entry */
 429                 EFX_POPULATE_QWORD_5(*txd,
 430                                      TX_KER_PORT, 0,
 431                                      TX_KER_CONT, buffer->continuation,
 432                                      TX_KER_BYTE_CNT, buffer->len,
 433                                      TX_KER_BUF_REGION, 0,
 434                                      TX_KER_BUF_ADR, buffer->dma_addr);
 435         } while (tx_queue->write_count != tx_queue->insert_count);
 436
 437         wmb(); /* Ensure descriptors are written before they are fetched */
 438         falcon_notify_tx_desc(tx_queue);
 439 }
 440
 441 /* Allocate hardware resources for a TX queue */
 442 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
 443 {
 444         struct efx_nic *efx = tx_queue->efx;
 445         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
 446                                            FALCON_TXD_RING_SIZE *
 447                                            sizeof(efx_qword_t));
 448 }
 449
 450 void falcon_init_tx(struct efx_tx_queue *tx_queue)
 451 {
 452         efx_oword_t tx_desc_ptr;
 453         struct efx_nic *efx = tx_queue->efx;
 454
 455         tx_queue->flushed = false;
 456
 457         /* Pin TX descriptor ring */
 458         falcon_init_special_buffer(efx, &tx_queue->txd);
 459
 460         /* Push TX descriptor ring to card */
 461         EFX_POPULATE_OWORD_10(tx_desc_ptr,
 462                               TX_DESCQ_EN, 1,
 463                               TX_ISCSI_DDIG_EN, 0,
 464                               TX_ISCSI_HDIG_EN, 0,
 465                               TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 466                               TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
 467                               TX_DESCQ_OWNER_ID, 0,
 468                               TX_DESCQ_LABEL, tx_queue->queue,
 469                               TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
 470                               TX_DESCQ_TYPE, 0,
 471                               TX_NON_IP_DROP_DIS_B0, 1);
 472
 473         if (falcon_rev(efx) >= FALCON_REV_B0) {
 474                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
 475                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
 476                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
 477         }
 478
 479         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 480                            tx_queue->queue);
 481
 482         if (falcon_rev(efx) < FALCON_REV_B0) {
 483                 efx_oword_t reg;
 484
 485                 /* Only 128 bits in this register */
 486                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
 487
 488                 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
 489                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
 490                         clear_bit_le(tx_queue->queue, (void *)&reg);
 491                 else
 492                         set_bit_le(tx_queue->queue, (void *)&reg);
 493                 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
 494         }
 495 }
 496
 497 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
 498 {
 499         struct efx_nic *efx = tx_queue->efx;
 500         efx_oword_t tx_flush_descq;
 501
 502         /* Post a flush command */
 503         EFX_POPULATE_OWORD_2(tx_flush_descq,
 504                              TX_FLUSH_DESCQ_CMD, 1,
 505                              TX_FLUSH_DESCQ, tx_queue->queue);
 506         falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
 507 }
 508
 509 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
 510 {
 511         struct efx_nic *efx = tx_queue->efx;
 512         efx_oword_t tx_desc_ptr;
 513
 514         /* The queue should have been flushed */
 515         WARN_ON(!tx_queue->flushed);
 516
 517         /* Remove TX descriptor ring from card */
 518         EFX_ZERO_OWORD(tx_desc_ptr);
 519         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 520                            tx_queue->queue);
 521
 522         /* Unpin TX descriptor ring */
 523         falcon_fini_special_buffer(efx, &tx_queue->txd);
 524 }
 525
 526 /* Free buffers backing TX queue */
 527 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
 528 {
 529         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 530 }
 531
 532 /**************************************************************************
 533  *
 534  * Falcon RX path
 535  *
 536  **************************************************************************/
 537
 538 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 539 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
 540                                                unsigned int index)
 541 {
 542         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
 543 }
 544
 545 /* This creates an entry in the RX descriptor queue */
 546 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
 547                                         unsigned index)
 548 {
 549         struct efx_rx_buffer *rx_buf;
 550         efx_qword_t *rxd;
 551
 552         rxd = falcon_rx_desc(rx_queue, index);
 553         rx_buf = efx_rx_buffer(rx_queue, index);
 554         EFX_POPULATE_QWORD_3(*rxd,
 555                              RX_KER_BUF_SIZE,
 556                              rx_buf->len -
 557                              rx_queue->efx->type->rx_buffer_padding,
 558                              RX_KER_BUF_REGION, 0,
 559                              RX_KER_BUF_ADR, rx_buf->dma_addr);
 560 }
 561
 562 /* This writes to the RX_DESC_WPTR register for the specified receive
 563  * descriptor ring.
 564  */
 565 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
 566 {
 567         efx_dword_t reg;
 568         unsigned write_ptr;
 569
 570         while (rx_queue->notified_count != rx_queue->added_count) {
 571                 falcon_build_rx_desc(rx_queue,
 572                                      rx_queue->notified_count &
 573                                      FALCON_RXD_RING_MASK);
 574                 ++rx_queue->notified_count;
 575         }
 576
 577         wmb();
 578         write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
 579         EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
 580         falcon_writel_page(rx_queue->efx, &reg,
 581                            RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
 582 }
 583
 584 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
 585 {
 586         struct efx_nic *efx = rx_queue->efx;
 587         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
 588                                            FALCON_RXD_RING_SIZE *
 589                                            sizeof(efx_qword_t));
 590 }
 591
 592 void falcon_init_rx(struct efx_rx_queue *rx_queue)
 593 {
 594         efx_oword_t rx_desc_ptr;
 595         struct efx_nic *efx = rx_queue->efx;
 596         bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
 597         bool iscsi_digest_en = is_b0;
 598
 599         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
 600                 rx_queue->queue, rx_queue->rxd.index,
 601                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 602
 603         rx_queue->flushed = false;
 604
 605         /* Pin RX descriptor ring */
 606         falcon_init_special_buffer(efx, &rx_queue->rxd);
 607
 608         /* Push RX descriptor ring to card */
 609         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 610                               RX_ISCSI_DDIG_EN, iscsi_digest_en,
 611                               RX_ISCSI_HDIG_EN, iscsi_digest_en,
 612                               RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 613                               RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
 614                               RX_DESCQ_OWNER_ID, 0,
 615                               RX_DESCQ_LABEL, rx_queue->queue,
 616                               RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
 617                               RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 618                               /* For >=B0 this is scatter so disable */
 619                               RX_DESCQ_JUMBO, !is_b0,
 620                               RX_DESCQ_EN, 1);
 621         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 622                            rx_queue->queue);
 623 }
 624
 625 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
 626 {
 627         struct efx_nic *efx = rx_queue->efx;
 628         efx_oword_t rx_flush_descq;
 629
 630         /* Post a flush command */
 631         EFX_POPULATE_OWORD_2(rx_flush_descq,
 632                              RX_FLUSH_DESCQ_CMD, 1,
 633                              RX_FLUSH_DESCQ, rx_queue->queue);
 634         falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
 635 }
 636
 637 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
 638 {
 639         efx_oword_t rx_desc_ptr;
 640         struct efx_nic *efx = rx_queue->efx;
 641
 642         /* The queue should already have been flushed */
 643         WARN_ON(!rx_queue->flushed);
 644
 645         /* Remove RX descriptor ring from card */
 646         EFX_ZERO_OWORD(rx_desc_ptr);
 647         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 648                            rx_queue->queue);
 649
 650         /* Unpin RX descriptor ring */
 651         falcon_fini_special_buffer(efx, &rx_queue->rxd);
 652 }
 653
 654 /* Free buffers backing RX queue */
 655 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
 656 {
 657         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 658 }
 659
 660 /**************************************************************************
 661  *
 662  * Falcon event queue processing
 663  * Event queues are processed by per-channel tasklets.
 664  *
 665  **************************************************************************/
 666
 667 /* Update a channel's event queue's read pointer (RPTR) register
 668  *
 669  * This writes the EVQ_RPTR_REG register for the specified channel's
 670  * event queue.
 671  *
 672  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
 673  * whereas channel->eventq_read_ptr contains the index of the "next to
 674  * read" event.
 675  */
 676 void falcon_eventq_read_ack(struct efx_channel *channel)
 677 {
 678         efx_dword_t reg;
 679         struct efx_nic *efx = channel->efx;
 680
 681         EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
 682         falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 683                             channel->channel);
 684 }
 685
 686 /* Use HW to insert a SW defined event */
 687 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
 688 {
 689         efx_oword_t drv_ev_reg;
 690
 691         EFX_POPULATE_OWORD_2(drv_ev_reg,
 692                              DRV_EV_QID, channel->channel,
 693                              DRV_EV_DATA,
 694                              EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
 695         falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
 696 }
 697
 698 /* Handle a transmit completion event
 699  *
 700  * Falcon batches TX completion events; the message we receive is of
 701  * the form "complete all TX events up to this index".
 702  */
 703 static void falcon_handle_tx_event(struct efx_channel *channel,
 704                                    efx_qword_t *event)
 705 {
 706         unsigned int tx_ev_desc_ptr;
 707         unsigned int tx_ev_q_label;
 708         struct efx_tx_queue *tx_queue;
 709         struct efx_nic *efx = channel->efx;
 710
 711         if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
 712                 /* Transmit completion */
 713                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
 714                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
 715                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 716                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 717         } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
 718                 /* Rewrite the FIFO write pointer */
 719                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
 720                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 721
 722                 if (efx_dev_registered(efx))
 723                         netif_tx_lock(efx->net_dev);
 724                 falcon_notify_tx_desc(tx_queue);
 725                 if (efx_dev_registered(efx))
 726                         netif_tx_unlock(efx->net_dev);
 727         } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
 728                    EFX_WORKAROUND_10727(efx)) {
 729                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 730         } else {
 731                 EFX_ERR(efx, "channel %d unexpected TX event "
 732                         EFX_QWORD_FMT"\n", channel->channel,
 733                         EFX_QWORD_VAL(*event));
 734         }
 735 }
 736
 737 /* Detect errors included in the rx_evt_pkt_ok bit. */
 738 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 739                                     const efx_qword_t *event,
 740                                     bool *rx_ev_pkt_ok,
 741                                     bool *discard)
 742 {
 743         struct efx_nic *efx = rx_queue->efx;
 744         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 745         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 746         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 747         bool rx_ev_other_err, rx_ev_pause_frm;
 748         bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
 749         unsigned rx_ev_pkt_type;
 750
 751         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
 752         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
 753         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
 754         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
 755         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 756                                                  RX_EV_BUF_OWNER_ID_ERR);
 757         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
 758         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 759                                                   RX_EV_IP_HDR_CHKSUM_ERR);
 760         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 761                                                    RX_EV_TCP_UDP_CHKSUM_ERR);
 762         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
 763         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
 764         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
 765                           0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
 766         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
 767
 768         /* Every error apart from tobe_disc and pause_frm */
 769         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 770                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 771                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 772
 773         /* Count errors that are not in MAC stats. */
 774         if (rx_ev_frm_trunc)
 775                 ++rx_queue->channel->n_rx_frm_trunc;
 776         else if (rx_ev_tobe_disc)
 777                 ++rx_queue->channel->n_rx_tobe_disc;
 778         else if (rx_ev_ip_hdr_chksum_err)
 779                 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
 780         else if (rx_ev_tcp_udp_chksum_err)
 781                 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
 782         if (rx_ev_ip_frag_err)
 783                 ++rx_queue->channel->n_rx_ip_frag_err;
 784
 785         /* The frame must be discarded if any of these are true. */
 786         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 787                     rx_ev_tobe_disc | rx_ev_pause_frm);
 788
 789         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 790          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 791          * to a FIFO overflow.
 792          */
 793 #ifdef EFX_ENABLE_DEBUG
 794         if (rx_ev_other_err) {
 795                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
 796                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 797                             rx_queue->queue, EFX_QWORD_VAL(*event),
 798                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 799                             rx_ev_ip_hdr_chksum_err ?
 800                             " [IP_HDR_CHKSUM_ERR]" : "",
 801                             rx_ev_tcp_udp_chksum_err ?
 802                             " [TCP_UDP_CHKSUM_ERR]" : "",
 803                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 804                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 805                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 806                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 807                             rx_ev_pause_frm ? " [PAUSE]" : "");
 808         }
 809 #endif
 810
 811         if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
 812                      efx->phy_type == PHY_TYPE_10XPRESS))
 813                 tenxpress_crc_err(efx);
 814 }
 815
 816 /* Handle receive events that are not in-order. */
 817 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
 818                                        unsigned index)
 819 {
 820         struct efx_nic *efx = rx_queue->efx;
 821         unsigned expected, dropped;
 822
 823         expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
 824         dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
 825                    FALCON_RXD_RING_MASK);
 826         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
 827                 dropped, index, expected);
 828
 829         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 830                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 831 }
 832
 833 /* Handle a packet received event
 834  *
 835  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
 836  * wrong destination address
 837  * Also "is multicast" and "matches multicast filter" flags can be used to
 838  * discard non-matching multicast packets.
 839  */
 840 static void falcon_handle_rx_event(struct efx_channel *channel,
 841                                    const efx_qword_t *event)
 842 {
 843         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 844         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 845         unsigned expected_ptr;
 846         bool rx_ev_pkt_ok, discard = false, checksummed;
 847         struct efx_rx_queue *rx_queue;
 848         struct efx_nic *efx = channel->efx;
 849
 850         /* Basic packet information */
 851         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
 852         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
 853         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
 854         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
 855         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
 856         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
 857
 858         rx_queue = &efx->rx_queue[channel->channel];
 859
 860         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
 861         expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
 862         if (unlikely(rx_ev_desc_ptr != expected_ptr))
 863                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
 864
 865         if (likely(rx_ev_pkt_ok)) {
 866                 /* If packet is marked as OK and packet type is TCP/IPv4 or
 867                  * UDP/IPv4, then we can rely on the hardware checksum.
 868                  */
 869                 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
 870         } else {
 871                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
 872                                         &discard);
 873                 checksummed = false;
 874         }
 875
 876         /* Detect multicast packets that didn't match the filter */
 877         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
 878         if (rx_ev_mcast_pkt) {
 879                 unsigned int rx_ev_mcast_hash_match =
 880                         EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
 881
 882                 if (unlikely(!rx_ev_mcast_hash_match))
 883                         discard = true;
 884         }
 885
 886         /* Handle received packet */
 887         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
 888                       checksummed, discard);
 889 }
 890
 891 /* Global events are basically PHY events */
 892 static void falcon_handle_global_event(struct efx_channel *channel,
 893                                        efx_qword_t *event)
 894 {
 895         struct efx_nic *efx = channel->efx;
 896         bool is_phy_event = false, handled = false;
 897
 898         /* Check for interrupt on either port.  Some boards have a
 899          * single PHY wired to the interrupt line for port 1. */
 900         if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
 901             EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
 902             EFX_QWORD_FIELD(*event, XG_PHY_INTR))
 903                 is_phy_event = true;
 904
 905         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
 906             EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0))
 907                 is_phy_event = true;
 908
 909         if (is_phy_event) {
 910                 efx->phy_op->clear_interrupt(efx);
 911                 queue_work(efx->workqueue, &efx->reconfigure_work);
 912                 handled = true;
 913         }
 914
 915         if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
 916                 EFX_ERR(efx, "channel %d seen global RX_RESET "
 917                         "event. Resetting.\n", channel->channel);
 918
 919                 atomic_inc(&efx->rx_reset);
 920                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
 921                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 922                 handled = true;
 923         }
 924
 925         if (!handled)
 926                 EFX_ERR(efx, "channel %d unknown global event "
 927                         EFX_QWORD_FMT "\n", channel->channel,
 928                         EFX_QWORD_VAL(*event));
 929 }
 930
 931 static void falcon_handle_driver_event(struct efx_channel *channel,
 932                                        efx_qword_t *event)
 933 {
 934         struct efx_nic *efx = channel->efx;
 935         unsigned int ev_sub_code;
 936         unsigned int ev_sub_data;
 937
 938         ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
 939         ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
 940
 941         switch (ev_sub_code) {
 942         case TX_DESCQ_FLS_DONE_EV_DECODE:
 943                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
 944                           channel->channel, ev_sub_data);
 945                 break;
 946         case RX_DESCQ_FLS_DONE_EV_DECODE:
 947                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
 948                           channel->channel, ev_sub_data);
 949                 break;
 950         case EVQ_INIT_DONE_EV_DECODE:
 951                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
 952                         channel->channel, ev_sub_data);
 953                 break;
 954         case SRM_UPD_DONE_EV_DECODE:
 955                 EFX_TRACE(efx, "channel %d SRAM update done\n",
 956                           channel->channel);
 957                 break;
 958         case WAKE_UP_EV_DECODE:
 959                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
 960                           channel->channel, ev_sub_data);
 961                 break;
 962         case TIMER_EV_DECODE:
 963                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
 964                           channel->channel, ev_sub_data);
 965                 break;
 966         case RX_RECOVERY_EV_DECODE:
 967                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
 968                         "Resetting.\n", channel->channel);
 969                 atomic_inc(&efx->rx_reset);
 970                 efx_schedule_reset(efx,
 971                                    EFX_WORKAROUND_6555(efx) ?
 972                                    RESET_TYPE_RX_RECOVERY :
 973                                    RESET_TYPE_DISABLE);
 974                 break;
 975         case RX_DSC_ERROR_EV_DECODE:
 976                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
 977                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 978                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
 979                 break;
 980         case TX_DSC_ERROR_EV_DECODE:
 981                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
 982                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 983                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 984                 break;
 985         default:
 986                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
 987                           "data %04x\n", channel->channel, ev_sub_code,
 988                           ev_sub_data);
 989                 break;
 990         }
 991 }
 992
 993 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
 994 {
 995         unsigned int read_ptr;
 996         efx_qword_t event, *p_event;
 997         int ev_code;
 998         int rx_packets = 0;
 999
1000         read_ptr = channel->eventq_read_ptr;
1001
1002         do {
1003                 p_event = falcon_event(channel, read_ptr);
1004                 event = *p_event;
1005
1006                 if (!falcon_event_present(&event))
1007                         /* End of events */
1008                         break;
1009
1010                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1011                           channel->channel, EFX_QWORD_VAL(event));
1012
1013                 /* Clear this event by marking it all ones */
1014                 EFX_SET_QWORD(*p_event);
1015
1016                 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1017
1018                 switch (ev_code) {
1019                 case RX_IP_EV_DECODE:
1020                         falcon_handle_rx_event(channel, &event);
1021                         ++rx_packets;
1022                         break;
1023                 case TX_IP_EV_DECODE:
1024                         falcon_handle_tx_event(channel, &event);
1025                         break;
1026                 case DRV_GEN_EV_DECODE:
1027                         channel->eventq_magic
1028                                 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1029                         EFX_LOG(channel->efx, "channel %d received generated "
1030                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1031                                 EFX_QWORD_VAL(event));
1032                         break;
1033                 case GLOBAL_EV_DECODE:
1034                         falcon_handle_global_event(channel, &event);
1035                         break;
1036                 case DRIVER_EV_DECODE:
1037                         falcon_handle_driver_event(channel, &event);
1038                         break;
1039                 default:
1040                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1041                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1042                                 ev_code, EFX_QWORD_VAL(event));
1043                 }
1044
1045                 /* Increment read pointer */
1046                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1047
1048         } while (rx_packets < rx_quota);
1049
1050         channel->eventq_read_ptr = read_ptr;
1051         return rx_packets;
1052 }
1053
1054 void falcon_set_int_moderation(struct efx_channel *channel)
1055 {
1056         efx_dword_t timer_cmd;
1057         struct efx_nic *efx = channel->efx;
1058
1059         /* Set timer register */
1060         if (channel->irq_moderation) {
1061                 /* Round to resolution supported by hardware.  The value we
1062                  * program is based at 0.  So actual interrupt moderation
1063                  * achieved is ((x + 1) * res).
1064                  */
1065                 unsigned int res = 5;
1066                 channel->irq_moderation -= (channel->irq_moderation % res);
1067                 if (channel->irq_moderation < res)
1068                         channel->irq_moderation = res;
1069                 EFX_POPULATE_DWORD_2(timer_cmd,
1070                                      TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1071                                      TIMER_VAL,
1072                                      (channel->irq_moderation / res) - 1);
1073         } else {
1074                 EFX_POPULATE_DWORD_2(timer_cmd,
1075                                      TIMER_MODE, TIMER_MODE_DIS,
1076                                      TIMER_VAL, 0);
1077         }
1078         falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1079                                   channel->channel);
1080
1081 }
1082
1083 /* Allocate buffer table entries for event queue */
1084 int falcon_probe_eventq(struct efx_channel *channel)
1085 {
1086         struct efx_nic *efx = channel->efx;
1087         unsigned int evq_size;
1088
1089         evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1090         return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1091 }
1092
1093 void falcon_init_eventq(struct efx_channel *channel)
1094 {
1095         efx_oword_t evq_ptr;
1096         struct efx_nic *efx = channel->efx;
1097
1098         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1099                 channel->channel, channel->eventq.index,
1100                 channel->eventq.index + channel->eventq.entries - 1);
1101
1102         /* Pin event queue buffer */
1103         falcon_init_special_buffer(efx, &channel->eventq);
1104
1105         /* Fill event queue with all ones (i.e. empty events) */
1106         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1107
1108         /* Push event queue to card */
1109         EFX_POPULATE_OWORD_3(evq_ptr,
1110                              EVQ_EN, 1,
1111                              EVQ_SIZE, FALCON_EVQ_ORDER,
1112                              EVQ_BUF_BASE_ID, channel->eventq.index);
1113         falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1114                            channel->channel);
1115
1116         falcon_set_int_moderation(channel);
1117 }
1118
1119 void falcon_fini_eventq(struct efx_channel *channel)
1120 {
1121         efx_oword_t eventq_ptr;
1122         struct efx_nic *efx = channel->efx;
1123
1124         /* Remove event queue from card */
1125         EFX_ZERO_OWORD(eventq_ptr);
1126         falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1127                            channel->channel);
1128
1129         /* Unpin event queue */
1130         falcon_fini_special_buffer(efx, &channel->eventq);
1131 }
1132
1133 /* Free buffers backing event queue */
1134 void falcon_remove_eventq(struct efx_channel *channel)
1135 {
1136         falcon_free_special_buffer(channel->efx, &channel->eventq);
1137 }
1138
1139
1140 /* Generates a test event on the event queue.  A subsequent call to
1141  * process_eventq() should pick up the event and place the value of
1142  * "magic" into channel->eventq_magic;
1143  */
1144 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1145 {
1146         efx_qword_t test_event;
1147
1148         EFX_POPULATE_QWORD_2(test_event,
1149                              EV_CODE, DRV_GEN_EV_DECODE,
1150                              EVQ_MAGIC, magic);
1151         falcon_generate_event(channel, &test_event);
1152 }
1153
1154 /**************************************************************************
1155  *
1156  * Flush handling
1157  *
1158  **************************************************************************/
1159
1160
1161 static void falcon_poll_flush_events(struct efx_nic *efx)
1162 {
1163         struct efx_channel *channel = &efx->channel[0];
1164         struct efx_tx_queue *tx_queue;
1165         struct efx_rx_queue *rx_queue;
1166         unsigned int read_ptr, i;
1167
1168         read_ptr = channel->eventq_read_ptr;
1169         for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
1170                 efx_qword_t *event = falcon_event(channel, read_ptr);
1171                 int ev_code, ev_sub_code, ev_queue;
1172                 bool ev_failed;
1173                 if (!falcon_event_present(event))
1174                         break;
1175
1176                 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1177                 if (ev_code != DRIVER_EV_DECODE)
1178                         continue;
1179
1180                 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1181                 switch (ev_sub_code) {
1182                 case TX_DESCQ_FLS_DONE_EV_DECODE:
1183                         ev_queue = EFX_QWORD_FIELD(*event,
1184                                                    DRIVER_EV_TX_DESCQ_ID);
1185                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1186                                 tx_queue = efx->tx_queue + ev_queue;
1187                                 tx_queue->flushed = true;
1188                         }
1189                         break;
1190                 case RX_DESCQ_FLS_DONE_EV_DECODE:
1191                         ev_queue = EFX_QWORD_FIELD(*event,
1192                                                    DRIVER_EV_RX_DESCQ_ID);
1193                         ev_failed = EFX_QWORD_FIELD(*event,
1194                                                     DRIVER_EV_RX_FLUSH_FAIL);
1195                         if (ev_queue < efx->n_rx_queues) {
1196                                 rx_queue = efx->rx_queue + ev_queue;
1197
1198                                 /* retry the rx flush */
1199                                 if (ev_failed)
1200                                         falcon_flush_rx_queue(rx_queue);
1201                                 else
1202                                         rx_queue->flushed = true;
1203                         }
1204                         break;
1205                 }
1206
1207                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1208         }
1209 }
1210
1211 /* Handle tx and rx flushes at the same time, since they run in
1212  * parallel in the hardware and there's no reason for us to
1213  * serialise them */
1214 int falcon_flush_queues(struct efx_nic *efx)
1215 {
1216         struct efx_rx_queue *rx_queue;
1217         struct efx_tx_queue *tx_queue;
1218         int i;
1219         bool outstanding;
1220
1221         /* Issue flush requests */
1222         efx_for_each_tx_queue(tx_queue, efx) {
1223                 tx_queue->flushed = false;
1224                 falcon_flush_tx_queue(tx_queue);
1225         }
1226         efx_for_each_rx_queue(rx_queue, efx) {
1227                 rx_queue->flushed = false;
1228                 falcon_flush_rx_queue(rx_queue);
1229         }
1230
1231         /* Poll the evq looking for flush completions. Since we're not pushing
1232          * any more rx or tx descriptors at this point, we're in no danger of
1233          * overflowing the evq whilst we wait */
1234         for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1235                 msleep(FALCON_FLUSH_INTERVAL);
1236                 falcon_poll_flush_events(efx);
1237
1238                 /* Check if every queue has been succesfully flushed */
1239                 outstanding = false;
1240                 efx_for_each_tx_queue(tx_queue, efx)
1241                         outstanding |= !tx_queue->flushed;
1242                 efx_for_each_rx_queue(rx_queue, efx)
1243                         outstanding |= !rx_queue->flushed;
1244                 if (!outstanding)
1245                         return 0;
1246         }
1247
1248         /* Mark the queues as all flushed. We're going to return failure
1249          * leading to a reset, or fake up success anyway. "flushed" now
1250          * indicates that we tried to flush. */
1251         efx_for_each_tx_queue(tx_queue, efx) {
1252                 if (!tx_queue->flushed)
1253                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1254                                 tx_queue->queue);
1255                 tx_queue->flushed = true;
1256         }
1257         efx_for_each_rx_queue(rx_queue, efx) {
1258                 if (!rx_queue->flushed)
1259                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1260                                 rx_queue->queue);
1261                 rx_queue->flushed = true;
1262         }
1263
1264         if (EFX_WORKAROUND_7803(efx))
1265                 return 0;
1266
1267         return -ETIMEDOUT;
1268 }
1269
1270 /**************************************************************************
1271  *
1272  * Falcon hardware interrupts
1273  * The hardware interrupt handler does very little work; all the event
1274  * queue processing is carried out by per-channel tasklets.
1275  *
1276  **************************************************************************/
1277
1278 /* Enable/disable/generate Falcon interrupts */
1279 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1280                                      int force)
1281 {
1282         efx_oword_t int_en_reg_ker;
1283
1284         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1285                              KER_INT_KER, force,
1286                              DRV_INT_EN_KER, enabled);
1287         falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1288 }
1289
1290 void falcon_enable_interrupts(struct efx_nic *efx)
1291 {
1292         efx_oword_t int_adr_reg_ker;
1293         struct efx_channel *channel;
1294
1295         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1296         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1297
1298         /* Program address */
1299         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1300                              NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1301                              INT_ADR_KER, efx->irq_status.dma_addr);
1302         falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1303
1304         /* Enable interrupts */
1305         falcon_interrupts(efx, 1, 0);
1306
1307         /* Force processing of all the channels to get the EVQ RPTRs up to
1308            date */
1309         efx_for_each_channel(channel, efx)
1310                 efx_schedule_channel(channel);
1311 }
1312
1313 void falcon_disable_interrupts(struct efx_nic *efx)
1314 {
1315         /* Disable interrupts */
1316         falcon_interrupts(efx, 0, 0);
1317 }
1318
1319 /* Generate a Falcon test interrupt
1320  * Interrupt must already have been enabled, otherwise nasty things
1321  * may happen.
1322  */
1323 void falcon_generate_interrupt(struct efx_nic *efx)
1324 {
1325         falcon_interrupts(efx, 1, 1);
1326 }
1327
1328 /* Acknowledge a legacy interrupt from Falcon
1329  *
1330  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1331  *
1332  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1333  * BIU. Interrupt acknowledge is read sensitive so must write instead
1334  * (then read to ensure the BIU collector is flushed)
1335  *
1336  * NB most hardware supports MSI interrupts
1337  */
1338 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1339 {
1340         efx_dword_t reg;
1341
1342         EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1343         falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1344         falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1345 }
1346
1347 /* Process a fatal interrupt
1348  * Disable bus mastering ASAP and schedule a reset
1349  */
1350 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1351 {
1352         struct falcon_nic_data *nic_data = efx->nic_data;
1353         efx_oword_t *int_ker = efx->irq_status.addr;
1354         efx_oword_t fatal_intr;
1355         int error, mem_perr;
1356         static int n_int_errors;
1357
1358         falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1359         error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1360
1361         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1362                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1363                 EFX_OWORD_VAL(fatal_intr),
1364                 error ? "disabling bus mastering" : "no recognised error");
1365         if (error == 0)
1366                 goto out;
1367
1368         /* If this is a memory parity error dump which blocks are offending */
1369         mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1370         if (mem_perr) {
1371                 efx_oword_t reg;
1372                 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1373                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1374                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1375         }
1376
1377         /* Disable both devices */
1378         pci_disable_device(efx->pci_dev);
1379         if (FALCON_IS_DUAL_FUNC(efx))
1380                 pci_disable_device(nic_data->pci_dev2);
1381         falcon_disable_interrupts(efx);
1382
1383         if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1384                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1385                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1386         } else {
1387                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1388                         "NIC will be disabled\n");
1389                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1390         }
1391 out:
1392         return IRQ_HANDLED;
1393 }
1394
1395 /* Handle a legacy interrupt from Falcon
1396  * Acknowledges the interrupt and schedule event queue processing.
1397  */
1398 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1399 {
1400         struct efx_nic *efx = dev_id;
1401         efx_oword_t *int_ker = efx->irq_status.addr;
1402         struct efx_channel *channel;
1403         efx_dword_t reg;
1404         u32 queues;
1405         int syserr;
1406
1407         /* Read the ISR which also ACKs the interrupts */
1408         falcon_readl(efx, &reg, INT_ISR0_B0);
1409         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1410
1411         /* Check to see if we have a serious error condition */
1412         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1413         if (unlikely(syserr))
1414                 return falcon_fatal_interrupt(efx);
1415
1416         if (queues == 0)
1417                 return IRQ_NONE;
1418
1419         efx->last_irq_cpu = raw_smp_processor_id();
1420         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1421                   irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1422
1423         /* Schedule processing of any interrupting queues */
1424         channel = &efx->channel[0];
1425         while (queues) {
1426                 if (queues & 0x01)
1427                         efx_schedule_channel(channel);
1428                 channel++;
1429                 queues >>= 1;
1430         }
1431
1432         return IRQ_HANDLED;
1433 }
1434
1435
1436 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1437 {
1438         struct efx_nic *efx = dev_id;
1439         efx_oword_t *int_ker = efx->irq_status.addr;
1440         struct efx_channel *channel;
1441         int syserr;
1442         int queues;
1443
1444         /* Check to see if this is our interrupt.  If it isn't, we
1445          * exit without having touched the hardware.
1446          */
1447         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1448                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1449                           raw_smp_processor_id());
1450                 return IRQ_NONE;
1451         }
1452         efx->last_irq_cpu = raw_smp_processor_id();
1453         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1454                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1455
1456         /* Check to see if we have a serious error condition */
1457         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1458         if (unlikely(syserr))
1459                 return falcon_fatal_interrupt(efx);
1460
1461         /* Determine interrupting queues, clear interrupt status
1462          * register and acknowledge the device interrupt.
1463          */
1464         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1465         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1466         EFX_ZERO_OWORD(*int_ker);
1467         wmb(); /* Ensure the vector is cleared before interrupt ack */
1468         falcon_irq_ack_a1(efx);
1469
1470         /* Schedule processing of any interrupting queues */
1471         channel = &efx->channel[0];
1472         while (queues) {
1473                 if (queues & 0x01)
1474                         efx_schedule_channel(channel);
1475                 channel++;
1476                 queues >>= 1;
1477         }
1478
1479         return IRQ_HANDLED;
1480 }
1481
1482 /* Handle an MSI interrupt from Falcon
1483  *
1484  * Handle an MSI hardware interrupt.  This routine schedules event
1485  * queue processing.  No interrupt acknowledgement cycle is necessary.
1486  * Also, we never need to check that the interrupt is for us, since
1487  * MSI interrupts cannot be shared.
1488  */
1489 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1490 {
1491         struct efx_channel *channel = dev_id;
1492         struct efx_nic *efx = channel->efx;
1493         efx_oword_t *int_ker = efx->irq_status.addr;
1494         int syserr;
1495
1496         efx->last_irq_cpu = raw_smp_processor_id();
1497         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1498                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1499
1500         /* Check to see if we have a serious error condition */
1501         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1502         if (unlikely(syserr))
1503                 return falcon_fatal_interrupt(efx);
1504
1505         /* Schedule processing of the channel */
1506         efx_schedule_channel(channel);
1507
1508         return IRQ_HANDLED;
1509 }
1510
1511
1512 /* Setup RSS indirection table.
1513  * This maps from the hash value of the packet to RXQ
1514  */
1515 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1516 {
1517         int i = 0;
1518         unsigned long offset;
1519         efx_dword_t dword;
1520
1521         if (falcon_rev(efx) < FALCON_REV_B0)
1522                 return;
1523
1524         for (offset = RX_RSS_INDIR_TBL_B0;
1525              offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1526              offset += 0x10) {
1527                 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1528                                      i % efx->n_rx_queues);
1529                 falcon_writel(efx, &dword, offset);
1530                 i++;
1531         }
1532 }
1533
1534 /* Hook interrupt handler(s)
1535  * Try MSI and then legacy interrupts.
1536  */
1537 int falcon_init_interrupt(struct efx_nic *efx)
1538 {
1539         struct efx_channel *channel;
1540         int rc;
1541
1542         if (!EFX_INT_MODE_USE_MSI(efx)) {
1543                 irq_handler_t handler;
1544                 if (falcon_rev(efx) >= FALCON_REV_B0)
1545                         handler = falcon_legacy_interrupt_b0;
1546                 else
1547                         handler = falcon_legacy_interrupt_a1;
1548
1549                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1550                                  efx->name, efx);
1551                 if (rc) {
1552                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1553                                 efx->pci_dev->irq);
1554                         goto fail1;
1555                 }
1556                 return 0;
1557         }
1558
1559         /* Hook MSI or MSI-X interrupt */
1560         efx_for_each_channel(channel, efx) {
1561                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1562                                  IRQF_PROBE_SHARED, /* Not shared */
1563                                  efx->name, channel);
1564                 if (rc) {
1565                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1566                         goto fail2;
1567                 }
1568         }
1569
1570         return 0;
1571
1572  fail2:
1573         efx_for_each_channel(channel, efx)
1574                 free_irq(channel->irq, channel);
1575  fail1:
1576         return rc;
1577 }
1578
1579 void falcon_fini_interrupt(struct efx_nic *efx)
1580 {
1581         struct efx_channel *channel;
1582         efx_oword_t reg;
1583
1584         /* Disable MSI/MSI-X interrupts */
1585         efx_for_each_channel(channel, efx) {
1586                 if (channel->irq)
1587                         free_irq(channel->irq, channel);
1588         }
1589
1590         /* ACK legacy interrupt */
1591         if (falcon_rev(efx) >= FALCON_REV_B0)
1592                 falcon_read(efx, &reg, INT_ISR0_B0);
1593         else
1594                 falcon_irq_ack_a1(efx);
1595
1596         /* Disable legacy interrupt */
1597         if (efx->legacy_irq)
1598                 free_irq(efx->legacy_irq, efx);
1599 }
1600
1601 /**************************************************************************
1602  *
1603  * EEPROM/flash
1604  *
1605  **************************************************************************
1606  */
1607
1608 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1609
1610 /* Wait for SPI command completion */
1611 static int falcon_spi_wait(struct efx_nic *efx)
1612 {
1613         unsigned long timeout = jiffies + DIV_ROUND_UP(HZ, 10);
1614         efx_oword_t reg;
1615         bool cmd_en, timer_active;
1616
1617         for (;;) {
1618                 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1619                 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1620                 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1621                 if (!cmd_en && !timer_active)
1622                         return 0;
1623                 if (time_after_eq(jiffies, timeout)) {
1624                         EFX_ERR(efx, "timed out waiting for SPI\n");
1625                         return -ETIMEDOUT;
1626                 }
1627                 cpu_relax();
1628         }
1629 }
1630
1631 int falcon_spi_cmd(const struct efx_spi_device *spi,
1632                    unsigned int command, int address,
1633                    const void *in, void *out, size_t len)
1634 {
1635         struct efx_nic *efx = spi->efx;
1636         bool addressed = (address >= 0);
1637         bool reading = (out != NULL);
1638         efx_oword_t reg;
1639         int rc;
1640
1641         /* Input validation */
1642         if (len > FALCON_SPI_MAX_LEN)
1643                 return -EINVAL;
1644         BUG_ON(!mutex_is_locked(&efx->spi_lock));
1645
1646         /* Check SPI not currently being accessed */
1647         rc = falcon_spi_wait(efx);
1648         if (rc)
1649                 return rc;
1650
1651         /* Program address register, if we have an address */
1652         if (addressed) {
1653                 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1654                 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1655         }
1656
1657         /* Program data register, if we have data */
1658         if (in != NULL) {
1659                 memcpy(&reg, in, len);
1660                 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1661         }
1662
1663         /* Issue read/write command */
1664         EFX_POPULATE_OWORD_7(reg,
1665                              EE_SPI_HCMD_CMD_EN, 1,
1666                              EE_SPI_HCMD_SF_SEL, spi->device_id,
1667                              EE_SPI_HCMD_DABCNT, len,
1668                              EE_SPI_HCMD_READ, reading,
1669                              EE_SPI_HCMD_DUBCNT, 0,
1670                              EE_SPI_HCMD_ADBCNT,
1671                              (addressed ? spi->addr_len : 0),
1672                              EE_SPI_HCMD_ENC, command);
1673         falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1674
1675         /* Wait for read/write to complete */
1676         rc = falcon_spi_wait(efx);
1677         if (rc)
1678                 return rc;
1679
1680         /* Read data */
1681         if (out != NULL) {
1682                 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1683                 memcpy(out, &reg, len);
1684         }
1685
1686         return 0;
1687 }
1688
1689 static size_t
1690 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1691 {
1692         return min(FALCON_SPI_MAX_LEN,
1693                    (spi->block_size - (start & (spi->block_size - 1))));
1694 }
1695
1696 static inline u8
1697 efx_spi_munge_command(const struct efx_spi_device *spi,
1698                       const u8 command, const unsigned int address)
1699 {
1700         return command | (((address >> 8) & spi->munge_address) << 3);
1701 }
1702
1703 int falcon_spi_fast_wait(const struct efx_spi_device *spi)
1704 {
1705         u8 status;
1706         int i, rc;
1707
1708         /* Wait up to 1000us for flash/EEPROM to finish a fast operation. */
1709         for (i = 0; i < 50; i++) {
1710                 udelay(20);
1711
1712                 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1713                                     &status, sizeof(status));
1714                 if (rc)
1715                         return rc;
1716                 if (!(status & SPI_STATUS_NRDY))
1717                         return 0;
1718         }
1719         EFX_ERR(spi->efx,
1720                 "timed out waiting for device %d last status=0x%02x\n",
1721                 spi->device_id, status);
1722         return -ETIMEDOUT;
1723 }
1724
1725 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1726                     size_t len, size_t *retlen, u8 *buffer)
1727 {
1728         size_t block_len, pos = 0;
1729         unsigned int command;
1730         int rc = 0;
1731
1732         while (pos < len) {
1733                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1734
1735                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1736                 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1737                                     buffer + pos, block_len);
1738                 if (rc)
1739                         break;
1740                 pos += block_len;
1741
1742                 /* Avoid locking up the system */
1743                 cond_resched();
1744                 if (signal_pending(current)) {
1745                         rc = -EINTR;
1746                         break;
1747                 }
1748         }
1749
1750         if (retlen)
1751                 *retlen = pos;
1752         return rc;
1753 }
1754
1755 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1756                      size_t len, size_t *retlen, const u8 *buffer)
1757 {
1758         u8 verify_buffer[FALCON_SPI_MAX_LEN];
1759         size_t block_len, pos = 0;
1760         unsigned int command;
1761         int rc = 0;
1762
1763         while (pos < len) {
1764                 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1765                 if (rc)
1766                         break;
1767
1768                 block_len = min(len - pos,
1769                                 falcon_spi_write_limit(spi, start + pos));
1770                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1771                 rc = falcon_spi_cmd(spi, command, start + pos,
1772                                     buffer + pos, NULL, block_len);
1773                 if (rc)
1774                         break;
1775
1776                 rc = falcon_spi_fast_wait(spi);
1777                 if (rc)
1778                         break;
1779
1780                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1781                 rc = falcon_spi_cmd(spi, command, start + pos,
1782                                     NULL, verify_buffer, block_len);
1783                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1784                         rc = -EIO;
1785                         break;
1786                 }
1787
1788                 pos += block_len;
1789
1790                 /* Avoid locking up the system */
1791                 cond_resched();
1792                 if (signal_pending(current)) {
1793                         rc = -EINTR;
1794                         break;
1795                 }
1796         }
1797
1798         if (retlen)
1799                 *retlen = pos;
1800         return rc;
1801 }
1802
1803 /**************************************************************************
1804  *
1805  * MAC wrapper
1806  *
1807  **************************************************************************
1808  */
1809 void falcon_drain_tx_fifo(struct efx_nic *efx)
1810 {
1811         efx_oword_t temp;
1812         int count;
1813
1814         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1815             (efx->loopback_mode != LOOPBACK_NONE))
1816                 return;
1817
1818         falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1819         /* There is no point in draining more than once */
1820         if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1821                 return;
1822
1823         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1824          * the drain sequence with the statistics fetch */
1825         spin_lock(&efx->stats_lock);
1826
1827         EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1828         falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1829
1830         /* Reset the MAC and EM block. */
1831         falcon_read(efx, &temp, GLB_CTL_REG_KER);
1832         EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1833         EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1834         EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1835         falcon_write(efx, &temp, GLB_CTL_REG_KER);
1836
1837         count = 0;
1838         while (1) {
1839                 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1840                 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1841                     !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1842                     !EFX_OWORD_FIELD(temp, RST_EM)) {
1843                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1844                                 count);
1845                         break;
1846                 }
1847                 if (count > 20) {
1848                         EFX_ERR(efx, "MAC reset failed\n");
1849                         break;
1850                 }
1851                 count++;
1852                 udelay(10);
1853         }
1854
1855         spin_unlock(&efx->stats_lock);
1856
1857         /* If we've reset the EM block and the link is up, then
1858          * we'll have to kick the XAUI link so the PHY can recover */
1859         if (efx->link_up && EFX_WORKAROUND_5147(efx))
1860                 falcon_reset_xaui(efx);
1861 }
1862
1863 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1864 {
1865         efx_oword_t temp;
1866
1867         if (falcon_rev(efx) < FALCON_REV_B0)
1868                 return;
1869
1870         /* Isolate the MAC -> RX */
1871         falcon_read(efx, &temp, RX_CFG_REG_KER);
1872         EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1873         falcon_write(efx, &temp, RX_CFG_REG_KER);
1874
1875         if (!efx->link_up)
1876                 falcon_drain_tx_fifo(efx);
1877 }
1878
1879 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1880 {
1881         efx_oword_t reg;
1882         int link_speed;
1883         bool tx_fc;
1884
1885         if (efx->link_options & GM_LPA_10000)
1886                 link_speed = 0x3;
1887         else if (efx->link_options & GM_LPA_1000)
1888                 link_speed = 0x2;
1889         else if (efx->link_options & GM_LPA_100)
1890                 link_speed = 0x1;
1891         else
1892                 link_speed = 0x0;
1893         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1894          * as advertised.  Disable to ensure packets are not
1895          * indefinitely held and TX queue can be flushed at any point
1896          * while the link is down. */
1897         EFX_POPULATE_OWORD_5(reg,
1898                              MAC_XOFF_VAL, 0xffff /* max pause time */,
1899                              MAC_BCAD_ACPT, 1,
1900                              MAC_UC_PROM, efx->promiscuous,
1901                              MAC_LINK_STATUS, 1, /* always set */
1902                              MAC_SPEED, link_speed);
1903         /* On B0, MAC backpressure can be disabled and packets get
1904          * discarded. */
1905         if (falcon_rev(efx) >= FALCON_REV_B0) {
1906                 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1907                                     !efx->link_up);
1908         }
1909
1910         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1911
1912         /* Restore the multicast hash registers. */
1913         falcon_set_multicast_hash(efx);
1914
1915         /* Transmission of pause frames when RX crosses the threshold is
1916          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1917          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1918         tx_fc = !!(efx->flow_control & EFX_FC_TX);
1919         falcon_read(efx, &reg, RX_CFG_REG_KER);
1920         EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1921
1922         /* Unisolate the MAC -> RX */
1923         if (falcon_rev(efx) >= FALCON_REV_B0)
1924                 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1925         falcon_write(efx, &reg, RX_CFG_REG_KER);
1926 }
1927
1928 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1929 {
1930         efx_oword_t reg;
1931         u32 *dma_done;
1932         int i;
1933
1934         if (disable_dma_stats)
1935                 return 0;
1936
1937         /* Statistics fetch will fail if the MAC is in TX drain */
1938         if (falcon_rev(efx) >= FALCON_REV_B0) {
1939                 efx_oword_t temp;
1940                 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1941                 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1942                         return 0;
1943         }
1944
1945         dma_done = (efx->stats_buffer.addr + done_offset);
1946         *dma_done = FALCON_STATS_NOT_DONE;
1947         wmb(); /* ensure done flag is clear */
1948
1949         /* Initiate DMA transfer of stats */
1950         EFX_POPULATE_OWORD_2(reg,
1951                              MAC_STAT_DMA_CMD, 1,
1952                              MAC_STAT_DMA_ADR,
1953                              efx->stats_buffer.dma_addr);
1954         falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1955
1956         /* Wait for transfer to complete */
1957         for (i = 0; i < 400; i++) {
1958                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
1959                         rmb(); /* Ensure the stats are valid. */
1960                         return 0;
1961                 }
1962                 udelay(10);
1963         }
1964
1965         EFX_ERR(efx, "timed out waiting for statistics\n");
1966         return -ETIMEDOUT;
1967 }
1968
1969 /**************************************************************************
1970  *
1971  * PHY access via GMII
1972  *
1973  **************************************************************************
1974  */
1975
1976 /* Use the top bit of the MII PHY id to indicate the PHY type
1977  * (1G/10G), with the remaining bits as the actual PHY id.
1978  *
1979  * This allows us to avoid leaking information from the mii_if_info
1980  * structure into other data structures.
1981  */
1982 #define FALCON_PHY_ID_ID_WIDTH  EFX_WIDTH(MD_PRT_DEV_ADR)
1983 #define FALCON_PHY_ID_ID_MASK   ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1984 #define FALCON_PHY_ID_WIDTH     (FALCON_PHY_ID_ID_WIDTH + 1)
1985 #define FALCON_PHY_ID_MASK      ((1 << FALCON_PHY_ID_WIDTH) - 1)
1986 #define FALCON_PHY_ID_10G       (1 << (FALCON_PHY_ID_WIDTH - 1))
1987
1988
1989 /* Packing the clause 45 port and device fields into a single value */
1990 #define MD_PRT_ADR_COMP_LBN   (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1991 #define MD_PRT_ADR_COMP_WIDTH  MD_PRT_ADR_WIDTH
1992 #define MD_DEV_ADR_COMP_LBN    0
1993 #define MD_DEV_ADR_COMP_WIDTH  MD_DEV_ADR_WIDTH
1994
1995
1996 /* Wait for GMII access to complete */
1997 static int falcon_gmii_wait(struct efx_nic *efx)
1998 {
1999         efx_dword_t md_stat;
2000         int count;
2001
2002         for (count = 0; count < 1000; count++) {        /* wait upto 10ms */
2003                 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2004                 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2005                         if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2006                             EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2007                                 EFX_ERR(efx, "error from GMII access "
2008                                         EFX_DWORD_FMT"\n",
2009                                         EFX_DWORD_VAL(md_stat));
2010                                 return -EIO;
2011                         }
2012                         return 0;
2013                 }
2014                 udelay(10);
2015         }
2016         EFX_ERR(efx, "timed out waiting for GMII\n");
2017         return -ETIMEDOUT;
2018 }
2019
2020 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2021 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2022                               int addr, int value)
2023 {
2024         struct efx_nic *efx = netdev_priv(net_dev);
2025         unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2026         efx_oword_t reg;
2027
2028         /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2029          * chosen so that the only current user, Falcon, can take the
2030          * packed value and use them directly.
2031          * Fail to build if this assumption is broken.
2032          */
2033         BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2034         BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2035         BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2036         BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2037
2038         if (phy_id2 == PHY_ADDR_INVALID)
2039                 return;
2040
2041         /* See falcon_mdio_read for an explanation. */
2042         if (!(phy_id & FALCON_PHY_ID_10G)) {
2043                 int mmd = ffs(efx->phy_op->mmds) - 1;
2044                 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2045                 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2046                         & FALCON_PHY_ID_ID_MASK;
2047         }
2048
2049         EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2050                     addr, value);
2051
2052         spin_lock_bh(&efx->phy_lock);
2053
2054         /* Check MII not currently being accessed */
2055         if (falcon_gmii_wait(efx) != 0)
2056                 goto out;
2057
2058         /* Write the address/ID register */
2059         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2060         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2061
2062         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2063         falcon_write(efx, &reg, MD_ID_REG_KER);
2064
2065         /* Write data */
2066         EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2067         falcon_write(efx, &reg, MD_TXD_REG_KER);
2068
2069         EFX_POPULATE_OWORD_2(reg,
2070                              MD_WRC, 1,
2071                              MD_GC, 0);
2072         falcon_write(efx, &reg, MD_CS_REG_KER);
2073
2074         /* Wait for data to be written */
2075         if (falcon_gmii_wait(efx) != 0) {
2076                 /* Abort the write operation */
2077                 EFX_POPULATE_OWORD_2(reg,
2078                                      MD_WRC, 0,
2079                                      MD_GC, 1);
2080                 falcon_write(efx, &reg, MD_CS_REG_KER);
2081                 udelay(10);
2082         }
2083
2084  out:
2085         spin_unlock_bh(&efx->phy_lock);
2086 }
2087
2088 /* Reads a GMII register from a PHY connected to Falcon.  If no value
2089  * could be read, -1 will be returned. */
2090 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2091 {
2092         struct efx_nic *efx = netdev_priv(net_dev);
2093         unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2094         efx_oword_t reg;
2095         int value = -1;
2096
2097         if (phy_addr == PHY_ADDR_INVALID)
2098                 return -1;
2099
2100         /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2101          * but the generic Linux code does not make any distinction or have
2102          * any state for this.
2103          * We spot the case where someone tried to talk 22 to a 45 PHY and
2104          * redirect the request to the lowest numbered MMD as a clause45
2105          * request. This is enough to allow simple queries like id and link
2106          * state to succeed. TODO: We may need to do more in future.
2107          */
2108         if (!(phy_id & FALCON_PHY_ID_10G)) {
2109                 int mmd = ffs(efx->phy_op->mmds) - 1;
2110                 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2111                 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2112                         & FALCON_PHY_ID_ID_MASK;
2113         }
2114
2115         spin_lock_bh(&efx->phy_lock);
2116
2117         /* Check MII not currently being accessed */
2118         if (falcon_gmii_wait(efx) != 0)
2119                 goto out;
2120
2121         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2122         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2123
2124         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2125         falcon_write(efx, &reg, MD_ID_REG_KER);
2126
2127         /* Request data to be read */
2128         EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2129         falcon_write(efx, &reg, MD_CS_REG_KER);
2130
2131         /* Wait for data to become available */
2132         value = falcon_gmii_wait(efx);
2133         if (value == 0) {
2134                 falcon_read(efx, &reg, MD_RXD_REG_KER);
2135                 value = EFX_OWORD_FIELD(reg, MD_RXD);
2136                 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2137                             phy_id, addr, value);
2138         } else {
2139                 /* Abort the read operation */
2140                 EFX_POPULATE_OWORD_2(reg,
2141                                      MD_RIC, 0,
2142                                      MD_GC, 1);
2143                 falcon_write(efx, &reg, MD_CS_REG_KER);
2144
2145                 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2146                         "error %d\n", phy_id, addr, value);
2147         }
2148
2149  out:
2150         spin_unlock_bh(&efx->phy_lock);
2151
2152         return value;
2153 }
2154
2155 static void falcon_init_mdio(struct mii_if_info *gmii)
2156 {
2157         gmii->mdio_read = falcon_mdio_read;
2158         gmii->mdio_write = falcon_mdio_write;
2159         gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2160         gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2161 }
2162
2163 static int falcon_probe_phy(struct efx_nic *efx)
2164 {
2165         switch (efx->phy_type) {
2166         case PHY_TYPE_10XPRESS:
2167                 efx->phy_op = &falcon_tenxpress_phy_ops;
2168                 break;
2169         case PHY_TYPE_XFP:
2170                 efx->phy_op = &falcon_xfp_phy_ops;
2171                 break;
2172         default:
2173                 EFX_ERR(efx, "Unknown PHY type %d\n",
2174                         efx->phy_type);
2175                 return -1;
2176         }
2177
2178         efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
2179         return 0;
2180 }
2181
2182 /* This call is responsible for hooking in the MAC and PHY operations */
2183 int falcon_probe_port(struct efx_nic *efx)
2184 {
2185         int rc;
2186
2187         /* Hook in PHY operations table */
2188         rc = falcon_probe_phy(efx);
2189         if (rc)
2190                 return rc;
2191
2192         /* Set up GMII structure for PHY */
2193         efx->mii.supports_gmii = true;
2194         falcon_init_mdio(&efx->mii);
2195
2196         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2197         if (falcon_rev(efx) >= FALCON_REV_B0)
2198                 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2199         else
2200                 efx->flow_control = EFX_FC_RX;
2201
2202         /* Allocate buffer for stats */
2203         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2204                                  FALCON_MAC_STATS_SIZE);
2205         if (rc)
2206                 return rc;
2207         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2208                 (unsigned long long)efx->stats_buffer.dma_addr,
2209                 efx->stats_buffer.addr,
2210                 virt_to_phys(efx->stats_buffer.addr));
2211
2212         return 0;
2213 }
2214
2215 void falcon_remove_port(struct efx_nic *efx)
2216 {
2217         falcon_free_buffer(efx, &efx->stats_buffer);
2218 }
2219
2220 /**************************************************************************
2221  *
2222  * Multicast filtering
2223  *
2224  **************************************************************************
2225  */
2226
2227 void falcon_set_multicast_hash(struct efx_nic *efx)
2228 {
2229         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2230
2231         /* Broadcast packets go through the multicast hash filter.
2232          * ether_crc_le() of the broadcast address is 0xbe2612ff
2233          * so we always add bit 0xff to the mask.
2234          */
2235         set_bit_le(0xff, mc_hash->byte);
2236
2237         falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2238         falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2239 }
2240
2241
2242 /**************************************************************************
2243  *
2244  * Falcon test code
2245  *
2246  **************************************************************************/
2247
2248 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2249 {
2250         struct falcon_nvconfig *nvconfig;
2251         struct efx_spi_device *spi;
2252         void *region;
2253         int rc, magic_num, struct_ver;
2254         __le16 *word, *limit;
2255         u32 csum;
2256
2257         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2258         if (!region)
2259                 return -ENOMEM;
2260         nvconfig = region + NVCONFIG_OFFSET;
2261
2262         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2263         mutex_lock(&efx->spi_lock);
2264         rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2265         mutex_unlock(&efx->spi_lock);
2266         if (rc) {
2267                 EFX_ERR(efx, "Failed to read %s\n",
2268                         efx->spi_flash ? "flash" : "EEPROM");
2269                 rc = -EIO;
2270                 goto out;
2271         }
2272
2273         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2274         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2275
2276         rc = -EINVAL;
2277         if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2278                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2279                 goto out;
2280         }
2281         if (struct_ver < 2) {
2282                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2283                 goto out;
2284         } else if (struct_ver < 4) {
2285                 word = &nvconfig->board_magic_num;
2286                 limit = (__le16 *) (nvconfig + 1);
2287         } else {
2288                 word = region;
2289                 limit = region + FALCON_NVCONFIG_END;
2290         }
2291         for (csum = 0; word < limit; ++word)
2292                 csum += le16_to_cpu(*word);
2293
2294         if (~csum & 0xffff) {
2295                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2296                 goto out;
2297         }
2298
2299         rc = 0;
2300         if (nvconfig_out)
2301                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2302
2303  out:
2304         kfree(region);
2305         return rc;
2306 }
2307
2308 /* Registers tested in the falcon register test */
2309 static struct {
2310         unsigned address;
2311         efx_oword_t mask;
2312 } efx_test_registers[] = {
2313         { ADR_REGION_REG_KER,
2314           EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2315         { RX_CFG_REG_KER,
2316           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2317         { TX_CFG_REG_KER,
2318           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2319         { TX_CFG2_REG_KER,
2320           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2321         { MAC0_CTRL_REG_KER,
2322           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2323         { SRM_TX_DC_CFG_REG_KER,
2324           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2325         { RX_DC_CFG_REG_KER,
2326           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2327         { RX_DC_PF_WM_REG_KER,
2328           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2329         { DP_CTRL_REG,
2330           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2331         { XM_GLB_CFG_REG,
2332           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2333         { XM_TX_CFG_REG,
2334           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2335         { XM_RX_CFG_REG,
2336           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2337         { XM_RX_PARAM_REG,
2338           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2339         { XM_FC_REG,
2340           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2341         { XM_ADR_LO_REG,
2342           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2343         { XX_SD_CTL_REG,
2344           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2345 };
2346
2347 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2348                                      const efx_oword_t *mask)
2349 {
2350         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2351                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2352 }
2353
2354 int falcon_test_registers(struct efx_nic *efx)
2355 {
2356         unsigned address = 0, i, j;
2357         efx_oword_t mask, imask, original, reg, buf;
2358
2359         /* Falcon should be in loopback to isolate the XMAC from the PHY */
2360         WARN_ON(!LOOPBACK_INTERNAL(efx));
2361
2362         for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2363                 address = efx_test_registers[i].address;
2364                 mask = imask = efx_test_registers[i].mask;
2365                 EFX_INVERT_OWORD(imask);
2366
2367                 falcon_read(efx, &original, address);
2368
2369                 /* bit sweep on and off */
2370                 for (j = 0; j < 128; j++) {
2371                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
2372                                 continue;
2373
2374                         /* Test this testable bit can be set in isolation */
2375                         EFX_AND_OWORD(reg, original, mask);
2376                         EFX_SET_OWORD32(reg, j, j, 1);
2377
2378                         falcon_write(efx, &reg, address);
2379                         falcon_read(efx, &buf, address);
2380
2381                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2382                                 goto fail;
2383
2384                         /* Test this testable bit can be cleared in isolation */
2385                         EFX_OR_OWORD(reg, original, mask);
2386                         EFX_SET_OWORD32(reg, j, j, 0);
2387
2388                         falcon_write(efx, &reg, address);
2389                         falcon_read(efx, &buf, address);
2390
2391                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2392                                 goto fail;
2393                 }
2394
2395                 falcon_write(efx, &original, address);
2396         }
2397
2398         return 0;
2399
2400 fail:
2401         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2402                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2403                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2404         return -EIO;
2405 }
2406
2407 /**************************************************************************
2408  *
2409  * Device reset
2410  *
2411  **************************************************************************
2412  */
2413
2414 /* Resets NIC to known state.  This routine must be called in process
2415  * context and is allowed to sleep. */
2416 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2417 {
2418         struct falcon_nic_data *nic_data = efx->nic_data;
2419         efx_oword_t glb_ctl_reg_ker;
2420         int rc;
2421
2422         EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2423
2424         /* Initiate device reset */
2425         if (method == RESET_TYPE_WORLD) {
2426                 rc = pci_save_state(efx->pci_dev);
2427                 if (rc) {
2428                         EFX_ERR(efx, "failed to backup PCI state of primary "
2429                                 "function prior to hardware reset\n");
2430                         goto fail1;
2431                 }
2432                 if (FALCON_IS_DUAL_FUNC(efx)) {
2433                         rc = pci_save_state(nic_data->pci_dev2);
2434                         if (rc) {
2435                                 EFX_ERR(efx, "failed to backup PCI state of "
2436                                         "secondary function prior to "
2437                                         "hardware reset\n");
2438                                 goto fail2;
2439                         }
2440                 }
2441
2442                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2443                                      EXT_PHY_RST_DUR, 0x7,
2444                                      SWRST, 1);
2445         } else {
2446                 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2447                                  EXCLUDE_FROM_RESET : 0);
2448
2449                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2450                                      EXT_PHY_RST_CTL, reset_phy,
2451                                      PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2452                                      PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2453                                      PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2454                                      EE_RST_CTL, EXCLUDE_FROM_RESET,
2455                                      EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2456                                      SWRST, 1);
2457         }
2458         falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2459
2460         EFX_LOG(efx, "waiting for hardware reset\n");
2461         schedule_timeout_uninterruptible(HZ / 20);
2462
2463         /* Restore PCI configuration if needed */
2464         if (method == RESET_TYPE_WORLD) {
2465                 if (FALCON_IS_DUAL_FUNC(efx)) {
2466                         rc = pci_restore_state(nic_data->pci_dev2);
2467                         if (rc) {
2468                                 EFX_ERR(efx, "failed to restore PCI config for "
2469                                         "the secondary function\n");
2470                                 goto fail3;
2471                         }
2472                 }
2473                 rc = pci_restore_state(efx->pci_dev);
2474                 if (rc) {
2475                         EFX_ERR(efx, "failed to restore PCI config for the "
2476                                 "primary function\n");
2477                         goto fail4;
2478                 }
2479                 EFX_LOG(efx, "successfully restored PCI config\n");
2480         }
2481
2482         /* Assert that reset complete */
2483         falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2484         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2485                 rc = -ETIMEDOUT;
2486                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2487                 goto fail5;
2488         }
2489         EFX_LOG(efx, "hardware reset complete\n");
2490
2491         return 0;
2492
2493         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2494 fail2:
2495 fail3:
2496         pci_restore_state(efx->pci_dev);
2497 fail1:
2498 fail4:
2499 fail5:
2500         return rc;
2501 }
2502
2503 /* Zeroes out the SRAM contents.  This routine must be called in
2504  * process context and is allowed to sleep.
2505  */
2506 static int falcon_reset_sram(struct efx_nic *efx)
2507 {
2508         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2509         int count;
2510
2511         /* Set the SRAM wake/sleep GPIO appropriately. */
2512         falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2513         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2514         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2515         falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2516
2517         /* Initiate SRAM reset */
2518         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2519                              SRAM_OOB_BT_INIT_EN, 1,
2520                              SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2521         falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2522
2523         /* Wait for SRAM reset to complete */
2524         count = 0;
2525         do {
2526                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2527
2528                 /* SRAM reset is slow; expect around 16ms */
2529                 schedule_timeout_uninterruptible(HZ / 50);
2530
2531                 /* Check for reset complete */
2532                 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2533                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2534                         EFX_LOG(efx, "SRAM reset complete\n");
2535
2536                         return 0;
2537                 }
2538         } while (++count < 20); /* wait upto 0.4 sec */
2539
2540         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2541         return -ETIMEDOUT;
2542 }
2543
2544 static int falcon_spi_device_init(struct efx_nic *efx,
2545                                   struct efx_spi_device **spi_device_ret,
2546                                   unsigned int device_id, u32 device_type)
2547 {
2548         struct efx_spi_device *spi_device;
2549
2550         if (device_type != 0) {
2551                 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2552                 if (!spi_device)
2553                         return -ENOMEM;
2554                 spi_device->device_id = device_id;
2555                 spi_device->size =
2556                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2557                 spi_device->addr_len =
2558                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2559                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2560                                              spi_device->addr_len == 1);
2561                 spi_device->erase_command =
2562                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2563                 spi_device->erase_size =
2564                         1 << SPI_DEV_TYPE_FIELD(device_type,
2565                                                 SPI_DEV_TYPE_ERASE_SIZE);
2566                 spi_device->block_size =
2567                         1 << SPI_DEV_TYPE_FIELD(device_type,
2568                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2569
2570                 spi_device->efx = efx;
2571         } else {
2572                 spi_device = NULL;
2573         }
2574
2575         kfree(*spi_device_ret);
2576         *spi_device_ret = spi_device;
2577         return 0;
2578 }
2579
2580
2581 static void falcon_remove_spi_devices(struct efx_nic *efx)
2582 {
2583         kfree(efx->spi_eeprom);
2584         efx->spi_eeprom = NULL;
2585         kfree(efx->spi_flash);
2586         efx->spi_flash = NULL;
2587 }
2588
2589 /* Extract non-volatile configuration */
2590 static int falcon_probe_nvconfig(struct efx_nic *efx)
2591 {
2592         struct falcon_nvconfig *nvconfig;
2593         int board_rev;
2594         int rc;
2595
2596         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2597         if (!nvconfig)
2598                 return -ENOMEM;
2599
2600         rc = falcon_read_nvram(efx, nvconfig);
2601         if (rc == -EINVAL) {
2602                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2603                 efx->phy_type = PHY_TYPE_NONE;
2604                 efx->mii.phy_id = PHY_ADDR_INVALID;
2605                 board_rev = 0;
2606                 rc = 0;
2607         } else if (rc) {
2608                 goto fail1;
2609         } else {
2610                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2611                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2612
2613                 efx->phy_type = v2->port0_phy_type;
2614                 efx->mii.phy_id = v2->port0_phy_addr;
2615                 board_rev = le16_to_cpu(v2->board_revision);
2616
2617                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2618                         __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2619                         __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2620                         rc = falcon_spi_device_init(efx, &efx->spi_flash,
2621                                                     EE_SPI_FLASH,
2622                                                     le32_to_cpu(fl));
2623                         if (rc)
2624                                 goto fail2;
2625                         rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2626                                                     EE_SPI_EEPROM,
2627                                                     le32_to_cpu(ee));
2628                         if (rc)
2629                                 goto fail2;
2630                 }
2631         }
2632
2633         /* Read the MAC addresses */
2634         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2635
2636         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2637
2638         efx_set_board_info(efx, board_rev);
2639
2640         kfree(nvconfig);
2641         return 0;
2642
2643  fail2:
2644         falcon_remove_spi_devices(efx);
2645  fail1:
2646         kfree(nvconfig);
2647         return rc;
2648 }
2649
2650 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2651  * count, port speed).  Set workaround and feature flags accordingly.
2652  */
2653 static int falcon_probe_nic_variant(struct efx_nic *efx)
2654 {
2655         efx_oword_t altera_build;
2656
2657         falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2658         if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2659                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2660                 return -ENODEV;
2661         }
2662
2663         switch (falcon_rev(efx)) {
2664         case FALCON_REV_A0:
2665         case 0xff:
2666                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2667                 return -ENODEV;
2668
2669         case FALCON_REV_A1:{
2670                 efx_oword_t nic_stat;
2671
2672                 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2673
2674                 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2675                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2676                         return -ENODEV;
2677                 }
2678                 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2679                         EFX_ERR(efx, "1G mode not supported\n");
2680                         return -ENODEV;
2681                 }
2682                 break;
2683         }
2684
2685         case FALCON_REV_B0:
2686                 break;
2687
2688         default:
2689                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2690                 return -ENODEV;
2691         }
2692
2693         return 0;
2694 }
2695
2696 /* Probe all SPI devices on the NIC */
2697 static void falcon_probe_spi_devices(struct efx_nic *efx)
2698 {
2699         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2700         bool has_flash, has_eeprom, boot_is_external;
2701
2702         falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2703         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2704         falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2705
2706         has_flash = EFX_OWORD_FIELD(nic_stat, SF_PRST);
2707         has_eeprom = EFX_OWORD_FIELD(nic_stat, EE_PRST);
2708         boot_is_external = EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE);
2709
2710         if (has_flash) {
2711                 /* Default flash SPI device: Atmel AT25F1024
2712                  * 128 KB, 24-bit address, 32 KB erase block,
2713                  * 256 B write block
2714                  */
2715                 u32 flash_device_type =
2716                         (17 << SPI_DEV_TYPE_SIZE_LBN)
2717                         | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2718                         | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
2719                         | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
2720                         | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2721
2722                 falcon_spi_device_init(efx, &efx->spi_flash,
2723                                        EE_SPI_FLASH, flash_device_type);
2724
2725                 if (!boot_is_external) {
2726                         /* Disable VPD and set clock dividers to safe
2727                          * values for initial programming.
2728                          */
2729                         EFX_LOG(efx, "Booted from internal ASIC settings;"
2730                                 " setting SPI config\n");
2731                         EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2732                                              /* 125 MHz / 7 ~= 20 MHz */
2733                                              EE_SF_CLOCK_DIV, 7,
2734                                              /* 125 MHz / 63 ~= 2 MHz */
2735                                              EE_EE_CLOCK_DIV, 63);
2736                         falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2737                 }
2738         }
2739
2740         if (has_eeprom) {
2741                 u32 eeprom_device_type;
2742
2743                 /* If it has no flash, it must have a large EEPROM
2744                  * for chip config; otherwise check whether 9-bit
2745                  * addressing is used for VPD configuration
2746                  */
2747                 if (has_flash &&
2748                     (!boot_is_external ||
2749                      EFX_OWORD_FIELD(ee_vpd_cfg, EE_VPD_EN_AD9_MODE))) {
2750                         /* Default SPI device: Atmel AT25040 or similar
2751                          * 512 B, 9-bit address, 8 B write block
2752                          */
2753                         eeprom_device_type =
2754                                 (9 << SPI_DEV_TYPE_SIZE_LBN)
2755                                 | (1 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2756                                 | (3 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2757                 } else {
2758                         /* "Large" SPI device: Atmel AT25640 or similar
2759                          * 8 KB, 16-bit address, 32 B write block
2760                          */
2761                         eeprom_device_type =
2762                                 (13 << SPI_DEV_TYPE_SIZE_LBN)
2763                                 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2764                                 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2765                 }
2766
2767                 falcon_spi_device_init(efx, &efx->spi_eeprom,
2768                                        EE_SPI_EEPROM, eeprom_device_type);
2769         }
2770
2771         EFX_LOG(efx, "flash is %s, EEPROM is %s\n",
2772                 (has_flash ? "present" : "absent"),
2773                 (has_eeprom ? "present" : "absent"));
2774 }
2775
2776 int falcon_probe_nic(struct efx_nic *efx)
2777 {
2778         struct falcon_nic_data *nic_data;
2779         int rc;
2780
2781         /* Allocate storage for hardware specific data */
2782         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2783         if (!nic_data)
2784                 return -ENOMEM;
2785         efx->nic_data = nic_data;
2786
2787         /* Determine number of ports etc. */
2788         rc = falcon_probe_nic_variant(efx);
2789         if (rc)
2790                 goto fail1;
2791
2792         /* Probe secondary function if expected */
2793         if (FALCON_IS_DUAL_FUNC(efx)) {
2794                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2795
2796                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2797                                              dev))) {
2798                         if (dev->bus == efx->pci_dev->bus &&
2799                             dev->devfn == efx->pci_dev->devfn + 1) {
2800                                 nic_data->pci_dev2 = dev;
2801                                 break;
2802                         }
2803                 }
2804                 if (!nic_data->pci_dev2) {
2805                         EFX_ERR(efx, "failed to find secondary function\n");
2806                         rc = -ENODEV;
2807                         goto fail2;
2808                 }
2809         }
2810
2811         /* Now we can reset the NIC */
2812         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2813         if (rc) {
2814                 EFX_ERR(efx, "failed to reset NIC\n");
2815                 goto fail3;
2816         }
2817
2818         /* Allocate memory for INT_KER */
2819         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2820         if (rc)
2821                 goto fail4;
2822         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2823
2824         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2825                 (unsigned long long)efx->irq_status.dma_addr,
2826                 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2827
2828         falcon_probe_spi_devices(efx);
2829
2830         /* Read in the non-volatile configuration */
2831         rc = falcon_probe_nvconfig(efx);
2832         if (rc)
2833                 goto fail5;
2834
2835         /* Initialise I2C adapter */
2836         efx->i2c_adap.owner = THIS_MODULE;
2837         nic_data->i2c_data = falcon_i2c_bit_operations;
2838         nic_data->i2c_data.data = efx;
2839         efx->i2c_adap.algo_data = &nic_data->i2c_data;
2840         efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2841         strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2842         rc = i2c_bit_add_bus(&efx->i2c_adap);
2843         if (rc)
2844                 goto fail5;
2845
2846         return 0;
2847
2848  fail5:
2849         falcon_remove_spi_devices(efx);
2850         falcon_free_buffer(efx, &efx->irq_status);
2851  fail4:
2852  fail3:
2853         if (nic_data->pci_dev2) {
2854                 pci_dev_put(nic_data->pci_dev2);
2855                 nic_data->pci_dev2 = NULL;
2856         }
2857  fail2:
2858  fail1:
2859         kfree(efx->nic_data);
2860         return rc;
2861 }
2862
2863 /* This call performs hardware-specific global initialisation, such as
2864  * defining the descriptor cache sizes and number of RSS channels.
2865  * It does not set up any buffers, descriptor rings or event queues.
2866  */
2867 int falcon_init_nic(struct efx_nic *efx)
2868 {
2869         efx_oword_t temp;
2870         unsigned thresh;
2871         int rc;
2872
2873         /* Set up the address region register. This is only needed
2874          * for the B0 FPGA, but since we are just pushing in the
2875          * reset defaults this may as well be unconditional. */
2876         EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2877                                    ADR_REGION1, (1 << 16),
2878                                    ADR_REGION2, (2 << 16),
2879                                    ADR_REGION3, (3 << 16));
2880         falcon_write(efx, &temp, ADR_REGION_REG_KER);
2881
2882         /* Use on-chip SRAM */
2883         falcon_read(efx, &temp, NIC_STAT_REG);
2884         EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2885         falcon_write(efx, &temp, NIC_STAT_REG);
2886
2887         /* Set buffer table mode */
2888         EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2889         falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2890
2891         rc = falcon_reset_sram(efx);
2892         if (rc)
2893                 return rc;
2894
2895         /* Set positions of descriptor caches in SRAM. */
2896         EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2897         falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2898         EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2899         falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2900
2901         /* Set TX descriptor cache size. */
2902         BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2903         EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2904         falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2905
2906         /* Set RX descriptor cache size.  Set low watermark to size-8, as
2907          * this allows most efficient prefetching.
2908          */
2909         BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2910         EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2911         falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2912         EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2913         falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2914
2915         /* Clear the parity enables on the TX data fifos as
2916          * they produce false parity errors because of timing issues
2917          */
2918         if (EFX_WORKAROUND_5129(efx)) {
2919                 falcon_read(efx, &temp, SPARE_REG_KER);
2920                 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2921                 falcon_write(efx, &temp, SPARE_REG_KER);
2922         }
2923
2924         /* Enable all the genuinely fatal interrupts.  (They are still
2925          * masked by the overall interrupt mask, controlled by
2926          * falcon_interrupts()).
2927          *
2928          * Note: All other fatal interrupts are enabled
2929          */
2930         EFX_POPULATE_OWORD_3(temp,
2931                              ILL_ADR_INT_KER_EN, 1,
2932                              RBUF_OWN_INT_KER_EN, 1,
2933                              TBUF_OWN_INT_KER_EN, 1);
2934         EFX_INVERT_OWORD(temp);
2935         falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2936
2937         if (EFX_WORKAROUND_7244(efx)) {
2938                 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2939                 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2940                 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2941                 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2942                 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2943                 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2944         }
2945
2946         falcon_setup_rss_indir_table(efx);
2947
2948         /* Setup RX.  Wait for descriptor is broken and must
2949          * be disabled.  RXDP recovery shouldn't be needed, but is.
2950          */
2951         falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2952         EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2953         EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2954         if (EFX_WORKAROUND_5583(efx))
2955                 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2956         falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2957
2958         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2959          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2960          */
2961         falcon_read(efx, &temp, TX_CFG2_REG_KER);
2962         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2963         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2964         EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2965         EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2966         EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2967         /* Enable SW_EV to inherit in char driver - assume harmless here */
2968         EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2969         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2970         EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2971         /* Squash TX of packets of 16 bytes or less */
2972         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
2973                 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2974         falcon_write(efx, &temp, TX_CFG2_REG_KER);
2975
2976         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2977          * descriptors (which is bad).
2978          */
2979         falcon_read(efx, &temp, TX_CFG_REG_KER);
2980         EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2981         falcon_write(efx, &temp, TX_CFG_REG_KER);
2982
2983         /* RX config */
2984         falcon_read(efx, &temp, RX_CFG_REG_KER);
2985         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2986         if (EFX_WORKAROUND_7575(efx))
2987                 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2988                                         (3 * 4096) / 32);
2989         if (falcon_rev(efx) >= FALCON_REV_B0)
2990                 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2991
2992         /* RX FIFO flow control thresholds */
2993         thresh = ((rx_xon_thresh_bytes >= 0) ?
2994                   rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2995         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2996         thresh = ((rx_xoff_thresh_bytes >= 0) ?
2997                   rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2998         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2999         /* RX control FIFO thresholds [32 entries] */
3000         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
3001         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
3002         falcon_write(efx, &temp, RX_CFG_REG_KER);
3003
3004         /* Set destination of both TX and RX Flush events */
3005         if (falcon_rev(efx) >= FALCON_REV_B0) {
3006                 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
3007                 falcon_write(efx, &temp, DP_CTRL_REG);
3008         }
3009
3010         return 0;
3011 }
3012
3013 void falcon_remove_nic(struct efx_nic *efx)
3014 {
3015         struct falcon_nic_data *nic_data = efx->nic_data;
3016         int rc;
3017
3018         rc = i2c_del_adapter(&efx->i2c_adap);
3019         BUG_ON(rc);
3020
3021         falcon_remove_spi_devices(efx);
3022         falcon_free_buffer(efx, &efx->irq_status);
3023
3024         falcon_reset_hw(efx, RESET_TYPE_ALL);
3025
3026         /* Release the second function after the reset */
3027         if (nic_data->pci_dev2) {
3028                 pci_dev_put(nic_data->pci_dev2);
3029                 nic_data->pci_dev2 = NULL;
3030         }
3031
3032         /* Tear down the private nic state */
3033         kfree(efx->nic_data);
3034         efx->nic_data = NULL;
3035 }
3036
3037 void falcon_update_nic_stats(struct efx_nic *efx)
3038 {
3039         efx_oword_t cnt;
3040
3041         falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3042         efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3043 }
3044
3045 /**************************************************************************
3046  *
3047  * Revision-dependent attributes used by efx.c
3048  *
3049  **************************************************************************
3050  */
3051
3052 struct efx_nic_type falcon_a_nic_type = {
3053         .mem_bar = 2,
3054         .mem_map_size = 0x20000,
3055         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3056         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3057         .buf_tbl_base = BUF_TBL_KER_A1,
3058         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3059         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3060         .txd_ring_mask = FALCON_TXD_RING_MASK,
3061         .rxd_ring_mask = FALCON_RXD_RING_MASK,
3062         .evq_size = FALCON_EVQ_SIZE,
3063         .max_dma_mask = FALCON_DMA_MASK,
3064         .tx_dma_mask = FALCON_TX_DMA_MASK,
3065         .bug5391_mask = 0xf,
3066         .rx_xoff_thresh = 2048,
3067         .rx_xon_thresh = 512,
3068         .rx_buffer_padding = 0x24,
3069         .max_interrupt_mode = EFX_INT_MODE_MSI,
3070         .phys_addr_channels = 4,
3071 };
3072
3073 struct efx_nic_type falcon_b_nic_type = {
3074         .mem_bar = 2,
3075         /* Map everything up to and including the RSS indirection
3076          * table.  Don't map MSI-X table, MSI-X PBA since Linux
3077          * requires that they not be mapped.  */
3078         .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3079         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3080         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3081         .buf_tbl_base = BUF_TBL_KER_B0,
3082         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3083         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3084         .txd_ring_mask = FALCON_TXD_RING_MASK,
3085         .rxd_ring_mask = FALCON_RXD_RING_MASK,
3086         .evq_size = FALCON_EVQ_SIZE,
3087         .max_dma_mask = FALCON_DMA_MASK,
3088         .tx_dma_mask = FALCON_TX_DMA_MASK,
3089         .bug5391_mask = 0,
3090         .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3091         .rx_xon_thresh = 27648,  /* ~3*max MTU */
3092         .rx_buffer_padding = 0,
3093         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3094         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3095                                    * interrupt handler only supports 32
3096                                    * channels */
3097 };
3098