1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/delay.h>
16 #include <linux/notifier.h>
18 #include <linux/tcp.h>
20 #include <linux/crc32.h>
21 #include <linux/ethtool.h>
22 #include <linux/topology.h>
23 #include "net_driver.h"
33 #define EFX_MAX_MTU (9 * 1024)
35 /* RX slow fill workqueue. If memory allocation fails in the fast path,
36 * a work item is pushed onto this work queue to retry the allocation later,
37 * to avoid the NIC being starved of RX buffers. Since this is a per cpu
38 * workqueue, there is nothing to be gained in making it per NIC
40 static struct workqueue_struct *refill_workqueue;
42 /**************************************************************************
46 *************************************************************************/
49 * Enable large receive offload (LRO) aka soft segment reassembly (SSR)
51 * This sets the default for new devices. It can be controlled later
54 static int lro = true;
55 module_param(lro, int, 0644);
56 MODULE_PARM_DESC(lro, "Large receive offload acceleration");
59 * Use separate channels for TX and RX events
61 * Set this to 1 to use separate channels for TX and RX. It allows us to
62 * apply a higher level of interrupt moderation to TX events.
64 * This is forced to 0 for MSI interrupt mode as the interrupt vector
67 static unsigned int separate_tx_and_rx_channels = true;
69 /* This is the weight assigned to each of the (per-channel) virtual
72 static int napi_weight = 64;
74 /* This is the time (in jiffies) between invocations of the hardware
75 * monitor, which checks for known hardware bugs and resets the
76 * hardware and driver as necessary.
78 unsigned int efx_monitor_interval = 1 * HZ;
80 /* This controls whether or not the hardware monitor will trigger a
81 * reset when it detects an error condition.
83 static unsigned int monitor_reset = true;
85 /* This controls whether or not the driver will initialise devices
86 * with invalid MAC addresses stored in the EEPROM or flash. If true,
87 * such devices will be initialised with a random locally-generated
88 * MAC address. This allows for loading the sfc_mtd driver to
89 * reprogram the flash, even if the flash contents (including the MAC
90 * address) have previously been erased.
92 static unsigned int allow_bad_hwaddr;
94 /* Initial interrupt moderation settings. They can be modified after
95 * module load with ethtool.
97 * The default for RX should strike a balance between increasing the
98 * round-trip latency and reducing overhead.
100 static unsigned int rx_irq_mod_usec = 60;
102 /* Initial interrupt moderation settings. They can be modified after
103 * module load with ethtool.
105 * This default is chosen to ensure that a 10G link does not go idle
106 * while a TX queue is stopped after it has become full. A queue is
107 * restarted when it drops below half full. The time this takes (assuming
108 * worst case 3 descriptors per packet and 1024 descriptors) is
109 * 512 / 3 * 1.2 = 205 usec.
111 static unsigned int tx_irq_mod_usec = 150;
113 /* This is the first interrupt mode to try out of:
118 static unsigned int interrupt_mode;
120 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
121 * i.e. the number of CPUs among which we may distribute simultaneous
122 * interrupt handling.
124 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
125 * The default (0) means to assign an interrupt to each package (level II cache)
127 static unsigned int rss_cpus;
128 module_param(rss_cpus, uint, 0444);
129 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
131 /**************************************************************************
133 * Utility functions and prototypes
135 *************************************************************************/
136 static void efx_remove_channel(struct efx_channel *channel);
137 static void efx_remove_port(struct efx_nic *efx);
138 static void efx_fini_napi(struct efx_nic *efx);
139 static void efx_fini_channels(struct efx_nic *efx);
141 #define EFX_ASSERT_RESET_SERIALISED(efx) \
143 if ((efx->state == STATE_RUNNING) || \
144 (efx->state == STATE_RESETTING)) \
148 /**************************************************************************
150 * Event queue processing
152 *************************************************************************/
154 /* Process channel's event queue
156 * This function is responsible for processing the event queue of a
157 * single channel. The caller must guarantee that this function will
158 * never be concurrently called more than once on the same channel,
159 * though different channels may be being processed concurrently.
161 static int efx_process_channel(struct efx_channel *channel, int rx_quota)
163 struct efx_nic *efx = channel->efx;
166 if (unlikely(efx->reset_pending != RESET_TYPE_NONE ||
170 rx_packets = falcon_process_eventq(channel, rx_quota);
174 /* Deliver last RX packet. */
175 if (channel->rx_pkt) {
176 __efx_rx_packet(channel, channel->rx_pkt,
177 channel->rx_pkt_csummed);
178 channel->rx_pkt = NULL;
181 efx_flush_lro(channel);
182 efx_rx_strategy(channel);
184 efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]);
189 /* Mark channel as finished processing
191 * Note that since we will not receive further interrupts for this
192 * channel before we finish processing and call the eventq_read_ack()
193 * method, there is no need to use the interrupt hold-off timers.
195 static inline void efx_channel_processed(struct efx_channel *channel)
197 /* The interrupt handler for this channel may set work_pending
198 * as soon as we acknowledge the events we've seen. Make sure
199 * it's cleared before then. */
200 channel->work_pending = false;
203 falcon_eventq_read_ack(channel);
208 * NAPI guarantees serialisation of polls of the same device, which
209 * provides the guarantee required by efx_process_channel().
211 static int efx_poll(struct napi_struct *napi, int budget)
213 struct efx_channel *channel =
214 container_of(napi, struct efx_channel, napi_str);
215 struct net_device *napi_dev = channel->napi_dev;
218 EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n",
219 channel->channel, raw_smp_processor_id());
221 rx_packets = efx_process_channel(channel, budget);
223 if (rx_packets < budget) {
224 /* There is no race here; although napi_disable() will
225 * only wait for netif_rx_complete(), this isn't a problem
226 * since efx_channel_processed() will have no effect if
227 * interrupts have already been disabled.
229 netif_rx_complete(napi_dev, napi);
230 efx_channel_processed(channel);
236 /* Process the eventq of the specified channel immediately on this CPU
238 * Disable hardware generated interrupts, wait for any existing
239 * processing to finish, then directly poll (and ack ) the eventq.
240 * Finally reenable NAPI and interrupts.
242 * Since we are touching interrupts the caller should hold the suspend lock
244 void efx_process_channel_now(struct efx_channel *channel)
246 struct efx_nic *efx = channel->efx;
248 BUG_ON(!channel->used_flags);
249 BUG_ON(!channel->enabled);
251 /* Disable interrupts and wait for ISRs to complete */
252 falcon_disable_interrupts(efx);
254 synchronize_irq(efx->legacy_irq);
256 synchronize_irq(channel->irq);
258 /* Wait for any NAPI processing to complete */
259 napi_disable(&channel->napi_str);
261 /* Poll the channel */
262 efx_process_channel(channel, efx->type->evq_size);
264 /* Ack the eventq. This may cause an interrupt to be generated
265 * when they are reenabled */
266 efx_channel_processed(channel);
268 napi_enable(&channel->napi_str);
269 falcon_enable_interrupts(efx);
272 /* Create event queue
273 * Event queue memory allocations are done only once. If the channel
274 * is reset, the memory buffer will be reused; this guards against
275 * errors during channel reset and also simplifies interrupt handling.
277 static int efx_probe_eventq(struct efx_channel *channel)
279 EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel);
281 return falcon_probe_eventq(channel);
284 /* Prepare channel's event queue */
285 static int efx_init_eventq(struct efx_channel *channel)
287 EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel);
289 channel->eventq_read_ptr = 0;
291 return falcon_init_eventq(channel);
294 static void efx_fini_eventq(struct efx_channel *channel)
296 EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel);
298 falcon_fini_eventq(channel);
301 static void efx_remove_eventq(struct efx_channel *channel)
303 EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel);
305 falcon_remove_eventq(channel);
308 /**************************************************************************
312 *************************************************************************/
314 static int efx_probe_channel(struct efx_channel *channel)
316 struct efx_tx_queue *tx_queue;
317 struct efx_rx_queue *rx_queue;
320 EFX_LOG(channel->efx, "creating channel %d\n", channel->channel);
322 rc = efx_probe_eventq(channel);
326 efx_for_each_channel_tx_queue(tx_queue, channel) {
327 rc = efx_probe_tx_queue(tx_queue);
332 efx_for_each_channel_rx_queue(rx_queue, channel) {
333 rc = efx_probe_rx_queue(rx_queue);
338 channel->n_rx_frm_trunc = 0;
343 efx_for_each_channel_rx_queue(rx_queue, channel)
344 efx_remove_rx_queue(rx_queue);
346 efx_for_each_channel_tx_queue(tx_queue, channel)
347 efx_remove_tx_queue(tx_queue);
353 /* Channels are shutdown and reinitialised whilst the NIC is running
354 * to propagate configuration changes (mtu, checksum offload), or
355 * to clear hardware error conditions
357 static int efx_init_channels(struct efx_nic *efx)
359 struct efx_tx_queue *tx_queue;
360 struct efx_rx_queue *rx_queue;
361 struct efx_channel *channel;
364 /* Calculate the rx buffer allocation parameters required to
365 * support the current MTU, including padding for header
366 * alignment and overruns.
368 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
369 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
370 efx->type->rx_buffer_padding);
371 efx->rx_buffer_order = get_order(efx->rx_buffer_len);
373 /* Initialise the channels */
374 efx_for_each_channel(channel, efx) {
375 EFX_LOG(channel->efx, "init chan %d\n", channel->channel);
377 rc = efx_init_eventq(channel);
381 efx_for_each_channel_tx_queue(tx_queue, channel) {
382 rc = efx_init_tx_queue(tx_queue);
387 /* The rx buffer allocation strategy is MTU dependent */
388 efx_rx_strategy(channel);
390 efx_for_each_channel_rx_queue(rx_queue, channel) {
391 rc = efx_init_rx_queue(rx_queue);
396 WARN_ON(channel->rx_pkt != NULL);
397 efx_rx_strategy(channel);
403 EFX_ERR(efx, "failed to initialise channel %d\n",
404 channel ? channel->channel : -1);
405 efx_fini_channels(efx);
409 /* This enables event queue processing and packet transmission.
411 * Note that this function is not allowed to fail, since that would
412 * introduce too much complexity into the suspend/resume path.
414 static void efx_start_channel(struct efx_channel *channel)
416 struct efx_rx_queue *rx_queue;
418 EFX_LOG(channel->efx, "starting chan %d\n", channel->channel);
420 if (!(channel->efx->net_dev->flags & IFF_UP))
421 netif_napi_add(channel->napi_dev, &channel->napi_str,
422 efx_poll, napi_weight);
424 /* The interrupt handler for this channel may set work_pending
425 * as soon as we enable it. Make sure it's cleared before
426 * then. Similarly, make sure it sees the enabled flag set. */
427 channel->work_pending = false;
428 channel->enabled = true;
431 napi_enable(&channel->napi_str);
433 /* Load up RX descriptors */
434 efx_for_each_channel_rx_queue(rx_queue, channel)
435 efx_fast_push_rx_descriptors(rx_queue);
438 /* This disables event queue processing and packet transmission.
439 * This function does not guarantee that all queue processing
440 * (e.g. RX refill) is complete.
442 static void efx_stop_channel(struct efx_channel *channel)
444 struct efx_rx_queue *rx_queue;
446 if (!channel->enabled)
449 EFX_LOG(channel->efx, "stop chan %d\n", channel->channel);
451 channel->enabled = false;
452 napi_disable(&channel->napi_str);
454 /* Ensure that any worker threads have exited or will be no-ops */
455 efx_for_each_channel_rx_queue(rx_queue, channel) {
456 spin_lock_bh(&rx_queue->add_lock);
457 spin_unlock_bh(&rx_queue->add_lock);
461 static void efx_fini_channels(struct efx_nic *efx)
463 struct efx_channel *channel;
464 struct efx_tx_queue *tx_queue;
465 struct efx_rx_queue *rx_queue;
467 EFX_ASSERT_RESET_SERIALISED(efx);
468 BUG_ON(efx->port_enabled);
470 efx_for_each_channel(channel, efx) {
471 EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel);
473 efx_for_each_channel_rx_queue(rx_queue, channel)
474 efx_fini_rx_queue(rx_queue);
475 efx_for_each_channel_tx_queue(tx_queue, channel)
476 efx_fini_tx_queue(tx_queue);
479 /* Do the event queues last so that we can handle flush events
480 * for all DMA queues. */
481 efx_for_each_channel(channel, efx) {
482 EFX_LOG(channel->efx, "shut down evq %d\n", channel->channel);
484 efx_fini_eventq(channel);
488 static void efx_remove_channel(struct efx_channel *channel)
490 struct efx_tx_queue *tx_queue;
491 struct efx_rx_queue *rx_queue;
493 EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel);
495 efx_for_each_channel_rx_queue(rx_queue, channel)
496 efx_remove_rx_queue(rx_queue);
497 efx_for_each_channel_tx_queue(tx_queue, channel)
498 efx_remove_tx_queue(tx_queue);
499 efx_remove_eventq(channel);
501 channel->used_flags = 0;
504 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay)
506 queue_delayed_work(refill_workqueue, &rx_queue->work, delay);
509 /**************************************************************************
513 **************************************************************************/
515 /* This ensures that the kernel is kept informed (via
516 * netif_carrier_on/off) of the link status, and also maintains the
517 * link status's stop on the port's TX queue.
519 static void efx_link_status_changed(struct efx_nic *efx)
521 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
522 * that no events are triggered between unregister_netdev() and the
523 * driver unloading. A more general condition is that NETDEV_CHANGE
524 * can only be generated between NETDEV_UP and NETDEV_DOWN */
525 if (!netif_running(efx->net_dev))
528 if (efx->link_up != netif_carrier_ok(efx->net_dev)) {
529 efx->n_link_state_changes++;
532 netif_carrier_on(efx->net_dev);
534 netif_carrier_off(efx->net_dev);
537 /* Status message for kernel log */
539 struct mii_if_info *gmii = &efx->mii;
541 /* NONE here means direct XAUI from the controller, with no
542 * MDIO-attached device we can query. */
543 if (efx->phy_type != PHY_TYPE_NONE) {
544 adv = gmii_advertised(gmii);
545 lpa = gmii_lpa(gmii);
547 lpa = GM_LPA_10000 | LPA_DUPLEX;
550 EFX_INFO(efx, "link up at %dMbps %s-duplex "
551 "(adv %04x lpa %04x) (MTU %d)%s\n",
552 (efx->link_options & GM_LPA_10000 ? 10000 :
553 (efx->link_options & GM_LPA_1000 ? 1000 :
554 (efx->link_options & GM_LPA_100 ? 100 :
556 (efx->link_options & GM_LPA_DUPLEX ?
560 (efx->promiscuous ? " [PROMISC]" : ""));
562 EFX_INFO(efx, "link down\n");
567 /* This call reinitialises the MAC to pick up new PHY settings. The
568 * caller must hold the mac_lock */
569 static void __efx_reconfigure_port(struct efx_nic *efx)
571 WARN_ON(!mutex_is_locked(&efx->mac_lock));
573 EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n",
574 raw_smp_processor_id());
576 falcon_reconfigure_xmac(efx);
578 /* Inform kernel of loss/gain of carrier */
579 efx_link_status_changed(efx);
582 /* Reinitialise the MAC to pick up new PHY settings, even if the port is
584 void efx_reconfigure_port(struct efx_nic *efx)
586 EFX_ASSERT_RESET_SERIALISED(efx);
588 mutex_lock(&efx->mac_lock);
589 __efx_reconfigure_port(efx);
590 mutex_unlock(&efx->mac_lock);
593 /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all()
594 * we don't efx_reconfigure_port() if the port is disabled. Care is taken
595 * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */
596 static void efx_reconfigure_work(struct work_struct *data)
598 struct efx_nic *efx = container_of(data, struct efx_nic,
601 mutex_lock(&efx->mac_lock);
602 if (efx->port_enabled)
603 __efx_reconfigure_port(efx);
604 mutex_unlock(&efx->mac_lock);
607 static int efx_probe_port(struct efx_nic *efx)
611 EFX_LOG(efx, "create port\n");
613 /* Connect up MAC/PHY operations table and read MAC address */
614 rc = falcon_probe_port(efx);
618 /* Sanity check MAC address */
619 if (is_valid_ether_addr(efx->mac_address)) {
620 memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN);
622 DECLARE_MAC_BUF(mac);
624 EFX_ERR(efx, "invalid MAC address %s\n",
625 print_mac(mac, efx->mac_address));
626 if (!allow_bad_hwaddr) {
630 random_ether_addr(efx->net_dev->dev_addr);
631 EFX_INFO(efx, "using locally-generated MAC %s\n",
632 print_mac(mac, efx->net_dev->dev_addr));
638 efx_remove_port(efx);
642 static int efx_init_port(struct efx_nic *efx)
646 EFX_LOG(efx, "init port\n");
648 /* Initialise the MAC and PHY */
649 rc = falcon_init_xmac(efx);
653 efx->port_initialized = true;
655 /* Reconfigure port to program MAC registers */
656 falcon_reconfigure_xmac(efx);
661 /* Allow efx_reconfigure_port() to be scheduled, and close the window
662 * between efx_stop_port and efx_flush_all whereby a previously scheduled
663 * efx_reconfigure_port() may have been cancelled */
664 static void efx_start_port(struct efx_nic *efx)
666 EFX_LOG(efx, "start port\n");
667 BUG_ON(efx->port_enabled);
669 mutex_lock(&efx->mac_lock);
670 efx->port_enabled = true;
671 __efx_reconfigure_port(efx);
672 mutex_unlock(&efx->mac_lock);
675 /* Prevent efx_reconfigure_work and efx_monitor() from executing, and
676 * efx_set_multicast_list() from scheduling efx_reconfigure_work.
677 * efx_reconfigure_work can still be scheduled via NAPI processing
678 * until efx_flush_all() is called */
679 static void efx_stop_port(struct efx_nic *efx)
681 EFX_LOG(efx, "stop port\n");
683 mutex_lock(&efx->mac_lock);
684 efx->port_enabled = false;
685 mutex_unlock(&efx->mac_lock);
687 /* Serialise against efx_set_multicast_list() */
688 if (efx_dev_registered(efx)) {
689 netif_addr_lock_bh(efx->net_dev);
690 netif_addr_unlock_bh(efx->net_dev);
694 static void efx_fini_port(struct efx_nic *efx)
696 EFX_LOG(efx, "shut down port\n");
698 if (!efx->port_initialized)
701 falcon_fini_xmac(efx);
702 efx->port_initialized = false;
704 efx->link_up = false;
705 efx_link_status_changed(efx);
708 static void efx_remove_port(struct efx_nic *efx)
710 EFX_LOG(efx, "destroying port\n");
712 falcon_remove_port(efx);
715 /**************************************************************************
719 **************************************************************************/
721 /* This configures the PCI device to enable I/O and DMA. */
722 static int efx_init_io(struct efx_nic *efx)
724 struct pci_dev *pci_dev = efx->pci_dev;
725 dma_addr_t dma_mask = efx->type->max_dma_mask;
728 EFX_LOG(efx, "initialising I/O\n");
730 rc = pci_enable_device(pci_dev);
732 EFX_ERR(efx, "failed to enable PCI device\n");
736 pci_set_master(pci_dev);
738 /* Set the PCI DMA mask. Try all possibilities from our
739 * genuine mask down to 32 bits, because some architectures
740 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
741 * masks event though they reject 46 bit masks.
743 while (dma_mask > 0x7fffffffUL) {
744 if (pci_dma_supported(pci_dev, dma_mask) &&
745 ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0))
750 EFX_ERR(efx, "could not find a suitable DMA mask\n");
753 EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask);
754 rc = pci_set_consistent_dma_mask(pci_dev, dma_mask);
756 /* pci_set_consistent_dma_mask() is not *allowed* to
757 * fail with a mask that pci_set_dma_mask() accepted,
758 * but just in case...
760 EFX_ERR(efx, "failed to set consistent DMA mask\n");
764 efx->membase_phys = pci_resource_start(efx->pci_dev,
766 rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc");
768 EFX_ERR(efx, "request for memory BAR failed\n");
772 efx->membase = ioremap_nocache(efx->membase_phys,
773 efx->type->mem_map_size);
775 EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n",
777 (unsigned long long)efx->membase_phys,
778 efx->type->mem_map_size);
782 EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n",
783 efx->type->mem_bar, (unsigned long long)efx->membase_phys,
784 efx->type->mem_map_size, efx->membase);
789 release_mem_region(efx->membase_phys, efx->type->mem_map_size);
791 efx->membase_phys = 0;
793 pci_disable_device(efx->pci_dev);
798 static void efx_fini_io(struct efx_nic *efx)
800 EFX_LOG(efx, "shutting down I/O\n");
803 iounmap(efx->membase);
807 if (efx->membase_phys) {
808 pci_release_region(efx->pci_dev, efx->type->mem_bar);
809 efx->membase_phys = 0;
812 pci_disable_device(efx->pci_dev);
815 /* Get number of RX queues wanted. Return number of online CPU
816 * packages in the expectation that an IRQ balancer will spread
817 * interrupts across them. */
818 static int efx_wanted_rx_queues(void)
824 cpus_clear(core_mask);
826 for_each_online_cpu(cpu) {
827 if (!cpu_isset(cpu, core_mask)) {
829 cpus_or(core_mask, core_mask,
830 topology_core_siblings(cpu));
837 /* Probe the number and type of interrupts we are able to obtain, and
838 * the resulting numbers of channels and RX queues.
840 static void efx_probe_interrupts(struct efx_nic *efx)
843 min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
846 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
847 struct msix_entry xentries[EFX_MAX_CHANNELS];
850 /* We want one RX queue and interrupt per CPU package
851 * (or as specified by the rss_cpus module parameter).
852 * We will need one channel per interrupt.
854 wanted_ints = rss_cpus ? rss_cpus : efx_wanted_rx_queues();
855 efx->n_rx_queues = min(wanted_ints, max_channels);
857 for (i = 0; i < efx->n_rx_queues; i++)
858 xentries[i].entry = i;
859 rc = pci_enable_msix(efx->pci_dev, xentries, efx->n_rx_queues);
861 EFX_BUG_ON_PARANOID(rc >= efx->n_rx_queues);
862 efx->n_rx_queues = rc;
863 rc = pci_enable_msix(efx->pci_dev, xentries,
868 for (i = 0; i < efx->n_rx_queues; i++)
869 efx->channel[i].irq = xentries[i].vector;
871 /* Fall back to single channel MSI */
872 efx->interrupt_mode = EFX_INT_MODE_MSI;
873 EFX_ERR(efx, "could not enable MSI-X\n");
877 /* Try single interrupt MSI */
878 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
879 efx->n_rx_queues = 1;
880 rc = pci_enable_msi(efx->pci_dev);
882 efx->channel[0].irq = efx->pci_dev->irq;
884 EFX_ERR(efx, "could not enable MSI\n");
885 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
889 /* Assume legacy interrupts */
890 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
891 efx->n_rx_queues = 1;
892 efx->legacy_irq = efx->pci_dev->irq;
896 static void efx_remove_interrupts(struct efx_nic *efx)
898 struct efx_channel *channel;
900 /* Remove MSI/MSI-X interrupts */
901 efx_for_each_channel(channel, efx)
903 pci_disable_msi(efx->pci_dev);
904 pci_disable_msix(efx->pci_dev);
906 /* Remove legacy interrupt */
910 static void efx_set_channels(struct efx_nic *efx)
912 struct efx_tx_queue *tx_queue;
913 struct efx_rx_queue *rx_queue;
915 efx_for_each_tx_queue(tx_queue, efx) {
916 if (!EFX_INT_MODE_USE_MSI(efx) && separate_tx_and_rx_channels)
917 tx_queue->channel = &efx->channel[1];
919 tx_queue->channel = &efx->channel[0];
920 tx_queue->channel->used_flags |= EFX_USED_BY_TX;
923 efx_for_each_rx_queue(rx_queue, efx) {
924 rx_queue->channel = &efx->channel[rx_queue->queue];
925 rx_queue->channel->used_flags |= EFX_USED_BY_RX;
929 static int efx_probe_nic(struct efx_nic *efx)
933 EFX_LOG(efx, "creating NIC\n");
935 /* Carry out hardware-type specific initialisation */
936 rc = falcon_probe_nic(efx);
940 /* Determine the number of channels and RX queues by trying to hook
941 * in MSI-X interrupts. */
942 efx_probe_interrupts(efx);
944 efx_set_channels(efx);
946 /* Initialise the interrupt moderation settings */
947 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec);
952 static void efx_remove_nic(struct efx_nic *efx)
954 EFX_LOG(efx, "destroying NIC\n");
956 efx_remove_interrupts(efx);
957 falcon_remove_nic(efx);
960 /**************************************************************************
962 * NIC startup/shutdown
964 *************************************************************************/
966 static int efx_probe_all(struct efx_nic *efx)
968 struct efx_channel *channel;
972 rc = efx_probe_nic(efx);
974 EFX_ERR(efx, "failed to create NIC\n");
979 rc = efx_probe_port(efx);
981 EFX_ERR(efx, "failed to create port\n");
985 /* Create channels */
986 efx_for_each_channel(channel, efx) {
987 rc = efx_probe_channel(channel);
989 EFX_ERR(efx, "failed to create channel %d\n",
998 efx_for_each_channel(channel, efx)
999 efx_remove_channel(channel);
1000 efx_remove_port(efx);
1002 efx_remove_nic(efx);
1007 /* Called after previous invocation(s) of efx_stop_all, restarts the
1008 * port, kernel transmit queue, NAPI processing and hardware interrupts,
1009 * and ensures that the port is scheduled to be reconfigured.
1010 * This function is safe to call multiple times when the NIC is in any
1012 static void efx_start_all(struct efx_nic *efx)
1014 struct efx_channel *channel;
1016 EFX_ASSERT_RESET_SERIALISED(efx);
1018 /* Check that it is appropriate to restart the interface. All
1019 * of these flags are safe to read under just the rtnl lock */
1020 if (efx->port_enabled)
1022 if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT))
1024 if (efx_dev_registered(efx) && !netif_running(efx->net_dev))
1027 /* Mark the port as enabled so port reconfigurations can start, then
1028 * restart the transmit interface early so the watchdog timer stops */
1029 efx_start_port(efx);
1030 if (efx_dev_registered(efx))
1031 efx_wake_queue(efx);
1033 efx_for_each_channel(channel, efx)
1034 efx_start_channel(channel);
1036 falcon_enable_interrupts(efx);
1038 /* Start hardware monitor if we're in RUNNING */
1039 if (efx->state == STATE_RUNNING)
1040 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1041 efx_monitor_interval);
1044 /* Flush all delayed work. Should only be called when no more delayed work
1045 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1046 * since we're holding the rtnl_lock at this point. */
1047 static void efx_flush_all(struct efx_nic *efx)
1049 struct efx_rx_queue *rx_queue;
1051 /* Make sure the hardware monitor is stopped */
1052 cancel_delayed_work_sync(&efx->monitor_work);
1054 /* Ensure that all RX slow refills are complete. */
1055 efx_for_each_rx_queue(rx_queue, efx)
1056 cancel_delayed_work_sync(&rx_queue->work);
1058 /* Stop scheduled port reconfigurations */
1059 cancel_work_sync(&efx->reconfigure_work);
1063 /* Quiesce hardware and software without bringing the link down.
1064 * Safe to call multiple times, when the nic and interface is in any
1065 * state. The caller is guaranteed to subsequently be in a position
1066 * to modify any hardware and software state they see fit without
1068 static void efx_stop_all(struct efx_nic *efx)
1070 struct efx_channel *channel;
1072 EFX_ASSERT_RESET_SERIALISED(efx);
1074 /* port_enabled can be read safely under the rtnl lock */
1075 if (!efx->port_enabled)
1078 /* Disable interrupts and wait for ISR to complete */
1079 falcon_disable_interrupts(efx);
1080 if (efx->legacy_irq)
1081 synchronize_irq(efx->legacy_irq);
1082 efx_for_each_channel(channel, efx) {
1084 synchronize_irq(channel->irq);
1087 /* Stop all NAPI processing and synchronous rx refills */
1088 efx_for_each_channel(channel, efx)
1089 efx_stop_channel(channel);
1091 /* Stop all asynchronous port reconfigurations. Since all
1092 * event processing has already been stopped, there is no
1093 * window to loose phy events */
1096 /* Flush reconfigure_work, refill_workqueue, monitor_work */
1099 /* Isolate the MAC from the TX and RX engines, so that queue
1100 * flushes will complete in a timely fashion. */
1101 falcon_deconfigure_mac_wrapper(efx);
1102 falcon_drain_tx_fifo(efx);
1104 /* Stop the kernel transmit interface late, so the watchdog
1105 * timer isn't ticking over the flush */
1106 if (efx_dev_registered(efx)) {
1107 efx_stop_queue(efx);
1108 netif_tx_lock_bh(efx->net_dev);
1109 netif_tx_unlock_bh(efx->net_dev);
1113 static void efx_remove_all(struct efx_nic *efx)
1115 struct efx_channel *channel;
1117 efx_for_each_channel(channel, efx)
1118 efx_remove_channel(channel);
1119 efx_remove_port(efx);
1120 efx_remove_nic(efx);
1123 /* A convinience function to safely flush all the queues */
1124 int efx_flush_queues(struct efx_nic *efx)
1128 EFX_ASSERT_RESET_SERIALISED(efx);
1132 efx_fini_channels(efx);
1133 rc = efx_init_channels(efx);
1135 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1144 /**************************************************************************
1146 * Interrupt moderation
1148 **************************************************************************/
1150 /* Set interrupt moderation parameters */
1151 void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs)
1153 struct efx_tx_queue *tx_queue;
1154 struct efx_rx_queue *rx_queue;
1156 EFX_ASSERT_RESET_SERIALISED(efx);
1158 efx_for_each_tx_queue(tx_queue, efx)
1159 tx_queue->channel->irq_moderation = tx_usecs;
1161 efx_for_each_rx_queue(rx_queue, efx)
1162 rx_queue->channel->irq_moderation = rx_usecs;
1165 /**************************************************************************
1169 **************************************************************************/
1171 /* Run periodically off the general workqueue. Serialised against
1172 * efx_reconfigure_port via the mac_lock */
1173 static void efx_monitor(struct work_struct *data)
1175 struct efx_nic *efx = container_of(data, struct efx_nic,
1179 EFX_TRACE(efx, "hardware monitor executing on CPU %d\n",
1180 raw_smp_processor_id());
1183 /* If the mac_lock is already held then it is likely a port
1184 * reconfiguration is already in place, which will likely do
1185 * most of the work of check_hw() anyway. */
1186 if (!mutex_trylock(&efx->mac_lock)) {
1187 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1188 efx_monitor_interval);
1192 if (efx->port_enabled)
1193 rc = falcon_check_xmac(efx);
1194 mutex_unlock(&efx->mac_lock);
1197 if (monitor_reset) {
1198 EFX_ERR(efx, "hardware monitor detected a fault: "
1199 "triggering reset\n");
1200 efx_schedule_reset(efx, RESET_TYPE_MONITOR);
1202 EFX_ERR(efx, "hardware monitor detected a fault, "
1203 "skipping reset\n");
1207 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1208 efx_monitor_interval);
1211 /**************************************************************************
1215 *************************************************************************/
1218 * Context: process, rtnl_lock() held.
1220 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1222 struct efx_nic *efx = netdev_priv(net_dev);
1224 EFX_ASSERT_RESET_SERIALISED(efx);
1226 return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL);
1229 /**************************************************************************
1233 **************************************************************************/
1235 static int efx_init_napi(struct efx_nic *efx)
1237 struct efx_channel *channel;
1240 efx_for_each_channel(channel, efx) {
1241 channel->napi_dev = efx->net_dev;
1242 rc = efx_lro_init(&channel->lro_mgr, efx);
1252 static void efx_fini_napi(struct efx_nic *efx)
1254 struct efx_channel *channel;
1256 efx_for_each_channel(channel, efx) {
1257 efx_lro_fini(&channel->lro_mgr);
1258 channel->napi_dev = NULL;
1262 /**************************************************************************
1264 * Kernel netpoll interface
1266 *************************************************************************/
1268 #ifdef CONFIG_NET_POLL_CONTROLLER
1270 /* Although in the common case interrupts will be disabled, this is not
1271 * guaranteed. However, all our work happens inside the NAPI callback,
1272 * so no locking is required.
1274 static void efx_netpoll(struct net_device *net_dev)
1276 struct efx_nic *efx = netdev_priv(net_dev);
1277 struct efx_channel *channel;
1279 efx_for_each_channel(channel, efx)
1280 efx_schedule_channel(channel);
1285 /**************************************************************************
1287 * Kernel net device interface
1289 *************************************************************************/
1291 /* Context: process, rtnl_lock() held. */
1292 static int efx_net_open(struct net_device *net_dev)
1294 struct efx_nic *efx = netdev_priv(net_dev);
1295 EFX_ASSERT_RESET_SERIALISED(efx);
1297 EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name,
1298 raw_smp_processor_id());
1300 if (efx->phy_mode & PHY_MODE_SPECIAL)
1307 /* Context: process, rtnl_lock() held.
1308 * Note that the kernel will ignore our return code; this method
1309 * should really be a void.
1311 static int efx_net_stop(struct net_device *net_dev)
1313 struct efx_nic *efx = netdev_priv(net_dev);
1316 EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name,
1317 raw_smp_processor_id());
1319 /* Stop the device and flush all the channels */
1321 efx_fini_channels(efx);
1322 rc = efx_init_channels(efx);
1324 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1329 /* Context: process, dev_base_lock or RTNL held, non-blocking. */
1330 static struct net_device_stats *efx_net_stats(struct net_device *net_dev)
1332 struct efx_nic *efx = netdev_priv(net_dev);
1333 struct efx_mac_stats *mac_stats = &efx->mac_stats;
1334 struct net_device_stats *stats = &net_dev->stats;
1336 /* Update stats if possible, but do not wait if another thread
1337 * is updating them (or resetting the NIC); slightly stale
1338 * stats are acceptable.
1340 if (!spin_trylock(&efx->stats_lock))
1342 if (efx->state == STATE_RUNNING) {
1343 falcon_update_stats_xmac(efx);
1344 falcon_update_nic_stats(efx);
1346 spin_unlock(&efx->stats_lock);
1348 stats->rx_packets = mac_stats->rx_packets;
1349 stats->tx_packets = mac_stats->tx_packets;
1350 stats->rx_bytes = mac_stats->rx_bytes;
1351 stats->tx_bytes = mac_stats->tx_bytes;
1352 stats->multicast = mac_stats->rx_multicast;
1353 stats->collisions = mac_stats->tx_collision;
1354 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1355 mac_stats->rx_length_error);
1356 stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt;
1357 stats->rx_crc_errors = mac_stats->rx_bad;
1358 stats->rx_frame_errors = mac_stats->rx_align_error;
1359 stats->rx_fifo_errors = mac_stats->rx_overflow;
1360 stats->rx_missed_errors = mac_stats->rx_missed;
1361 stats->tx_window_errors = mac_stats->tx_late_collision;
1363 stats->rx_errors = (stats->rx_length_errors +
1364 stats->rx_over_errors +
1365 stats->rx_crc_errors +
1366 stats->rx_frame_errors +
1367 stats->rx_fifo_errors +
1368 stats->rx_missed_errors +
1369 mac_stats->rx_symbol_error);
1370 stats->tx_errors = (stats->tx_window_errors +
1376 /* Context: netif_tx_lock held, BHs disabled. */
1377 static void efx_watchdog(struct net_device *net_dev)
1379 struct efx_nic *efx = netdev_priv(net_dev);
1381 EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d: %s\n",
1382 atomic_read(&efx->netif_stop_count), efx->port_enabled,
1383 monitor_reset ? "resetting channels" : "skipping reset");
1386 efx_schedule_reset(efx, RESET_TYPE_MONITOR);
1390 /* Context: process, rtnl_lock() held. */
1391 static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1393 struct efx_nic *efx = netdev_priv(net_dev);
1396 EFX_ASSERT_RESET_SERIALISED(efx);
1398 if (new_mtu > EFX_MAX_MTU)
1403 EFX_LOG(efx, "changing MTU to %d\n", new_mtu);
1405 efx_fini_channels(efx);
1406 net_dev->mtu = new_mtu;
1407 rc = efx_init_channels(efx);
1415 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1419 static int efx_set_mac_address(struct net_device *net_dev, void *data)
1421 struct efx_nic *efx = netdev_priv(net_dev);
1422 struct sockaddr *addr = data;
1423 char *new_addr = addr->sa_data;
1425 EFX_ASSERT_RESET_SERIALISED(efx);
1427 if (!is_valid_ether_addr(new_addr)) {
1428 DECLARE_MAC_BUF(mac);
1429 EFX_ERR(efx, "invalid ethernet MAC address requested: %s\n",
1430 print_mac(mac, new_addr));
1434 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
1436 /* Reconfigure the MAC */
1437 efx_reconfigure_port(efx);
1442 /* Context: netif_tx_lock held, BHs disabled. */
1443 static void efx_set_multicast_list(struct net_device *net_dev)
1445 struct efx_nic *efx = netdev_priv(net_dev);
1446 struct dev_mc_list *mc_list = net_dev->mc_list;
1447 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1453 /* Set per-MAC promiscuity flag and reconfigure MAC if necessary */
1454 promiscuous = !!(net_dev->flags & IFF_PROMISC);
1455 if (efx->promiscuous != promiscuous) {
1456 efx->promiscuous = promiscuous;
1457 /* Close the window between efx_stop_port() and efx_flush_all()
1458 * by only queuing work when the port is enabled. */
1459 if (efx->port_enabled)
1460 queue_work(efx->workqueue, &efx->reconfigure_work);
1463 /* Build multicast hash table */
1464 if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
1465 memset(mc_hash, 0xff, sizeof(*mc_hash));
1467 memset(mc_hash, 0x00, sizeof(*mc_hash));
1468 for (i = 0; i < net_dev->mc_count; i++) {
1469 crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr);
1470 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
1471 set_bit_le(bit, mc_hash->byte);
1472 mc_list = mc_list->next;
1476 /* Create and activate new global multicast hash table */
1477 falcon_set_multicast_hash(efx);
1480 static int efx_netdev_event(struct notifier_block *this,
1481 unsigned long event, void *ptr)
1483 struct net_device *net_dev = ptr;
1485 if (net_dev->open == efx_net_open && event == NETDEV_CHANGENAME) {
1486 struct efx_nic *efx = netdev_priv(net_dev);
1488 strcpy(efx->name, net_dev->name);
1494 static struct notifier_block efx_netdev_notifier = {
1495 .notifier_call = efx_netdev_event,
1498 static int efx_register_netdev(struct efx_nic *efx)
1500 struct net_device *net_dev = efx->net_dev;
1503 net_dev->watchdog_timeo = 5 * HZ;
1504 net_dev->irq = efx->pci_dev->irq;
1505 net_dev->open = efx_net_open;
1506 net_dev->stop = efx_net_stop;
1507 net_dev->get_stats = efx_net_stats;
1508 net_dev->tx_timeout = &efx_watchdog;
1509 net_dev->hard_start_xmit = efx_hard_start_xmit;
1510 net_dev->do_ioctl = efx_ioctl;
1511 net_dev->change_mtu = efx_change_mtu;
1512 net_dev->set_mac_address = efx_set_mac_address;
1513 net_dev->set_multicast_list = efx_set_multicast_list;
1514 #ifdef CONFIG_NET_POLL_CONTROLLER
1515 net_dev->poll_controller = efx_netpoll;
1517 SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev);
1518 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
1520 /* Always start with carrier off; PHY events will detect the link */
1521 netif_carrier_off(efx->net_dev);
1523 /* Clear MAC statistics */
1524 falcon_update_stats_xmac(efx);
1525 memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
1527 rc = register_netdev(net_dev);
1529 EFX_ERR(efx, "could not register net dev\n");
1532 strcpy(efx->name, net_dev->name);
1537 static void efx_unregister_netdev(struct efx_nic *efx)
1539 struct efx_tx_queue *tx_queue;
1544 BUG_ON(netdev_priv(efx->net_dev) != efx);
1546 /* Free up any skbs still remaining. This has to happen before
1547 * we try to unregister the netdev as running their destructors
1548 * may be needed to get the device ref. count to 0. */
1549 efx_for_each_tx_queue(tx_queue, efx)
1550 efx_release_tx_buffers(tx_queue);
1552 if (efx_dev_registered(efx)) {
1553 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
1554 unregister_netdev(efx->net_dev);
1558 /**************************************************************************
1560 * Device reset and suspend
1562 **************************************************************************/
1564 /* The final hardware and software finalisation before reset. */
1565 static int efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd)
1569 EFX_ASSERT_RESET_SERIALISED(efx);
1571 rc = falcon_xmac_get_settings(efx, ecmd);
1573 EFX_ERR(efx, "could not back up PHY settings\n");
1577 efx_fini_channels(efx);
1584 /* The first part of software initialisation after a hardware reset
1585 * This function does not handle serialisation with the kernel, it
1586 * assumes the caller has done this */
1587 static int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd)
1591 rc = efx_init_channels(efx);
1595 /* Restore MAC and PHY settings. */
1596 rc = falcon_xmac_set_settings(efx, ecmd);
1598 EFX_ERR(efx, "could not restore PHY settings\n");
1605 efx_fini_channels(efx);
1610 /* Reset the NIC as transparently as possible. Do not reset the PHY
1611 * Note that the reset may fail, in which case the card will be left
1612 * in a most-probably-unusable state.
1614 * This function will sleep. You cannot reset from within an atomic
1615 * state; use efx_schedule_reset() instead.
1617 * Grabs the rtnl_lock.
1619 static int efx_reset(struct efx_nic *efx)
1621 struct ethtool_cmd ecmd;
1622 enum reset_type method = efx->reset_pending;
1625 /* Serialise with kernel interfaces */
1628 /* If we're not RUNNING then don't reset. Leave the reset_pending
1629 * flag set so that efx_pci_probe_main will be retried */
1630 if (efx->state != STATE_RUNNING) {
1631 EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n");
1635 efx->state = STATE_RESETTING;
1636 EFX_INFO(efx, "resetting (%d)\n", method);
1638 /* The net_dev->get_stats handler is quite slow, and will fail
1639 * if a fetch is pending over reset. Serialise against it. */
1640 spin_lock(&efx->stats_lock);
1641 spin_unlock(&efx->stats_lock);
1644 mutex_lock(&efx->mac_lock);
1646 rc = efx_reset_down(efx, &ecmd);
1650 rc = falcon_reset_hw(efx, method);
1652 EFX_ERR(efx, "failed to reset hardware\n");
1656 /* Allow resets to be rescheduled. */
1657 efx->reset_pending = RESET_TYPE_NONE;
1659 /* Reinitialise bus-mastering, which may have been turned off before
1660 * the reset was scheduled. This is still appropriate, even in the
1661 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
1662 * can respond to requests. */
1663 pci_set_master(efx->pci_dev);
1665 /* Reinitialise device. This is appropriate in the RESET_TYPE_DISABLE
1666 * case so the driver can talk to external SRAM */
1667 rc = falcon_init_nic(efx);
1669 EFX_ERR(efx, "failed to initialise NIC\n");
1673 /* Leave device stopped if necessary */
1674 if (method == RESET_TYPE_DISABLE) {
1675 /* Reinitialise the device anyway so the driver unload sequence
1676 * can talk to the external SRAM */
1677 falcon_init_nic(efx);
1682 rc = efx_reset_up(efx, &ecmd);
1686 mutex_unlock(&efx->mac_lock);
1687 EFX_LOG(efx, "reset complete\n");
1689 efx->state = STATE_RUNNING;
1701 EFX_ERR(efx, "has been disabled\n");
1702 efx->state = STATE_DISABLED;
1704 mutex_unlock(&efx->mac_lock);
1706 efx_unregister_netdev(efx);
1711 /* The worker thread exists so that code that cannot sleep can
1712 * schedule a reset for later.
1714 static void efx_reset_work(struct work_struct *data)
1716 struct efx_nic *nic = container_of(data, struct efx_nic, reset_work);
1721 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
1723 enum reset_type method;
1725 if (efx->reset_pending != RESET_TYPE_NONE) {
1726 EFX_INFO(efx, "quenching already scheduled reset\n");
1731 case RESET_TYPE_INVISIBLE:
1732 case RESET_TYPE_ALL:
1733 case RESET_TYPE_WORLD:
1734 case RESET_TYPE_DISABLE:
1737 case RESET_TYPE_RX_RECOVERY:
1738 case RESET_TYPE_RX_DESC_FETCH:
1739 case RESET_TYPE_TX_DESC_FETCH:
1740 case RESET_TYPE_TX_SKIP:
1741 method = RESET_TYPE_INVISIBLE;
1744 method = RESET_TYPE_ALL;
1749 EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method);
1751 EFX_LOG(efx, "scheduling reset (%d)\n", method);
1753 efx->reset_pending = method;
1755 queue_work(efx->reset_workqueue, &efx->reset_work);
1758 /**************************************************************************
1760 * List of NICs we support
1762 **************************************************************************/
1764 /* PCI device ID table */
1765 static struct pci_device_id efx_pci_table[] __devinitdata = {
1766 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID),
1767 .driver_data = (unsigned long) &falcon_a_nic_type},
1768 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID),
1769 .driver_data = (unsigned long) &falcon_b_nic_type},
1770 {0} /* end of list */
1773 /**************************************************************************
1775 * Dummy PHY/MAC/Board operations
1777 * Can be used for some unimplemented operations
1778 * Needed so all function pointers are valid and do not have to be tested
1781 **************************************************************************/
1782 int efx_port_dummy_op_int(struct efx_nic *efx)
1786 void efx_port_dummy_op_void(struct efx_nic *efx) {}
1787 void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {}
1789 static struct efx_phy_operations efx_dummy_phy_operations = {
1790 .init = efx_port_dummy_op_int,
1791 .reconfigure = efx_port_dummy_op_void,
1792 .check_hw = efx_port_dummy_op_int,
1793 .fini = efx_port_dummy_op_void,
1794 .clear_interrupt = efx_port_dummy_op_void,
1795 .reset_xaui = efx_port_dummy_op_void,
1798 static struct efx_board efx_dummy_board_info = {
1799 .init = efx_port_dummy_op_int,
1800 .init_leds = efx_port_dummy_op_int,
1801 .set_fault_led = efx_port_dummy_op_blink,
1802 .blink = efx_port_dummy_op_blink,
1803 .fini = efx_port_dummy_op_void,
1806 /**************************************************************************
1810 **************************************************************************/
1812 /* This zeroes out and then fills in the invariants in a struct
1813 * efx_nic (including all sub-structures).
1815 static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type,
1816 struct pci_dev *pci_dev, struct net_device *net_dev)
1818 struct efx_channel *channel;
1819 struct efx_tx_queue *tx_queue;
1820 struct efx_rx_queue *rx_queue;
1823 /* Initialise common structures */
1824 memset(efx, 0, sizeof(*efx));
1825 spin_lock_init(&efx->biu_lock);
1826 spin_lock_init(&efx->phy_lock);
1827 INIT_WORK(&efx->reset_work, efx_reset_work);
1828 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
1829 efx->pci_dev = pci_dev;
1830 efx->state = STATE_INIT;
1831 efx->reset_pending = RESET_TYPE_NONE;
1832 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
1833 efx->board_info = efx_dummy_board_info;
1835 efx->net_dev = net_dev;
1836 efx->rx_checksum_enabled = true;
1837 spin_lock_init(&efx->netif_stop_lock);
1838 spin_lock_init(&efx->stats_lock);
1839 mutex_init(&efx->mac_lock);
1840 efx->phy_op = &efx_dummy_phy_operations;
1841 efx->mii.dev = net_dev;
1842 INIT_WORK(&efx->reconfigure_work, efx_reconfigure_work);
1843 atomic_set(&efx->netif_stop_count, 1);
1845 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
1846 channel = &efx->channel[i];
1848 channel->channel = i;
1849 channel->work_pending = false;
1851 for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) {
1852 tx_queue = &efx->tx_queue[i];
1853 tx_queue->efx = efx;
1854 tx_queue->queue = i;
1855 tx_queue->buffer = NULL;
1856 tx_queue->channel = &efx->channel[0]; /* for safety */
1857 tx_queue->tso_headers_free = NULL;
1859 for (i = 0; i < EFX_MAX_RX_QUEUES; i++) {
1860 rx_queue = &efx->rx_queue[i];
1861 rx_queue->efx = efx;
1862 rx_queue->queue = i;
1863 rx_queue->channel = &efx->channel[0]; /* for safety */
1864 rx_queue->buffer = NULL;
1865 spin_lock_init(&rx_queue->add_lock);
1866 INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work);
1871 /* Sanity-check NIC type */
1872 EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask &
1873 (efx->type->txd_ring_mask + 1));
1874 EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask &
1875 (efx->type->rxd_ring_mask + 1));
1876 EFX_BUG_ON_PARANOID(efx->type->evq_size &
1877 (efx->type->evq_size - 1));
1878 /* As close as we can get to guaranteeing that we don't overflow */
1879 EFX_BUG_ON_PARANOID(efx->type->evq_size <
1880 (efx->type->txd_ring_mask + 1 +
1881 efx->type->rxd_ring_mask + 1));
1882 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
1884 /* Higher numbered interrupt modes are less capable! */
1885 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
1888 efx->workqueue = create_singlethread_workqueue("sfc_work");
1889 if (!efx->workqueue) {
1894 efx->reset_workqueue = create_singlethread_workqueue("sfc_reset");
1895 if (!efx->reset_workqueue) {
1903 destroy_workqueue(efx->workqueue);
1904 efx->workqueue = NULL;
1910 static void efx_fini_struct(struct efx_nic *efx)
1912 if (efx->reset_workqueue) {
1913 destroy_workqueue(efx->reset_workqueue);
1914 efx->reset_workqueue = NULL;
1916 if (efx->workqueue) {
1917 destroy_workqueue(efx->workqueue);
1918 efx->workqueue = NULL;
1922 /**************************************************************************
1926 **************************************************************************/
1928 /* Main body of final NIC shutdown code
1929 * This is called only at module unload (or hotplug removal).
1931 static void efx_pci_remove_main(struct efx_nic *efx)
1933 EFX_ASSERT_RESET_SERIALISED(efx);
1935 /* Skip everything if we never obtained a valid membase */
1939 efx_fini_channels(efx);
1942 /* Shutdown the board, then the NIC and board state */
1943 efx->board_info.fini(efx);
1944 falcon_fini_interrupt(efx);
1947 efx_remove_all(efx);
1950 /* Final NIC shutdown
1951 * This is called only at module unload (or hotplug removal).
1953 static void efx_pci_remove(struct pci_dev *pci_dev)
1955 struct efx_nic *efx;
1957 efx = pci_get_drvdata(pci_dev);
1961 /* Mark the NIC as fini, then stop the interface */
1963 efx->state = STATE_FINI;
1964 dev_close(efx->net_dev);
1966 /* Allow any queued efx_resets() to complete */
1969 if (efx->membase == NULL)
1972 efx_unregister_netdev(efx);
1974 /* Wait for any scheduled resets to complete. No more will be
1975 * scheduled from this point because efx_stop_all() has been
1976 * called, we are no longer registered with driverlink, and
1977 * the net_device's have been removed. */
1978 flush_workqueue(efx->reset_workqueue);
1980 efx_pci_remove_main(efx);
1984 EFX_LOG(efx, "shutdown successful\n");
1986 pci_set_drvdata(pci_dev, NULL);
1987 efx_fini_struct(efx);
1988 free_netdev(efx->net_dev);
1991 /* Main body of NIC initialisation
1992 * This is called at module load (or hotplug insertion, theoretically).
1994 static int efx_pci_probe_main(struct efx_nic *efx)
1998 /* Do start-of-day initialisation */
1999 rc = efx_probe_all(efx);
2003 rc = efx_init_napi(efx);
2007 /* Initialise the board */
2008 rc = efx->board_info.init(efx);
2010 EFX_ERR(efx, "failed to initialise board\n");
2014 rc = falcon_init_nic(efx);
2016 EFX_ERR(efx, "failed to initialise NIC\n");
2020 rc = efx_init_port(efx);
2022 EFX_ERR(efx, "failed to initialise port\n");
2026 rc = efx_init_channels(efx);
2030 rc = falcon_init_interrupt(efx);
2037 efx_fini_channels(efx);
2045 efx_remove_all(efx);
2050 /* NIC initialisation
2052 * This is called at module load (or hotplug insertion,
2053 * theoretically). It sets up PCI mappings, tests and resets the NIC,
2054 * sets up and registers the network devices with the kernel and hooks
2055 * the interrupt service routine. It does not prepare the device for
2056 * transmission; this is left to the first time one of the network
2057 * interfaces is brought up (i.e. efx_net_open).
2059 static int __devinit efx_pci_probe(struct pci_dev *pci_dev,
2060 const struct pci_device_id *entry)
2062 struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data;
2063 struct net_device *net_dev;
2064 struct efx_nic *efx;
2067 /* Allocate and initialise a struct net_device and struct efx_nic */
2068 net_dev = alloc_etherdev(sizeof(*efx));
2071 net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG |
2072 NETIF_F_HIGHDMA | NETIF_F_TSO);
2074 net_dev->features |= NETIF_F_LRO;
2075 /* Mask for features that also apply to VLAN devices */
2076 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
2077 NETIF_F_HIGHDMA | NETIF_F_TSO);
2078 efx = netdev_priv(net_dev);
2079 pci_set_drvdata(pci_dev, efx);
2080 rc = efx_init_struct(efx, type, pci_dev, net_dev);
2084 EFX_INFO(efx, "Solarflare Communications NIC detected\n");
2086 /* Set up basic I/O (BAR mappings etc) */
2087 rc = efx_init_io(efx);
2091 /* No serialisation is required with the reset path because
2092 * we're in STATE_INIT. */
2093 for (i = 0; i < 5; i++) {
2094 rc = efx_pci_probe_main(efx);
2098 /* Serialise against efx_reset(). No more resets will be
2099 * scheduled since efx_stop_all() has been called, and we
2100 * have not and never have been registered with either
2101 * the rtnetlink or driverlink layers. */
2102 flush_workqueue(efx->reset_workqueue);
2104 /* Retry if a recoverably reset event has been scheduled */
2105 if ((efx->reset_pending != RESET_TYPE_INVISIBLE) &&
2106 (efx->reset_pending != RESET_TYPE_ALL))
2109 efx->reset_pending = RESET_TYPE_NONE;
2113 EFX_ERR(efx, "Could not reset NIC\n");
2117 /* Switch to the running state before we expose the device to
2118 * the OS. This is to ensure that the initial gathering of
2119 * MAC stats succeeds. */
2121 efx->state = STATE_RUNNING;
2124 rc = efx_register_netdev(efx);
2128 EFX_LOG(efx, "initialisation successful\n");
2133 efx_pci_remove_main(efx);
2138 efx_fini_struct(efx);
2140 EFX_LOG(efx, "initialisation failed. rc=%d\n", rc);
2141 free_netdev(net_dev);
2145 static struct pci_driver efx_pci_driver = {
2146 .name = EFX_DRIVER_NAME,
2147 .id_table = efx_pci_table,
2148 .probe = efx_pci_probe,
2149 .remove = efx_pci_remove,
2152 /**************************************************************************
2154 * Kernel module interface
2156 *************************************************************************/
2158 module_param(interrupt_mode, uint, 0444);
2159 MODULE_PARM_DESC(interrupt_mode,
2160 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2162 static int __init efx_init_module(void)
2166 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2168 rc = register_netdevice_notifier(&efx_netdev_notifier);
2172 refill_workqueue = create_workqueue("sfc_refill");
2173 if (!refill_workqueue) {
2178 rc = pci_register_driver(&efx_pci_driver);
2185 destroy_workqueue(refill_workqueue);
2187 unregister_netdevice_notifier(&efx_netdev_notifier);
2192 static void __exit efx_exit_module(void)
2194 printk(KERN_INFO "Solarflare NET driver unloading\n");
2196 pci_unregister_driver(&efx_pci_driver);
2197 destroy_workqueue(refill_workqueue);
2198 unregister_netdevice_notifier(&efx_netdev_notifier);
2202 module_init(efx_init_module);
2203 module_exit(efx_exit_module);
2205 MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and "
2206 "Solarflare Communications");
2207 MODULE_DESCRIPTION("Solarflare Communications network driver");
2208 MODULE_LICENSE("GPL");
2209 MODULE_DEVICE_TABLE(pci, efx_pci_table);