1 // SPDX-License-Identifier: GPL-2.0+
3 * rtl8169.c : U-Boot driver for the RealTek RTL8169
5 * Masami Komiya (mkomiya@sonare.it)
7 * Most part is taken from r8169.c of etherboot
11 /**************************************************************************
12 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
13 * Written 2003 by Timothy Legge <tlegge@rogers.com>
15 * Portions of this code based on:
16 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
17 * for Linux kernel 2.4.x.
19 * Written 2002 ShuChen <shuchen@realtek.com.tw>
20 * See Linux Driver for full information
22 * Linux Driver Version 1.27a, 10.02.2002
25 * Jean Chen of RealTek Semiconductor Corp. for
26 * providing the evaluation NIC used to develop
27 * this driver. RealTek's support for Etherboot
33 * v1.0 11-26-2003 timlegge Initial port of Linux driver
34 * v1.5 01-17-2004 timlegge Initial driver output cleanup
36 * Indent Options: indent -kr -i8
37 ***************************************************************************/
39 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
40 * Modified to use le32_to_cpu and cpu_to_le32 properly
50 #include <asm/cache.h>
53 #include <linux/delay.h>
56 #undef DEBUG_RTL8169_TX
57 #undef DEBUG_RTL8169_RX
59 #define drv_version "v1.5"
60 #define drv_date "01-17-2004"
62 static unsigned long ioaddr;
64 /* Condensed operations for readability. */
65 #define currticks() get_timer(0)
69 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
71 /* MAC address length*/
72 #define MAC_ADDR_LEN 6
74 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
75 #define MAX_ETH_FRAME_SIZE 1536
77 #define TX_FIFO_THRESH 256 /* In bytes */
79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
83 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
84 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
87 #ifdef CONFIG_SYS_RX_ETH_BUFFER
88 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
90 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
93 #define RX_BUF_LEN 8192
95 #define RTL_MIN_IO_SIZE 0x80
96 #define TX_TIMEOUT (6*HZ)
98 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
99 #define RTL_W8(reg, val8) writeb((val8), (void *)(ioaddr + (reg)))
100 #define RTL_W16(reg, val16) writew((val16), (void *)(ioaddr + (reg)))
101 #define RTL_W32(reg, val32) writel((val32), (void *)(ioaddr + (reg)))
102 #define RTL_R8(reg) readb((void *)(ioaddr + (reg)))
103 #define RTL_R16(reg) readw((void *)(ioaddr + (reg)))
104 #define RTL_R32(reg) readl((void *)(ioaddr + (reg)))
106 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
107 (pci_addr_t)(unsigned long)a)
108 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
111 enum RTL8169_registers {
112 MAC0 = 0, /* Ethernet hardware address. */
113 MAR0 = 8, /* Multicast filter. */
114 TxDescStartAddrLow = 0x20,
115 TxDescStartAddrHigh = 0x24,
116 TxHDescStartAddrLow = 0x28,
117 TxHDescStartAddrHigh = 0x2c,
122 IntrMask_8169 = 0x3C,
123 IntrStatus_8169 = 0x3E,
142 RxDescStartAddrLow = 0xE4,
143 RxDescStartAddrHigh = 0xE8,
146 FuncEventMask = 0xF4,
147 FuncPresetState = 0xF8,
148 FuncForceEvent = 0xFC,
151 enum RTL8125_registers {
152 IntrMask_8125 = 0x38,
153 IntrStatus_8125 = 0x3C,
157 enum RTL8169_register_content {
158 /*InterruptStatusBits */
162 TxDescUnavail = 0x80,
185 Cfg9346_Unlock = 0xC0,
190 AcceptBroadcast = 0x08,
191 AcceptMulticast = 0x04,
193 AcceptAllPhys = 0x01,
200 TxInterFrameGapShift = 24,
201 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
203 /*rtl8169_PHYstatus */
213 /*GIGABIT_PHY_registers */
216 PHY_AUTO_NEGO_REG = 4,
217 PHY_1000_CTRL_REG = 9,
219 /*GIGABIT_PHY_REG_BIT */
220 PHY_Restart_Auto_Nego = 0x0200,
221 PHY_Enable_Auto_Nego = 0x1000,
223 /* PHY_STAT_REG = 1; */
224 PHY_Auto_Nego_Comp = 0x0020,
226 /* PHY_AUTO_NEGO_REG = 4; */
227 PHY_Cap_10_Half = 0x0020,
228 PHY_Cap_10_Full = 0x0040,
229 PHY_Cap_100_Half = 0x0080,
230 PHY_Cap_100_Full = 0x0100,
232 /* PHY_1000_CTRL_REG = 9; */
233 PHY_Cap_1000_Full = 0x0200,
245 TBILinkOK = 0x02000000,
248 RxDv_Gated_En = 0x80000,
253 u8 version; /* depend on RTL8169 docs */
254 u32 RxConfigMask; /* should clear the bits supported by this chip */
255 } rtl_chip_info[] = {
256 {"RTL-8169", 0x00, 0xff7e1880,},
257 {"RTL-8169", 0x04, 0xff7e1880,},
258 {"RTL-8169", 0x00, 0xff7e1880,},
259 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
260 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
261 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
262 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
263 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
264 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
265 {"RTL-8168c/8111c", 0x3c, 0xff7e1880,},
266 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
267 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
268 {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
269 {"RTL-8101e", 0x34, 0xff7e1880,},
270 {"RTL-8100e", 0x32, 0xff7e1880,},
271 {"RTL-8168h/8111h", 0x54, 0xff7e1880,},
272 {"RTL-8125B", 0x64, 0xff7e1880,},
275 enum _DescStatusBit {
296 static unsigned char rxdata[RX_BUF_LEN];
298 #define RTL8169_DESC_SIZE 16
300 #if ARCH_DMA_MINALIGN > 256
301 # define RTL8169_ALIGN ARCH_DMA_MINALIGN
303 # define RTL8169_ALIGN 256
307 * Warn if the cache-line size is larger than the descriptor size. In such
308 * cases the driver will likely fail because the CPU needs to flush the cache
309 * when requeuing RX buffers, therefore descriptors written by the hardware
312 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
313 * the driver to allocate descriptors from a pool of non-cached memory.
315 * Hardware maintain D-cache coherency in RISC-V architecture.
317 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
318 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
319 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) && !defined(CONFIG_RISCV)
320 #warning cache-line size is larger than descriptor size
325 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
326 * descriptors point to a part of this buffer.
328 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
331 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
332 * descriptors point to a part of this buffer.
334 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
336 struct rtl8169_private {
338 void *mmio_addr; /* memory map physical address */
340 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
341 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
342 unsigned long dirty_tx;
343 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
344 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
345 unsigned char *RxBufferRings; /* Index of Rx Buffer */
346 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
347 unsigned char *Tx_skbuff[NUM_TX_DESC];
350 static struct rtl8169_private *tpc;
352 static const unsigned int rtl8169_rx_config =
353 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
355 static struct pci_device_id supported[] = {
356 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
357 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161) },
358 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
359 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
360 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
364 void mdio_write(int RegAddr, int value)
368 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
371 for (i = 2000; i > 0; i--) {
372 /* Check if the RTL8169 has completed writing to the specified MII register */
373 if (!(RTL_R32(PHYAR) & 0x80000000)) {
381 int mdio_read(int RegAddr)
385 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
388 for (i = 2000; i > 0; i--) {
389 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
390 if (RTL_R32(PHYAR) & 0x80000000) {
391 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
400 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
406 printf ("%s\n", __FUNCTION__);
410 /* Soft reset the chip. */
411 RTL_W8(ChipCmd, CmdReset);
413 /* Check that the chip has finished the reset. */
414 for (i = 1000; i > 0; i--)
415 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
420 /* identify chip attached to board */
421 tmp = RTL_R32(TxConfig);
422 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
424 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
425 if (tmp == rtl_chip_info[i].version) {
431 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
432 printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
434 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
442 * TX and RX descriptors are 16 bytes. This causes problems with the cache
443 * maintenance on CPUs where the cache-line size exceeds the size of these
444 * descriptors. What will happen is that when the driver receives a packet
445 * it will be immediately requeued for the hardware to reuse. The CPU will
446 * therefore need to flush the cache-line containing the descriptor, which
447 * will cause all other descriptors in the same cache-line to be flushed
448 * along with it. If one of those descriptors had been written to by the
449 * device those changes (and the associated packet) will be lost.
451 * To work around this, we make use of non-cached memory if available. If
452 * descriptors are mapped uncached there's no need to manually flush them
453 * or invalidate them.
455 * Note that this only applies to descriptors. The packet data buffers do
456 * not have the same constraints since they are 1536 bytes large, so they
457 * are unlikely to share cache-lines.
459 static void *rtl_alloc_descs(unsigned int num)
461 size_t size = num * RTL8169_DESC_SIZE;
463 #ifdef CONFIG_SYS_NONCACHED_MEMORY
464 return (void *)noncached_alloc(size, RTL8169_ALIGN);
466 return memalign(RTL8169_ALIGN, size);
471 * Cache maintenance functions. These are simple wrappers around the more
472 * general purpose flush_cache() and invalidate_dcache_range() functions.
475 static void rtl_inval_rx_desc(struct RxDesc *desc)
477 #ifndef CONFIG_SYS_NONCACHED_MEMORY
478 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
479 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
481 invalidate_dcache_range(start, end);
485 static void rtl_flush_rx_desc(struct RxDesc *desc)
487 #ifndef CONFIG_SYS_NONCACHED_MEMORY
488 flush_cache((unsigned long)desc, sizeof(*desc));
492 static void rtl_inval_tx_desc(struct TxDesc *desc)
494 #ifndef CONFIG_SYS_NONCACHED_MEMORY
495 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
496 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
498 invalidate_dcache_range(start, end);
502 static void rtl_flush_tx_desc(struct TxDesc *desc)
504 #ifndef CONFIG_SYS_NONCACHED_MEMORY
505 flush_cache((unsigned long)desc, sizeof(*desc));
509 static void rtl_inval_buffer(void *buf, size_t size)
511 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
512 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
514 invalidate_dcache_range(start, end);
517 static void rtl_flush_buffer(void *buf, size_t size)
519 flush_cache((unsigned long)buf, size);
522 /**************************************************************************
523 RECV - Receive a frame
524 ***************************************************************************/
525 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
528 /* return true if there's an ethernet packet ready to read */
529 /* nic->packet should contain data on return */
530 /* nic->packetlen should contain length of data */
531 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
535 #ifdef DEBUG_RTL8169_RX
536 printf ("%s\n", __FUNCTION__);
540 cur_rx = tpc->cur_rx;
542 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
544 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
545 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
546 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
547 status) & 0x00001FFF) - 4;
549 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
550 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
552 if (cur_rx == NUM_RX_DESC - 1)
553 tpc->RxDescArray[cur_rx].status =
554 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
556 tpc->RxDescArray[cur_rx].status =
557 cpu_to_le32(OWNbit + RX_BUF_SIZE);
558 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
559 dm_pci_mem_to_phys(dev,
560 (pci_addr_t)(unsigned long)
561 tpc->RxBufferRing[cur_rx]));
562 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
568 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
569 tpc->cur_rx = cur_rx;
573 u32 IntrStatus = IntrStatus_8169;
575 if (pplat->device == 0x8125)
576 IntrStatus = IntrStatus_8125;
577 ushort sts = RTL_R8(IntrStatus);
578 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
579 udelay(100); /* wait */
581 tpc->cur_rx = cur_rx;
582 return (0); /* initially as this is called to flush the input */
585 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
587 struct rtl8169_private *priv = dev_get_priv(dev);
589 return rtl_recv_common(dev, priv->iobase, packetp);
593 /**************************************************************************
594 SEND - Transmit a frame
595 ***************************************************************************/
596 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
597 void *packet, int length)
599 /* send the packet to destination */
601 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
604 int entry = tpc->cur_tx % NUM_TX_DESC;
608 #ifdef DEBUG_RTL8169_TX
609 int stime = currticks();
610 printf ("%s\n", __FUNCTION__);
611 printf("sending %d bytes\n", len);
616 /* point to the current txb incase multiple tx_rings are used */
617 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
618 memcpy(ptxb, (char *)packet, (int)length);
620 while (len < ETH_ZLEN)
623 rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
625 tpc->TxDescArray[entry].buf_Haddr = 0;
626 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
627 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
628 if (entry != (NUM_TX_DESC - 1)) {
629 tpc->TxDescArray[entry].status =
630 cpu_to_le32((OWNbit | FSbit | LSbit) |
631 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
633 tpc->TxDescArray[entry].status =
634 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
635 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
637 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
638 if (pplat->device == 0x8125)
639 RTL_W8(TxPoll_8125, 0x1); /* set polling bit */
641 RTL_W8(TxPoll_8169, 0x40); /* set polling bit */
644 to = currticks() + TX_TIMEOUT;
646 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
647 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
648 && (currticks() < to)); /* wait */
650 if (currticks() >= to) {
651 #ifdef DEBUG_RTL8169_TX
652 puts("tx timeout/error\n");
653 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
657 #ifdef DEBUG_RTL8169_TX
662 /* Delay to make net console (nc) work properly */
667 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
669 struct rtl8169_private *priv = dev_get_priv(dev);
671 return rtl_send_common(dev, priv->iobase, packet, length);
674 static void rtl8169_set_rx_mode(void)
676 u32 mc_filter[2]; /* Multicast hash filter */
681 printf ("%s\n", __FUNCTION__);
685 /* Too many to filter perfectly -- accept all multicasts. */
686 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
687 mc_filter[1] = mc_filter[0] = 0xffffffff;
689 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
690 rtl_chip_info[tpc->chipset].RxConfigMask);
692 RTL_W32(RxConfig, tmp);
693 RTL_W32(MAR0 + 0, mc_filter[0]);
694 RTL_W32(MAR0 + 4, mc_filter[1]);
697 static void rtl8169_hw_start(struct udevice *dev)
702 int stime = currticks();
703 printf ("%s\n", __FUNCTION__);
707 /* Soft reset the chip. */
708 RTL_W8(ChipCmd, CmdReset);
710 /* Check that the chip has finished the reset. */
711 for (i = 1000; i > 0; i--) {
712 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
719 RTL_W8(Cfg9346, Cfg9346_Unlock);
721 /* RTL-8169sb/8110sb or previous version */
722 if (tpc->chipset <= 5)
723 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
725 RTL_W8(EarlyTxThres, EarlyTxThld);
727 /* For gigabit rtl8169 */
728 RTL_W16(RxMaxSize, RxPacketMaxSize);
730 /* Set Rx Config register */
731 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
732 rtl_chip_info[tpc->chipset].RxConfigMask);
733 RTL_W32(RxConfig, i);
735 /* Set DMA burst size and Interframe Gap Time */
736 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
737 (InterFrameGap << TxInterFrameGapShift));
742 RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
743 (pci_addr_t)(unsigned long)tpc->TxDescArray));
744 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
745 RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
746 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
747 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
749 /* RTL-8169sc/8110sc or later version */
750 if (tpc->chipset > 5)
751 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
753 RTL_W8(Cfg9346, Cfg9346_Lock);
756 RTL_W32(RxMissed, 0);
758 rtl8169_set_rx_mode();
760 /* no early-rx interrupts */
761 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
764 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
768 static void rtl8169_init_ring(struct udevice *dev)
773 int stime = currticks();
774 printf ("%s\n", __FUNCTION__);
780 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
781 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
783 for (i = 0; i < NUM_TX_DESC; i++) {
784 tpc->Tx_skbuff[i] = &txb[i];
787 for (i = 0; i < NUM_RX_DESC; i++) {
788 if (i == (NUM_RX_DESC - 1))
789 tpc->RxDescArray[i].status =
790 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
792 tpc->RxDescArray[i].status =
793 cpu_to_le32(OWNbit + RX_BUF_SIZE);
795 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
796 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
797 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
798 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
802 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
806 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
807 unsigned long dev_iobase)
812 int stime = currticks();
813 printf ("%s\n", __FUNCTION__);
818 rtl8169_init_ring(dev);
819 rtl8169_hw_start(dev);
820 /* Construct a perfect filter frame with the mac address as first match
821 * and broadcast for all others */
822 for (i = 0; i < 192; i++)
825 txb[0] = enetaddr[0];
826 txb[1] = enetaddr[1];
827 txb[2] = enetaddr[2];
828 txb[3] = enetaddr[3];
829 txb[4] = enetaddr[4];
830 txb[5] = enetaddr[5];
833 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
837 static int rtl8169_eth_start(struct udevice *dev)
839 struct eth_pdata *plat = dev_get_plat(dev);
840 struct rtl8169_private *priv = dev_get_priv(dev);
842 rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
847 static void rtl_halt_common(struct udevice *dev)
849 struct rtl8169_private *priv = dev_get_priv(dev);
850 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
854 printf ("%s\n", __FUNCTION__);
857 ioaddr = priv->iobase;
859 /* Stop the chip's Tx and Rx DMA processes. */
860 RTL_W8(ChipCmd, 0x00);
862 /* Disable interrupts by clearing the interrupt mask. */
863 if (pplat->device == 0x8125)
864 RTL_W16(IntrMask_8125, 0x0000);
866 RTL_W16(IntrMask_8169, 0x0000);
868 RTL_W32(RxMissed, 0);
870 for (i = 0; i < NUM_RX_DESC; i++) {
871 tpc->RxBufferRing[i] = NULL;
875 void rtl8169_eth_stop(struct udevice *dev)
877 rtl_halt_common(dev);
880 static int rtl8169_write_hwaddr(struct udevice *dev)
882 struct eth_pdata *plat = dev_get_plat(dev);
885 RTL_W8(Cfg9346, Cfg9346_Unlock);
887 for (i = 0; i < MAC_ADDR_LEN; i++)
888 RTL_W8(MAC0 + i, plat->enetaddr[i]);
890 RTL_W8(Cfg9346, Cfg9346_Lock);
895 /**************************************************************************
896 INIT - Look for an adapter, this routine's visible to the outside
897 ***************************************************************************/
899 #define board_found 1
901 static int rtl_init(unsigned long dev_ioaddr, const char *name,
902 unsigned char *enetaddr)
904 static int board_idx = -1;
906 int option = -1, Cap10_100 = 0, Cap1000 = 0;
909 printf ("%s\n", __FUNCTION__);
915 /* point to private storage */
918 rc = rtl8169_init_board(ioaddr, name);
922 /* Get MAC address. FIXME: read EEPROM */
923 for (i = 0; i < MAC_ADDR_LEN; i++)
924 enetaddr[i] = RTL_R8(MAC0 + i);
927 printf("chipset = %d\n", tpc->chipset);
928 printf("MAC Address");
929 for (i = 0; i < MAC_ADDR_LEN; i++)
930 printf(":%02x", enetaddr[i]);
935 /* Print out some hardware info */
936 printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
939 /* if TBI is not endbled */
940 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
941 int val = mdio_read(PHY_AUTO_NEGO_REG);
943 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
944 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
947 printf("%s: Force-mode Enabled.\n", name);
949 Cap10_100 = 0, Cap1000 = 0;
952 Cap10_100 = PHY_Cap_10_Half;
953 Cap1000 = PHY_Cap_Null;
956 Cap10_100 = PHY_Cap_10_Full;
957 Cap1000 = PHY_Cap_Null;
960 Cap10_100 = PHY_Cap_100_Half;
961 Cap1000 = PHY_Cap_Null;
964 Cap10_100 = PHY_Cap_100_Full;
965 Cap1000 = PHY_Cap_Null;
968 Cap10_100 = PHY_Cap_Null;
969 Cap1000 = PHY_Cap_1000_Full;
974 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
975 mdio_write(PHY_1000_CTRL_REG, Cap1000);
978 printf("%s: Auto-negotiation Enabled.\n",
981 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
982 mdio_write(PHY_AUTO_NEGO_REG,
983 PHY_Cap_10_Half | PHY_Cap_10_Full |
984 PHY_Cap_100_Half | PHY_Cap_100_Full |
987 /* enable 1000 Full Mode */
988 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
992 /* Enable auto-negotiation and restart auto-nigotiation */
993 mdio_write(PHY_CTRL_REG,
994 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
997 /* wait for auto-negotiation process */
998 for (i = 10000; i > 0; i--) {
999 /* check if auto-negotiation complete */
1000 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
1002 option = RTL_R8(PHYstatus);
1003 if (option & _1000bpsF) {
1004 #ifdef DEBUG_RTL8169
1005 printf("%s: 1000Mbps Full-duplex operation.\n",
1009 #ifdef DEBUG_RTL8169
1010 printf("%s: %sMbps %s-duplex operation.\n",
1012 (option & _100bps) ? "100" :
1014 (option & FullDup) ? "Full" :
1022 } /* end for-loop to wait for auto-negotiation process */
1026 #ifdef DEBUG_RTL8169
1028 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1030 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1035 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1036 if (!tpc->RxDescArray)
1039 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1040 if (!tpc->TxDescArray)
1046 static int rtl8169_eth_probe(struct udevice *dev)
1048 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
1049 struct rtl8169_private *priv = dev_get_priv(dev);
1050 struct eth_pdata *plat = dev_get_plat(dev);
1054 switch (pplat->device) {
1065 priv->iobase = (ulong)dm_pci_map_bar(dev,
1066 PCI_BASE_ADDRESS_0 + region * 4,
1068 PCI_REGION_TYPE, PCI_REGION_MEM);
1070 debug("rtl8169: REALTEK RTL8169 @0x%lx\n", priv->iobase);
1071 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1073 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1078 * WAR for DHCP failure after rebooting from kernel.
1079 * Clear RxDv_Gated_En bit which was set by kernel driver.
1080 * Without this, U-Boot can't get an IP via DHCP.
1081 * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
1082 * the r8169.c kernel driver.
1085 u32 val = RTL_R32(FuncEvent);
1086 debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
1087 val &= ~RxDv_Gated_En;
1088 RTL_W32(FuncEvent, val);
1093 static const struct eth_ops rtl8169_eth_ops = {
1094 .start = rtl8169_eth_start,
1095 .send = rtl8169_eth_send,
1096 .recv = rtl8169_eth_recv,
1097 .stop = rtl8169_eth_stop,
1098 .write_hwaddr = rtl8169_write_hwaddr,
1101 static const struct udevice_id rtl8169_eth_ids[] = {
1102 { .compatible = "realtek,rtl8169" },
1106 U_BOOT_DRIVER(eth_rtl8169) = {
1107 .name = "eth_rtl8169",
1109 .of_match = rtl8169_eth_ids,
1110 .probe = rtl8169_eth_probe,
1111 .ops = &rtl8169_eth_ops,
1112 .priv_auto = sizeof(struct rtl8169_private),
1113 .plat_auto = sizeof(struct eth_pdata),
1116 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);