drivers/net/rtl8169.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rtl8169.c : U-Boot driver for the RealTek RTL8169
   4  *
   5  * Masami Komiya (mkomiya@sonare.it)
   6  *
   7  * Most part is taken from r8169.c of etherboot
   8  *
   9  */
  10
  11 /**************************************************************************
  12 *    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
  13 *    Written 2003 by Timothy Legge <tlegge@rogers.com>
  14 *
  15 *    Portions of this code based on:
  16 *       r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
  17 *               for Linux kernel 2.4.x.
  18 *
  19 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
  20 *         See Linux Driver for full information
  21 *
  22 *    Linux Driver Version 1.27a, 10.02.2002
  23 *
  24 *    Thanks to:
  25 *       Jean Chen of RealTek Semiconductor Corp. for
  26 *       providing the evaluation NIC used to develop
  27 *       this driver.  RealTek's support for Etherboot
  28 *       is appreciated.
  29 *
  30 *    REVISION HISTORY:
  31 *    ================
  32 *
  33 *    v1.0       11-26-2003      timlegge        Initial port of Linux driver
  34 *    v1.5       01-17-2004      timlegge        Initial driver output cleanup
  35 *
  36 *    Indent Options: indent -kr -i8
  37 ***************************************************************************/
  38 /*
  39  * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
  40  * Modified to use le32_to_cpu and cpu_to_le32 properly
  41  */
  42 #include <common.h>
  43 #include <cpu_func.h>
  44 #include <dm.h>
  45 #include <errno.h>
  46 #include <log.h>
  47 #include <malloc.h>
  48 #include <memalign.h>
  49 #include <net.h>
  50 #ifndef CONFIG_DM_ETH
  51 #include <netdev.h>
  52 #endif
  53 #include <asm/cache.h>
  54 #include <asm/io.h>
  55 #include <pci.h>
  56 #include <linux/delay.h>
  57
  58 #undef DEBUG_RTL8169
  59 #undef DEBUG_RTL8169_TX
  60 #undef DEBUG_RTL8169_RX
  61
  62 #define drv_version "v1.5"
  63 #define drv_date "01-17-2004"
  64
  65 static unsigned long ioaddr;
  66
  67 /* Condensed operations for readability. */
  68 #define currticks()     get_timer(0)
  69
  70 /* media options */
  71 #define MAX_UNITS 8
  72 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  73
  74 /* MAC address length*/
  75 #define MAC_ADDR_LEN    6
  76
  77 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
  78 #define MAX_ETH_FRAME_SIZE      1536
  79
  80 #define TX_FIFO_THRESH 256      /* In bytes */
  81
  82 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
  83 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  84 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  85 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  86 #define RxPacketMaxSize 0x0800  /* Maximum size supported is 16K-1 */
  87 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  88
  89 #define NUM_TX_DESC     1       /* Number of Tx descriptor registers */
  90 #ifdef CONFIG_SYS_RX_ETH_BUFFER
  91   #define NUM_RX_DESC   CONFIG_SYS_RX_ETH_BUFFER
  92 #else
  93   #define NUM_RX_DESC   4       /* Number of Rx descriptor registers */
  94 #endif
  95 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  96 #define RX_BUF_LEN      8192
  97
  98 #define RTL_MIN_IO_SIZE 0x80
  99 #define TX_TIMEOUT  (6*HZ)
 100
 101 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
 102 #define RTL_W8(reg, val8)       writeb((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb(ioaddr + (reg))
 106 #define RTL_R16(reg)            readw(ioaddr + (reg))
 107 #define RTL_R32(reg)            readl(ioaddr + (reg))
 108
 109 #define bus_to_phys(a)  pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
 110         (pci_addr_t)(unsigned long)a)
 111 #define phys_to_bus(a)  pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
 112         (phys_addr_t)a)
 113
 114 enum RTL8169_registers {
 115         MAC0 = 0,               /* Ethernet hardware address. */
 116         MAR0 = 8,               /* Multicast filter. */
 117         TxDescStartAddrLow = 0x20,
 118         TxDescStartAddrHigh = 0x24,
 119         TxHDescStartAddrLow = 0x28,
 120         TxHDescStartAddrHigh = 0x2c,
 121         FLASH = 0x30,
 122         ERSR = 0x36,
 123         ChipCmd = 0x37,
 124         TxPoll = 0x38,
 125         IntrMask = 0x3C,
 126         IntrStatus = 0x3E,
 127         TxConfig = 0x40,
 128         RxConfig = 0x44,
 129         RxMissed = 0x4C,
 130         Cfg9346 = 0x50,
 131         Config0 = 0x51,
 132         Config1 = 0x52,
 133         Config2 = 0x53,
 134         Config3 = 0x54,
 135         Config4 = 0x55,
 136         Config5 = 0x56,
 137         MultiIntr = 0x5C,
 138         PHYAR = 0x60,
 139         TBICSR = 0x64,
 140         TBI_ANAR = 0x68,
 141         TBI_LPAR = 0x6A,
 142         PHYstatus = 0x6C,
 143         RxMaxSize = 0xDA,
 144         CPlusCmd = 0xE0,
 145         RxDescStartAddrLow = 0xE4,
 146         RxDescStartAddrHigh = 0xE8,
 147         EarlyTxThres = 0xEC,
 148         FuncEvent = 0xF0,
 149         FuncEventMask = 0xF4,
 150         FuncPresetState = 0xF8,
 151         FuncForceEvent = 0xFC,
 152 };
 153
 154 enum RTL8169_register_content {
 155         /*InterruptStatusBits */
 156         SYSErr = 0x8000,
 157         PCSTimeout = 0x4000,
 158         SWInt = 0x0100,
 159         TxDescUnavail = 0x80,
 160         RxFIFOOver = 0x40,
 161         RxUnderrun = 0x20,
 162         RxOverflow = 0x10,
 163         TxErr = 0x08,
 164         TxOK = 0x04,
 165         RxErr = 0x02,
 166         RxOK = 0x01,
 167
 168         /*RxStatusDesc */
 169         RxRES = 0x00200000,
 170         RxCRC = 0x00080000,
 171         RxRUNT = 0x00100000,
 172         RxRWT = 0x00400000,
 173
 174         /*ChipCmdBits */
 175         CmdReset = 0x10,
 176         CmdRxEnb = 0x08,
 177         CmdTxEnb = 0x04,
 178         RxBufEmpty = 0x01,
 179
 180         /*Cfg9346Bits */
 181         Cfg9346_Lock = 0x00,
 182         Cfg9346_Unlock = 0xC0,
 183
 184         /*rx_mode_bits */
 185         AcceptErr = 0x20,
 186         AcceptRunt = 0x10,
 187         AcceptBroadcast = 0x08,
 188         AcceptMulticast = 0x04,
 189         AcceptMyPhys = 0x02,
 190         AcceptAllPhys = 0x01,
 191
 192         /*RxConfigBits */
 193         RxCfgFIFOShift = 13,
 194         RxCfgDMAShift = 8,
 195
 196         /*TxConfigBits */
 197         TxInterFrameGapShift = 24,
 198         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 199
 200         /*rtl8169_PHYstatus */
 201         TBI_Enable = 0x80,
 202         TxFlowCtrl = 0x40,
 203         RxFlowCtrl = 0x20,
 204         _1000bpsF = 0x10,
 205         _100bps = 0x08,
 206         _10bps = 0x04,
 207         LinkStatus = 0x02,
 208         FullDup = 0x01,
 209
 210         /*GIGABIT_PHY_registers */
 211         PHY_CTRL_REG = 0,
 212         PHY_STAT_REG = 1,
 213         PHY_AUTO_NEGO_REG = 4,
 214         PHY_1000_CTRL_REG = 9,
 215
 216         /*GIGABIT_PHY_REG_BIT */
 217         PHY_Restart_Auto_Nego = 0x0200,
 218         PHY_Enable_Auto_Nego = 0x1000,
 219
 220         /* PHY_STAT_REG = 1; */
 221         PHY_Auto_Nego_Comp = 0x0020,
 222
 223         /* PHY_AUTO_NEGO_REG = 4; */
 224         PHY_Cap_10_Half = 0x0020,
 225         PHY_Cap_10_Full = 0x0040,
 226         PHY_Cap_100_Half = 0x0080,
 227         PHY_Cap_100_Full = 0x0100,
 228
 229         /* PHY_1000_CTRL_REG = 9; */
 230         PHY_Cap_1000_Full = 0x0200,
 231
 232         PHY_Cap_Null = 0x0,
 233
 234         /*_MediaType*/
 235         _10_Half = 0x01,
 236         _10_Full = 0x02,
 237         _100_Half = 0x04,
 238         _100_Full = 0x08,
 239         _1000_Full = 0x10,
 240
 241         /*_TBICSRBit*/
 242         TBILinkOK = 0x02000000,
 243
 244         /* FuncEvent/Misc */
 245         RxDv_Gated_En = 0x80000,
 246 };
 247
 248 static struct {
 249         const char *name;
 250         u8 version;             /* depend on RTL8169 docs */
 251         u32 RxConfigMask;       /* should clear the bits supported by this chip */
 252 } rtl_chip_info[] = {
 253         {"RTL-8169", 0x00, 0xff7e1880,},
 254         {"RTL-8169", 0x04, 0xff7e1880,},
 255         {"RTL-8169", 0x00, 0xff7e1880,},
 256         {"RTL-8169s/8110s",     0x02, 0xff7e1880,},
 257         {"RTL-8169s/8110s",     0x04, 0xff7e1880,},
 258         {"RTL-8169sb/8110sb",   0x10, 0xff7e1880,},
 259         {"RTL-8169sc/8110sc",   0x18, 0xff7e1880,},
 260         {"RTL-8168b/8111sb",    0x30, 0xff7e1880,},
 261         {"RTL-8168b/8111sb",    0x38, 0xff7e1880,},
 262         {"RTL-8168c/8111c",     0x3c, 0xff7e1880,},
 263         {"RTL-8168d/8111d",     0x28, 0xff7e1880,},
 264         {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
 265         {"RTL-8168/8111g",      0x4c, 0xff7e1880,},
 266         {"RTL-8101e",           0x34, 0xff7e1880,},
 267         {"RTL-8100e",           0x32, 0xff7e1880,},
 268         {"RTL-8168h/8111h",     0x54, 0xff7e1880,},
 269 };
 270
 271 enum _DescStatusBit {
 272         OWNbit = 0x80000000,
 273         EORbit = 0x40000000,
 274         FSbit = 0x20000000,
 275         LSbit = 0x10000000,
 276 };
 277
 278 struct TxDesc {
 279         u32 status;
 280         u32 vlan_tag;
 281         u32 buf_addr;
 282         u32 buf_Haddr;
 283 };
 284
 285 struct RxDesc {
 286         u32 status;
 287         u32 vlan_tag;
 288         u32 buf_addr;
 289         u32 buf_Haddr;
 290 };
 291
 292 static unsigned char rxdata[RX_BUF_LEN];
 293
 294 #define RTL8169_DESC_SIZE 16
 295
 296 #if ARCH_DMA_MINALIGN > 256
 297 #  define RTL8169_ALIGN ARCH_DMA_MINALIGN
 298 #else
 299 #  define RTL8169_ALIGN 256
 300 #endif
 301
 302 /*
 303  * Warn if the cache-line size is larger than the descriptor size. In such
 304  * cases the driver will likely fail because the CPU needs to flush the cache
 305  * when requeuing RX buffers, therefore descriptors written by the hardware
 306  * may be discarded.
 307  *
 308  * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
 309  * the driver to allocate descriptors from a pool of non-cached memory.
 310  */
 311 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 312 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
 313         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
 314 #warning cache-line size is larger than descriptor size
 315 #endif
 316 #endif
 317
 318 /*
 319  * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
 320  * descriptors point to a part of this buffer.
 321  */
 322 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
 323
 324 /*
 325  * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
 326  * descriptors point to a part of this buffer.
 327  */
 328 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
 329
 330 struct rtl8169_private {
 331         ulong iobase;
 332         void *mmio_addr;        /* memory map physical address */
 333         int chipset;
 334         unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
 335         unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
 336         unsigned long dirty_tx;
 337         struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
 338         struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
 339         unsigned char *RxBufferRings;   /* Index of Rx Buffer  */
 340         unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
 341         unsigned char *Tx_skbuff[NUM_TX_DESC];
 342 } tpx;
 343
 344 static struct rtl8169_private *tpc;
 345
 346 static const unsigned int rtl8169_rx_config =
 347     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 348
 349 static struct pci_device_id supported[] = {
 350         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
 351         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
 352         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
 353         {}
 354 };
 355
 356 void mdio_write(int RegAddr, int value)
 357 {
 358         int i;
 359
 360         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
 361         udelay(1000);
 362
 363         for (i = 2000; i > 0; i--) {
 364                 /* Check if the RTL8169 has completed writing to the specified MII register */
 365                 if (!(RTL_R32(PHYAR) & 0x80000000)) {
 366                         break;
 367                 } else {
 368                         udelay(100);
 369                 }
 370         }
 371 }
 372
 373 int mdio_read(int RegAddr)
 374 {
 375         int i, value = -1;
 376
 377         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
 378         udelay(1000);
 379
 380         for (i = 2000; i > 0; i--) {
 381                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
 382                 if (RTL_R32(PHYAR) & 0x80000000) {
 383                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 384                         break;
 385                 } else {
 386                         udelay(100);
 387                 }
 388         }
 389         return value;
 390 }
 391
 392 static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
 393 {
 394         int i;
 395         u32 tmp;
 396
 397 #ifdef DEBUG_RTL8169
 398         printf ("%s\n", __FUNCTION__);
 399 #endif
 400         ioaddr = dev_iobase;
 401
 402         /* Soft reset the chip. */
 403         RTL_W8(ChipCmd, CmdReset);
 404
 405         /* Check that the chip has finished the reset. */
 406         for (i = 1000; i > 0; i--)
 407                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 408                         break;
 409                 else
 410                         udelay(10);
 411
 412         /* identify chip attached to board */
 413         tmp = RTL_R32(TxConfig);
 414         tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
 415
 416         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
 417                 if (tmp == rtl_chip_info[i].version) {
 418                         tpc->chipset = i;
 419                         goto match;
 420                 }
 421         }
 422
 423         /* if unknown chip, assume array element #0, original RTL-8169 in this case */
 424         printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
 425                name);
 426         printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
 427         tpc->chipset = 0;
 428
 429 match:
 430         return 0;
 431 }
 432
 433 /*
 434  * TX and RX descriptors are 16 bytes. This causes problems with the cache
 435  * maintenance on CPUs where the cache-line size exceeds the size of these
 436  * descriptors. What will happen is that when the driver receives a packet
 437  * it will be immediately requeued for the hardware to reuse. The CPU will
 438  * therefore need to flush the cache-line containing the descriptor, which
 439  * will cause all other descriptors in the same cache-line to be flushed
 440  * along with it. If one of those descriptors had been written to by the
 441  * device those changes (and the associated packet) will be lost.
 442  *
 443  * To work around this, we make use of non-cached memory if available. If
 444  * descriptors are mapped uncached there's no need to manually flush them
 445  * or invalidate them.
 446  *
 447  * Note that this only applies to descriptors. The packet data buffers do
 448  * not have the same constraints since they are 1536 bytes large, so they
 449  * are unlikely to share cache-lines.
 450  */
 451 static void *rtl_alloc_descs(unsigned int num)
 452 {
 453         size_t size = num * RTL8169_DESC_SIZE;
 454
 455 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 456         return (void *)noncached_alloc(size, RTL8169_ALIGN);
 457 #else
 458         return memalign(RTL8169_ALIGN, size);
 459 #endif
 460 }
 461
 462 /*
 463  * Cache maintenance functions. These are simple wrappers around the more
 464  * general purpose flush_cache() and invalidate_dcache_range() functions.
 465  */
 466
 467 static void rtl_inval_rx_desc(struct RxDesc *desc)
 468 {
 469 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 470         unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
 471         unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
 472
 473         invalidate_dcache_range(start, end);
 474 #endif
 475 }
 476
 477 static void rtl_flush_rx_desc(struct RxDesc *desc)
 478 {
 479 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 480         flush_cache((unsigned long)desc, sizeof(*desc));
 481 #endif
 482 }
 483
 484 static void rtl_inval_tx_desc(struct TxDesc *desc)
 485 {
 486 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 487         unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
 488         unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
 489
 490         invalidate_dcache_range(start, end);
 491 #endif
 492 }
 493
 494 static void rtl_flush_tx_desc(struct TxDesc *desc)
 495 {
 496 #ifndef CONFIG_SYS_NONCACHED_MEMORY
 497         flush_cache((unsigned long)desc, sizeof(*desc));
 498 #endif
 499 }
 500
 501 static void rtl_inval_buffer(void *buf, size_t size)
 502 {
 503         unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
 504         unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
 505
 506         invalidate_dcache_range(start, end);
 507 }
 508
 509 static void rtl_flush_buffer(void *buf, size_t size)
 510 {
 511         flush_cache((unsigned long)buf, size);
 512 }
 513
 514 /**************************************************************************
 515 RECV - Receive a frame
 516 ***************************************************************************/
 517 #ifdef CONFIG_DM_ETH
 518 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
 519                            uchar **packetp)
 520 #else
 521 static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
 522                            uchar **packetp)
 523 #endif
 524 {
 525         /* return true if there's an ethernet packet ready to read */
 526         /* nic->packet should contain data on return */
 527         /* nic->packetlen should contain length of data */
 528         int cur_rx;
 529         int length = 0;
 530
 531 #ifdef DEBUG_RTL8169_RX
 532         printf ("%s\n", __FUNCTION__);
 533 #endif
 534         ioaddr = dev_iobase;
 535
 536         cur_rx = tpc->cur_rx;
 537
 538         rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
 539
 540         if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
 541                 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 542                         length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
 543                                                 status) & 0x00001FFF) - 4;
 544
 545                         rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
 546                         memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
 547
 548                         if (cur_rx == NUM_RX_DESC - 1)
 549                                 tpc->RxDescArray[cur_rx].status =
 550                                         cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 551                         else
 552                                 tpc->RxDescArray[cur_rx].status =
 553                                         cpu_to_le32(OWNbit + RX_BUF_SIZE);
 554 #ifdef CONFIG_DM_ETH
 555                         tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
 556                                 dm_pci_mem_to_phys(dev,
 557                                         (pci_addr_t)(unsigned long)
 558                                         tpc->RxBufferRing[cur_rx]));
 559 #else
 560                         tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
 561                                 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
 562                                 tpc->RxBufferRing[cur_rx]));
 563 #endif
 564                         rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
 565 #ifdef CONFIG_DM_ETH
 566                         *packetp = rxdata;
 567 #else
 568                         net_process_received_packet(rxdata, length);
 569 #endif
 570                 } else {
 571                         puts("Error Rx");
 572                         length = -EIO;
 573                 }
 574                 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
 575                 tpc->cur_rx = cur_rx;
 576                 return length;
 577
 578         } else {
 579                 ushort sts = RTL_R8(IntrStatus);
 580                 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
 581                 udelay(100);    /* wait */
 582         }
 583         tpc->cur_rx = cur_rx;
 584         return (0);             /* initially as this is called to flush the input */
 585 }
 586
 587 #ifdef CONFIG_DM_ETH
 588 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 589 {
 590         struct rtl8169_private *priv = dev_get_priv(dev);
 591
 592         return rtl_recv_common(dev, priv->iobase, packetp);
 593 }
 594 #else
 595 static int rtl_recv(struct eth_device *dev)
 596 {
 597         return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
 598                                dev->iobase, NULL);
 599 }
 600 #endif /* nCONFIG_DM_ETH */
 601
 602 #define HZ 1000
 603 /**************************************************************************
 604 SEND - Transmit a frame
 605 ***************************************************************************/
 606 #ifdef CONFIG_DM_ETH
 607 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
 608                            void *packet, int length)
 609 #else
 610 static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
 611                            void *packet, int length)
 612 #endif
 613 {
 614         /* send the packet to destination */
 615
 616         u32 to;
 617         u8 *ptxb;
 618         int entry = tpc->cur_tx % NUM_TX_DESC;
 619         u32 len = length;
 620         int ret;
 621
 622 #ifdef DEBUG_RTL8169_TX
 623         int stime = currticks();
 624         printf ("%s\n", __FUNCTION__);
 625         printf("sending %d bytes\n", len);
 626 #endif
 627
 628         ioaddr = dev_iobase;
 629
 630         /* point to the current txb incase multiple tx_rings are used */
 631         ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
 632         memcpy(ptxb, (char *)packet, (int)length);
 633
 634         while (len < ETH_ZLEN)
 635                 ptxb[len++] = '\0';
 636
 637         rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
 638
 639         tpc->TxDescArray[entry].buf_Haddr = 0;
 640 #ifdef CONFIG_DM_ETH
 641         tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
 642                 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
 643 #else
 644         tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
 645                 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
 646 #endif
 647         if (entry != (NUM_TX_DESC - 1)) {
 648                 tpc->TxDescArray[entry].status =
 649                         cpu_to_le32((OWNbit | FSbit | LSbit) |
 650                                     ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 651         } else {
 652                 tpc->TxDescArray[entry].status =
 653                         cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
 654                                     ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 655         }
 656         rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
 657         RTL_W8(TxPoll, 0x40);   /* set polling bit */
 658
 659         tpc->cur_tx++;
 660         to = currticks() + TX_TIMEOUT;
 661         do {
 662                 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
 663         } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
 664                                 && (currticks() < to)); /* wait */
 665
 666         if (currticks() >= to) {
 667 #ifdef DEBUG_RTL8169_TX
 668                 puts("tx timeout/error\n");
 669                 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 670 #endif
 671                 ret = -ETIMEDOUT;
 672         } else {
 673 #ifdef DEBUG_RTL8169_TX
 674                 puts("tx done\n");
 675 #endif
 676                 ret = 0;
 677         }
 678         /* Delay to make net console (nc) work properly */
 679         udelay(20);
 680         return ret;
 681 }
 682
 683 #ifdef CONFIG_DM_ETH
 684 int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
 685 {
 686         struct rtl8169_private *priv = dev_get_priv(dev);
 687
 688         return rtl_send_common(dev, priv->iobase, packet, length);
 689 }
 690
 691 #else
 692 static int rtl_send(struct eth_device *dev, void *packet, int length)
 693 {
 694         return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
 695                                dev->iobase, packet, length);
 696 }
 697 #endif
 698
 699 static void rtl8169_set_rx_mode(void)
 700 {
 701         u32 mc_filter[2];       /* Multicast hash filter */
 702         int rx_mode;
 703         u32 tmp = 0;
 704
 705 #ifdef DEBUG_RTL8169
 706         printf ("%s\n", __FUNCTION__);
 707 #endif
 708
 709         /* IFF_ALLMULTI */
 710         /* Too many to filter perfectly -- accept all multicasts. */
 711         rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
 712         mc_filter[1] = mc_filter[0] = 0xffffffff;
 713
 714         tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
 715                                    rtl_chip_info[tpc->chipset].RxConfigMask);
 716
 717         RTL_W32(RxConfig, tmp);
 718         RTL_W32(MAR0 + 0, mc_filter[0]);
 719         RTL_W32(MAR0 + 4, mc_filter[1]);
 720 }
 721
 722 #ifdef CONFIG_DM_ETH
 723 static void rtl8169_hw_start(struct udevice *dev)
 724 #else
 725 static void rtl8169_hw_start(pci_dev_t dev)
 726 #endif
 727 {
 728         u32 i;
 729
 730 #ifdef DEBUG_RTL8169
 731         int stime = currticks();
 732         printf ("%s\n", __FUNCTION__);
 733 #endif
 734
 735 #if 0
 736         /* Soft reset the chip. */
 737         RTL_W8(ChipCmd, CmdReset);
 738
 739         /* Check that the chip has finished the reset. */
 740         for (i = 1000; i > 0; i--) {
 741                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 742                         break;
 743                 else
 744                         udelay(10);
 745         }
 746 #endif
 747
 748         RTL_W8(Cfg9346, Cfg9346_Unlock);
 749
 750         /* RTL-8169sb/8110sb or previous version */
 751         if (tpc->chipset <= 5)
 752                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 753
 754         RTL_W8(EarlyTxThres, EarlyTxThld);
 755
 756         /* For gigabit rtl8169 */
 757         RTL_W16(RxMaxSize, RxPacketMaxSize);
 758
 759         /* Set Rx Config register */
 760         i = rtl8169_rx_config | (RTL_R32(RxConfig) &
 761                                  rtl_chip_info[tpc->chipset].RxConfigMask);
 762         RTL_W32(RxConfig, i);
 763
 764         /* Set DMA burst size and Interframe Gap Time */
 765         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
 766                                 (InterFrameGap << TxInterFrameGapShift));
 767
 768
 769         tpc->cur_rx = 0;
 770
 771 #ifdef CONFIG_DM_ETH
 772         RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
 773                         (pci_addr_t)(unsigned long)tpc->TxDescArray));
 774 #else
 775         RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
 776                         (pci_addr_t)(unsigned long)tpc->TxDescArray));
 777 #endif
 778         RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
 779 #ifdef CONFIG_DM_ETH
 780         RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
 781                         dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
 782 #else
 783         RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
 784                         dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
 785 #endif
 786         RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
 787
 788         /* RTL-8169sc/8110sc or later version */
 789         if (tpc->chipset > 5)
 790                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 791
 792         RTL_W8(Cfg9346, Cfg9346_Lock);
 793         udelay(10);
 794
 795         RTL_W32(RxMissed, 0);
 796
 797         rtl8169_set_rx_mode();
 798
 799         /* no early-rx interrupts */
 800         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 801
 802 #ifdef DEBUG_RTL8169
 803         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 804 #endif
 805 }
 806
 807 #ifdef CONFIG_DM_ETH
 808 static void rtl8169_init_ring(struct udevice *dev)
 809 #else
 810 static void rtl8169_init_ring(pci_dev_t dev)
 811 #endif
 812 {
 813         int i;
 814
 815 #ifdef DEBUG_RTL8169
 816         int stime = currticks();
 817         printf ("%s\n", __FUNCTION__);
 818 #endif
 819
 820         tpc->cur_rx = 0;
 821         tpc->cur_tx = 0;
 822         tpc->dirty_tx = 0;
 823         memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
 824         memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
 825
 826         for (i = 0; i < NUM_TX_DESC; i++) {
 827                 tpc->Tx_skbuff[i] = &txb[i];
 828         }
 829
 830         for (i = 0; i < NUM_RX_DESC; i++) {
 831                 if (i == (NUM_RX_DESC - 1))
 832                         tpc->RxDescArray[i].status =
 833                                 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 834                 else
 835                         tpc->RxDescArray[i].status =
 836                                 cpu_to_le32(OWNbit + RX_BUF_SIZE);
 837
 838                 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 839 #ifdef CONFIG_DM_ETH
 840                 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
 841                         dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
 842 #else
 843                 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
 844                         dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
 845 #endif
 846                 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
 847         }
 848
 849 #ifdef DEBUG_RTL8169
 850         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 851 #endif
 852 }
 853
 854 #ifdef CONFIG_DM_ETH
 855 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
 856                                  unsigned long dev_iobase)
 857 #else
 858 static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
 859                                  unsigned long dev_iobase)
 860 #endif
 861 {
 862         int i;
 863
 864 #ifdef DEBUG_RTL8169
 865         int stime = currticks();
 866         printf ("%s\n", __FUNCTION__);
 867 #endif
 868
 869         ioaddr = dev_iobase;
 870
 871         rtl8169_init_ring(dev);
 872         rtl8169_hw_start(dev);
 873         /* Construct a perfect filter frame with the mac address as first match
 874          * and broadcast for all others */
 875         for (i = 0; i < 192; i++)
 876                 txb[i] = 0xFF;
 877
 878         txb[0] = enetaddr[0];
 879         txb[1] = enetaddr[1];
 880         txb[2] = enetaddr[2];
 881         txb[3] = enetaddr[3];
 882         txb[4] = enetaddr[4];
 883         txb[5] = enetaddr[5];
 884
 885 #ifdef DEBUG_RTL8169
 886         printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
 887 #endif
 888 }
 889
 890 #ifdef CONFIG_DM_ETH
 891 static int rtl8169_eth_start(struct udevice *dev)
 892 {
 893         struct eth_pdata *plat = dev_get_platdata(dev);
 894         struct rtl8169_private *priv = dev_get_priv(dev);
 895
 896         rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
 897
 898         return 0;
 899 }
 900 #else
 901 /**************************************************************************
 902 RESET - Finish setting up the ethernet interface
 903 ***************************************************************************/
 904 static int rtl_reset(struct eth_device *dev, bd_t *bis)
 905 {
 906         rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
 907                              dev->enetaddr, dev->iobase);
 908
 909         return 0;
 910 }
 911 #endif /* nCONFIG_DM_ETH */
 912
 913 static void rtl_halt_common(unsigned long dev_iobase)
 914 {
 915         int i;
 916
 917 #ifdef DEBUG_RTL8169
 918         printf ("%s\n", __FUNCTION__);
 919 #endif
 920
 921         ioaddr = dev_iobase;
 922
 923         /* Stop the chip's Tx and Rx DMA processes. */
 924         RTL_W8(ChipCmd, 0x00);
 925
 926         /* Disable interrupts by clearing the interrupt mask. */
 927         RTL_W16(IntrMask, 0x0000);
 928
 929         RTL_W32(RxMissed, 0);
 930
 931         for (i = 0; i < NUM_RX_DESC; i++) {
 932                 tpc->RxBufferRing[i] = NULL;
 933         }
 934 }
 935
 936 #ifdef CONFIG_DM_ETH
 937 void rtl8169_eth_stop(struct udevice *dev)
 938 {
 939         struct rtl8169_private *priv = dev_get_priv(dev);
 940
 941         rtl_halt_common(priv->iobase);
 942 }
 943 #else
 944 /**************************************************************************
 945 HALT - Turn off ethernet interface
 946 ***************************************************************************/
 947 static void rtl_halt(struct eth_device *dev)
 948 {
 949         rtl_halt_common(dev->iobase);
 950 }
 951 #endif
 952
 953 #ifdef CONFIG_DM_ETH
 954 static int rtl8169_write_hwaddr(struct udevice *dev)
 955 {
 956         struct eth_pdata *plat = dev_get_platdata(dev);
 957         unsigned int i;
 958
 959         RTL_W8(Cfg9346, Cfg9346_Unlock);
 960
 961         for (i = 0; i < MAC_ADDR_LEN; i++)
 962                 RTL_W8(MAC0 + i, plat->enetaddr[i]);
 963
 964         RTL_W8(Cfg9346, Cfg9346_Lock);
 965
 966         return 0;
 967 }
 968 #endif
 969
 970 /**************************************************************************
 971 INIT - Look for an adapter, this routine's visible to the outside
 972 ***************************************************************************/
 973
 974 #define board_found 1
 975 #define valid_link 0
 976 static int rtl_init(unsigned long dev_ioaddr, const char *name,
 977                     unsigned char *enetaddr)
 978 {
 979         static int board_idx = -1;
 980         int i, rc;
 981         int option = -1, Cap10_100 = 0, Cap1000 = 0;
 982
 983 #ifdef DEBUG_RTL8169
 984         printf ("%s\n", __FUNCTION__);
 985 #endif
 986         ioaddr = dev_ioaddr;
 987
 988         board_idx++;
 989
 990         /* point to private storage */
 991         tpc = &tpx;
 992
 993         rc = rtl8169_init_board(ioaddr, name);
 994         if (rc)
 995                 return rc;
 996
 997         /* Get MAC address.  FIXME: read EEPROM */
 998         for (i = 0; i < MAC_ADDR_LEN; i++)
 999                 enetaddr[i] = RTL_R8(MAC0 + i);
1000
1001 #ifdef DEBUG_RTL8169
1002         printf("chipset = %d\n", tpc->chipset);
1003         printf("MAC Address");
1004         for (i = 0; i < MAC_ADDR_LEN; i++)
1005                 printf(":%02x", enetaddr[i]);
1006         putc('\n');
1007 #endif
1008
1009 #ifdef DEBUG_RTL8169
1010         /* Print out some hardware info */
1011         printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
1012 #endif
1013
1014         /* if TBI is not endbled */
1015         if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
1016                 int val = mdio_read(PHY_AUTO_NEGO_REG);
1017
1018                 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1019                 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
1020                 if (option > 0) {
1021 #ifdef DEBUG_RTL8169
1022                         printf("%s: Force-mode Enabled.\n", name);
1023 #endif
1024                         Cap10_100 = 0, Cap1000 = 0;
1025                         switch (option) {
1026                         case _10_Half:
1027                                 Cap10_100 = PHY_Cap_10_Half;
1028                                 Cap1000 = PHY_Cap_Null;
1029                                 break;
1030                         case _10_Full:
1031                                 Cap10_100 = PHY_Cap_10_Full;
1032                                 Cap1000 = PHY_Cap_Null;
1033                                 break;
1034                         case _100_Half:
1035                                 Cap10_100 = PHY_Cap_100_Half;
1036                                 Cap1000 = PHY_Cap_Null;
1037                                 break;
1038                         case _100_Full:
1039                                 Cap10_100 = PHY_Cap_100_Full;
1040                                 Cap1000 = PHY_Cap_Null;
1041                                 break;
1042                         case _1000_Full:
1043                                 Cap10_100 = PHY_Cap_Null;
1044                                 Cap1000 = PHY_Cap_1000_Full;
1045                                 break;
1046                         default:
1047                                 break;
1048                         }
1049                         mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F));        /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1050                         mdio_write(PHY_1000_CTRL_REG, Cap1000);
1051                 } else {
1052 #ifdef DEBUG_RTL8169
1053                         printf("%s: Auto-negotiation Enabled.\n",
1054                                name);
1055 #endif
1056                         /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
1057                         mdio_write(PHY_AUTO_NEGO_REG,
1058                                    PHY_Cap_10_Half | PHY_Cap_10_Full |
1059                                    PHY_Cap_100_Half | PHY_Cap_100_Full |
1060                                    (val & 0x1F));
1061
1062                         /* enable 1000 Full Mode */
1063                         mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
1064
1065                 }
1066
1067                 /* Enable auto-negotiation and restart auto-nigotiation */
1068                 mdio_write(PHY_CTRL_REG,
1069                            PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
1070                 udelay(100);
1071
1072                 /* wait for auto-negotiation process */
1073                 for (i = 10000; i > 0; i--) {
1074                         /* check if auto-negotiation complete */
1075                         if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
1076                                 udelay(100);
1077                                 option = RTL_R8(PHYstatus);
1078                                 if (option & _1000bpsF) {
1079 #ifdef DEBUG_RTL8169
1080                                         printf("%s: 1000Mbps Full-duplex operation.\n",
1081                                                name);
1082 #endif
1083                                 } else {
1084 #ifdef DEBUG_RTL8169
1085                                         printf("%s: %sMbps %s-duplex operation.\n",
1086                                                name,
1087                                                (option & _100bps) ? "100" :
1088                                                "10",
1089                                                (option & FullDup) ? "Full" :
1090                                                "Half");
1091 #endif
1092                                 }
1093                                 break;
1094                         } else {
1095                                 udelay(100);
1096                         }
1097                 }               /* end for-loop to wait for auto-negotiation process */
1098
1099         } else {
1100                 udelay(100);
1101 #ifdef DEBUG_RTL8169
1102                 printf
1103                     ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1104                      name,
1105                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1106 #endif
1107         }
1108
1109
1110         tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
1111         if (!tpc->RxDescArray)
1112                 return -ENOMEM;
1113
1114         tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
1115         if (!tpc->TxDescArray)
1116                 return -ENOMEM;
1117
1118         return 0;
1119 }
1120
1121 #ifndef CONFIG_DM_ETH
1122 int rtl8169_initialize(bd_t *bis)
1123 {
1124         pci_dev_t devno;
1125         int card_number = 0;
1126         struct eth_device *dev;
1127         u32 iobase;
1128         int idx=0;
1129
1130         while(1){
1131                 unsigned int region;
1132                 u16 device;
1133                 int err;
1134
1135                 /* Find RTL8169 */
1136                 if ((devno = pci_find_devices(supported, idx++)) < 0)
1137                         break;
1138
1139                 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
1140                 switch (device) {
1141                 case 0x8168:
1142                         region = 2;
1143                         break;
1144
1145                 default:
1146                         region = 1;
1147                         break;
1148                 }
1149
1150                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
1151                 iobase &= ~0xf;
1152
1153                 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1154
1155                 dev = (struct eth_device *)malloc(sizeof *dev);
1156                 if (!dev) {
1157                         printf("Can not allocate memory of rtl8169\n");
1158                         break;
1159                 }
1160
1161                 memset(dev, 0, sizeof(*dev));
1162                 sprintf (dev->name, "RTL8169#%d", card_number);
1163
1164                 dev->priv = (void *)(unsigned long)devno;
1165                 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1166
1167                 dev->init = rtl_reset;
1168                 dev->halt = rtl_halt;
1169                 dev->send = rtl_send;
1170                 dev->recv = rtl_recv;
1171
1172                 err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
1173                 if (err < 0) {
1174                         printf(pr_fmt("failed to initialize card: %d\n"), err);
1175                         free(dev);
1176                         continue;
1177                 }
1178
1179                 eth_register (dev);
1180
1181                 card_number++;
1182         }
1183         return card_number;
1184 }
1185 #endif
1186
1187 #ifdef CONFIG_DM_ETH
1188 static int rtl8169_eth_probe(struct udevice *dev)
1189 {
1190         struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
1191         struct rtl8169_private *priv = dev_get_priv(dev);
1192         struct eth_pdata *plat = dev_get_platdata(dev);
1193         u32 iobase;
1194         int region;
1195         int ret;
1196
1197         debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
1198         switch (pplat->device) {
1199         case 0x8168:
1200                 region = 2;
1201                 break;
1202         default:
1203                 region = 1;
1204                 break;
1205         }
1206         dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
1207         iobase &= ~0xf;
1208         priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
1209
1210         ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
1211         if (ret < 0) {
1212                 printf(pr_fmt("failed to initialize card: %d\n"), ret);
1213                 return ret;
1214         }
1215
1216         /*
1217          * WAR for DHCP failure after rebooting from kernel.
1218          * Clear RxDv_Gated_En bit which was set by kernel driver.
1219          * Without this, U-Boot can't get an IP via DHCP.
1220          * Register (FuncEvent, aka MISC) and RXDV_GATED_EN bit are from
1221          * the r8169.c kernel driver.
1222          */
1223
1224         u32 val = RTL_R32(FuncEvent);
1225         debug("%s: FuncEvent/Misc (0xF0) = 0x%08X\n", __func__, val);
1226         val &= ~RxDv_Gated_En;
1227         RTL_W32(FuncEvent, val);
1228
1229         return 0;
1230 }
1231
1232 static const struct eth_ops rtl8169_eth_ops = {
1233         .start  = rtl8169_eth_start,
1234         .send   = rtl8169_eth_send,
1235         .recv   = rtl8169_eth_recv,
1236         .stop   = rtl8169_eth_stop,
1237         .write_hwaddr = rtl8169_write_hwaddr,
1238 };
1239
1240 static const struct udevice_id rtl8169_eth_ids[] = {
1241         { .compatible = "realtek,rtl8169" },
1242         { }
1243 };
1244
1245 U_BOOT_DRIVER(eth_rtl8169) = {
1246         .name   = "eth_rtl8169",
1247         .id     = UCLASS_ETH,
1248         .of_match = rtl8169_eth_ids,
1249         .probe  = rtl8169_eth_probe,
1250         .ops    = &rtl8169_eth_ops,
1251         .priv_auto_alloc_size = sizeof(struct rtl8169_private),
1252         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1253 };
1254
1255 U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
1256 #endif