2 * rtl8139.c : U-Boot driver for the RealTek RTL8139
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from rtl8139.c of etherboot
10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
12 ported from the linux driver written by Donald Becker
13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
15 This software may be used and distributed according to the terms
16 of the GNU Public License, incorporated herein by reference.
18 changes to the original driver:
19 - removed support for interrupts, switching to polling mode (yuck!)
20 - removed support for the 8129 chip (external MII)
24 /*********************************************************************/
25 /* Revision History */
26 /*********************************************************************/
29 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
30 Put in virt_to_bus calls to allow Etherboot relocation.
32 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
33 Following email from Hyun-Joon Cha, added a disable routine, otherwise
34 NIC remains live and can crash the kernel later.
36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
37 Shuffled things around, removed the leftovers from the 8129 support
38 that was in the Linux driver and added a bit more 8139 definitions.
39 Moved the 8K receive buffer to a fixed, available address outside the
40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
41 way to make room for the Etherboot features that need substantial amounts
42 of code like the ANSI console support. Currently the buffer is just below
43 0x10000, so this even conforms to the tagged boot image specification,
44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
45 interpretation of this "reserved" is that Etherboot may do whatever it
46 likes, as long as its environment is kept intact (like the BIOS
47 variables). Hopefully fixed rtl_poll() once and for all. The symptoms
48 were that if Etherboot was left at the boot menu for several minutes, the
49 first eth_poll failed. Seems like I am the only person who does this.
50 First of all I fixed the debugging code and then set out for a long bug
51 hunting session. It took me about a week full time work - poking around
52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux
53 driver and even the FreeBSD driver (what a piece of crap!) - and
54 eventually spotted the nasty thing: the transmit routine was acknowledging
55 each and every interrupt pending, including the RxOverrun and RxFIFIOver
56 interrupts. This confused the RTL8139 thoroughly. It destroyed the
57 Rx ring contents by dumping the 2K FIFO contents right where we wanted to
58 get the next packet. Oh well, what fun.
60 18 Jan 2000 mdc@thinguin.org (Marty Connor)
61 Drastically simplified error handling. Basically, if any error
62 in transmission or reception occurs, the card is reset.
63 Also, pointed all transmit descriptors to the same buffer to
64 save buffer space. This should decrease driver size and avoid
65 corruption because of exceeding 32K during runtime.
67 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
68 rtl_poll was quite broken: it used the RxOK interrupt flag instead
69 of the RxBufferEmpty flag which often resulted in very bad
70 transmission performace - below 1kBytes/s.
82 #define RTL_TIMEOUT 100000
84 /* PCI Tuning Parameters
85 Threshold is bytes transferred to chip before transmission starts. */
86 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
87 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
88 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
89 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
90 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
91 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
92 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
93 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
95 #define DEBUG_TX 0 /* set to 1 to enable debug code */
96 #define DEBUG_RX 0 /* set to 1 to enable debug code */
98 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
99 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
101 /* Symbolic offsets to registers. */
102 /* Ethernet hardware address. */
103 #define RTL_REG_MAC0 0x00
104 /* Multicast filter. */
105 #define RTL_REG_MAR0 0x08
106 /* Transmit status (four 32bit registers). */
107 #define RTL_REG_TXSTATUS0 0x10
108 /* Tx descriptors (also four 32bit). */
109 #define RTL_REG_TXADDR0 0x20
110 #define RTL_REG_RXBUF 0x30
111 #define RTL_REG_RXEARLYCNT 0x34
112 #define RTL_REG_RXEARLYSTATUS 0x36
113 #define RTL_REG_CHIPCMD 0x37
114 #define RTL_REG_CHIPCMD_CMDRESET BIT(4)
115 #define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
116 #define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
117 #define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
118 #define RTL_REG_RXBUFPTR 0x38
119 #define RTL_REG_RXBUFADDR 0x3A
120 #define RTL_REG_INTRMASK 0x3C
121 #define RTL_REG_INTRSTATUS 0x3E
122 #define RTL_REG_INTRSTATUS_PCIERR BIT(15)
123 #define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
124 #define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
125 #define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
126 #define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
127 #define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
128 #define RTL_REG_INTRSTATUS_TXERR BIT(3)
129 #define RTL_REG_INTRSTATUS_TXOK BIT(2)
130 #define RTL_REG_INTRSTATUS_RXERR BIT(1)
131 #define RTL_REG_INTRSTATUS_RXOK BIT(0)
132 #define RTL_REG_TXCONFIG 0x40
133 #define RTL_REG_RXCONFIG 0x44
134 #define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
135 #define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
136 #define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
137 #define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
138 #define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
139 #define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
140 #define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
141 /* general-purpose counter. */
142 #define RTL_REG_TIMER 0x48
143 /* 24 bits valid, write clears. */
144 #define RTL_REG_RXMISSED 0x4C
145 #define RTL_REG_CFG9346 0x50
146 #define RTL_REG_CONFIG0 0x51
147 #define RTL_REG_CONFIG1 0x52
148 /* intr if gp counter reaches this value */
149 #define RTL_REG_TIMERINTRREG 0x54
150 #define RTL_REG_MEDIASTATUS 0x58
151 #define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
152 #define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
153 #define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
154 #define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
155 #define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
156 #define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
157 #define RTL_REG_CONFIG3 0x59
158 #define RTL_REG_MULTIINTR 0x5C
159 /* revision of the RTL8139 chip */
160 #define RTL_REG_REVISIONID 0x5E
161 #define RTL_REG_TXSUMMARY 0x60
162 #define RTL_REG_MII_BMCR 0x62
163 #define RTL_REG_MII_BMSR 0x64
164 #define RTL_REG_NWAYADVERT 0x66
165 #define RTL_REG_NWAYLPAR 0x68
166 #define RTL_REG_NWAYEXPANSION 0x6A
167 #define RTL_REG_DISCONNECTCNT 0x6C
168 #define RTL_REG_FALSECARRIERCNT 0x6E
169 #define RTL_REG_NWAYTESTREG 0x70
170 /* packet received counter */
171 #define RTL_REG_RXCNT 0x72
172 /* chip status and configuration register */
173 #define RTL_REG_CSCR 0x74
174 #define RTL_REG_PHYPARM1 0x78
175 #define RTL_REG_TWISTERPARM 0x7c
177 #define RTL_REG_PHYPARM2 0x80
179 * from 0x84 onwards are a number of power management/wakeup frame
180 * definitions we will probably never need to know about.
183 #define RTL_STS_RXMULTICAST BIT(15)
184 #define RTL_STS_RXPHYSICAL BIT(14)
185 #define RTL_STS_RXBROADCAST BIT(13)
186 #define RTL_STS_RXBADSYMBOL BIT(5)
187 #define RTL_STS_RXRUNT BIT(4)
188 #define RTL_STS_RXTOOLONG BIT(3)
189 #define RTL_STS_RXCRCERR BIT(2)
190 #define RTL_STS_RXBADALIGN BIT(1)
191 #define RTL_STS_RXSTATUSOK BIT(0)
194 static unsigned int cur_rx,cur_tx;
196 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
197 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
198 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
200 static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
201 static int read_eeprom(int location, int addr_len);
202 static void rtl_reset(struct eth_device *dev);
203 static int rtl_transmit(struct eth_device *dev, void *packet, int length);
204 static int rtl_poll(struct eth_device *dev);
205 static void rtl_disable(struct eth_device *dev);
206 static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
211 static struct pci_device_id supported[] = {
212 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
213 {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
217 int rtl8139_initialize(bd_t *bis)
221 struct eth_device *dev;
227 if ((devno = pci_find_devices(supported, idx++)) < 0)
230 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
233 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
235 dev = (struct eth_device *)malloc(sizeof *dev);
237 printf("Can not allocate memory of rtl8139\n");
240 memset(dev, 0, sizeof(*dev));
242 sprintf (dev->name, "RTL8139#%d", card_number);
244 dev->priv = (void *) devno;
245 dev->iobase = (int)bus_to_phys(iobase);
246 dev->init = rtl8139_probe;
247 dev->halt = rtl_disable;
248 dev->send = rtl_transmit;
249 dev->recv = rtl_poll;
250 dev->mcast = rtl_bcast_addr;
256 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
264 static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
268 unsigned short *ap = (unsigned short *)dev->enetaddr;
270 ioaddr = dev->iobase;
272 /* Bring the chip out of low-power mode. */
273 outb(0x00, ioaddr + RTL_REG_CONFIG1);
275 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
276 for (i = 0; i < 3; i++)
277 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
281 if (inb(ioaddr + RTL_REG_MEDIASTATUS) & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
282 printf("Cable not connected or other link failure\n");
289 /* Serial EEPROM section. */
291 /* EEPROM_Ctrl bits. */
292 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
293 #define EE_CS 0x08 /* EEPROM chip select. */
294 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
295 #define EE_WRITE_0 0x00
296 #define EE_WRITE_1 0x02
297 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
298 #define EE_ENB (0x80 | EE_CS)
301 Delay between EEPROM clock transitions.
302 No extra delay is needed with 33MHz PCI, but 66MHz may change this.
305 #define eeprom_delay() inl(ee_addr)
307 /* The EEPROM commands include the alway-set leading bit. */
308 #define EE_WRITE_CMD 5
309 #define EE_READ_CMD 6
310 #define EE_ERASE_CMD 7
312 static int read_eeprom(int location, int addr_len)
315 unsigned int retval = 0;
316 long ee_addr = ioaddr + RTL_REG_CFG9346;
317 int read_cmd = location | (EE_READ_CMD << addr_len);
319 outb(EE_ENB & ~EE_CS, ee_addr);
320 outb(EE_ENB, ee_addr);
323 /* Shift the read command bits out. */
324 for (i = 4 + addr_len; i >= 0; i--) {
325 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
326 outb(EE_ENB | dataval, ee_addr);
328 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
331 outb(EE_ENB, ee_addr);
334 for (i = 16; i > 0; i--) {
335 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
337 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
338 outb(EE_ENB, ee_addr);
342 /* Terminate the EEPROM access. */
343 outb(~EE_CS, ee_addr);
348 static const unsigned int rtl8139_rx_config =
349 (RX_BUF_LEN_IDX << 11) |
350 (RX_FIFO_THRESH << 13) |
353 static void set_rx_mode(struct eth_device *dev) {
354 unsigned int mc_filter[2];
357 rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
358 RTL_REG_RXCONFIG_ACCEPTMULTICAST |
359 RTL_REG_RXCONFIG_ACCEPTMYPHYS;
360 mc_filter[1] = mc_filter[0] = 0xffffffff;
362 outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
364 outl(mc_filter[0], ioaddr + RTL_REG_MAR0 + 0);
365 outl(mc_filter[1], ioaddr + RTL_REG_MAR0 + 4);
368 static void rtl_reset(struct eth_device *dev)
372 outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
377 /* Give the chip 10ms to finish the reset. */
378 for (i=0; i<100; ++i){
379 if ((inb(ioaddr + RTL_REG_CHIPCMD) &
380 RTL_REG_CHIPCMD_CMDRESET) == 0)
382 udelay (100); /* wait 100us */
386 for (i = 0; i < ETH_ALEN; i++)
387 outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
389 /* Must enable Tx/Rx before setting transfer thresholds! */
390 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
391 ioaddr + RTL_REG_CHIPCMD);
392 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
393 ioaddr + RTL_REG_RXCONFIG); /* accept no frames yet! */
394 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + RTL_REG_TXCONFIG);
396 /* The Linux driver changes RTL_REG_CONFIG1 here to use a different LED pattern
397 * for half duplex or full/autodetect duplex (for full/autodetect, the
398 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
399 * TX/RX, Link100, Link10). This is messy, because it doesn't match
400 * the inscription on the mounting bracket. It should not be changed
401 * from the configuration EEPROM default, because the card manufacturer
402 * should have set that to match the card. */
405 "rx ring address is %lX\n",(unsigned long)rx_ring);
406 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
407 outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
409 /* If we add multicast support, the RTL_REG_MAR0 register would have to be
410 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
411 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
413 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
414 ioaddr + RTL_REG_CHIPCMD);
416 outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
418 /* Start the chip's Tx and Rx process. */
419 outl(0, ioaddr + RTL_REG_RXMISSED);
424 /* Disable all known interrupts by setting the interrupt mask. */
425 outw(0, ioaddr + RTL_REG_INTRMASK);
428 static int rtl_transmit(struct eth_device *dev, void *packet, int length)
431 unsigned long txstatus;
432 unsigned int len = length;
435 ioaddr = dev->iobase;
437 memcpy((char *)tx_buffer, (char *)packet, (int)length);
439 debug_cond(DEBUG_TX, "sending %d bytes\n", len);
441 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
442 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
443 while (len < ETH_ZLEN) {
444 tx_buffer[len++] = '\0';
447 flush_cache((unsigned long)tx_buffer, length);
448 outl(phys_to_bus((int)tx_buffer), ioaddr + RTL_REG_TXADDR0 + cur_tx*4);
449 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
450 ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4);
453 status = inw(ioaddr + RTL_REG_INTRSTATUS);
455 * Only acknlowledge interrupt sources we can properly
456 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
457 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
458 * rtl_poll() function.
460 outw(status & (RTL_REG_INTRSTATUS_TXOK |
461 RTL_REG_INTRSTATUS_TXERR |
462 RTL_REG_INTRSTATUS_PCIERR),
463 ioaddr + RTL_REG_INTRSTATUS);
464 if ((status & (RTL_REG_INTRSTATUS_TXOK |
465 RTL_REG_INTRSTATUS_TXERR |
466 RTL_REG_INTRSTATUS_PCIERR)) != 0)
469 } while (i++ < RTL_TIMEOUT);
471 txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4);
473 if (status & RTL_REG_INTRSTATUS_TXOK) {
474 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
477 "tx done, status %hX txstatus %lX\n",
484 "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
485 10*i, status, txstatus);
493 static int rtl_poll(struct eth_device *dev)
496 unsigned int ring_offs;
497 unsigned int rx_size, rx_status;
500 ioaddr = dev->iobase;
502 if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY) {
506 status = inw(ioaddr + RTL_REG_INTRSTATUS);
507 /* See below for the rest of the interrupt acknowledges. */
508 outw(status & ~(RTL_REG_INTRSTATUS_RXFIFOOVER |
509 RTL_REG_INTRSTATUS_RXOVERFLOW |
510 RTL_REG_INTRSTATUS_RXOK),
511 ioaddr + RTL_REG_INTRSTATUS);
513 debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
515 ring_offs = cur_rx % RX_BUF_LEN;
516 /* ring_offs is guaranteed being 4-byte aligned */
517 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
518 rx_size = rx_status >> 16;
521 if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
522 RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
523 RTL_STS_RXBADALIGN)) ||
524 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
525 printf("rx error %hX\n", rx_status);
526 rtl_reset(dev); /* this clears all interrupts still pending */
530 /* Received a good packet */
531 length = rx_size - 4; /* no one cares about the FCS */
532 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
533 int semi_count = RX_BUF_LEN - ring_offs - 4;
534 unsigned char rxdata[RX_BUF_LEN];
536 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
537 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
539 net_process_received_packet(rxdata, length);
540 debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
541 semi_count, rx_size-4-semi_count);
543 net_process_received_packet(rx_ring + ring_offs + 4, length);
544 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
546 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
548 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
549 outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
550 /* See RTL8139 Programming Guide V0.1 for the official handling of
551 * Rx overflow situations. The document itself contains basically no
552 * usable information, except for a few exception handling rules. */
553 outw(status & (RTL_REG_INTRSTATUS_RXFIFOOVER |
554 RTL_REG_INTRSTATUS_RXOVERFLOW |
555 RTL_REG_INTRSTATUS_RXOK), ioaddr + RTL_REG_INTRSTATUS);
559 static void rtl_disable(struct eth_device *dev)
563 ioaddr = dev->iobase;
566 outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
568 /* Give the chip 10ms to finish the reset. */
569 for (i=0; i<100; ++i){
570 if ((inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_CMDRESET) == 0) break;
571 udelay (100); /* wait 100us */