1 // SPDX-License-Identifier: GPL-2.0
3 * rtl8139.c : U-Boot driver for the RealTek RTL8139
5 * Masami Komiya (mkomiya@sonare.it)
7 * Most part is taken from rtl8139.c of etherboot
11 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
13 * ported from the linux driver written by Donald Becker
14 * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
16 * changes to the original driver:
17 * - removed support for interrupts, switching to polling mode (yuck!)
18 * - removed support for the 8129 chip (external MII)
21 /*********************************************************************/
22 /* Revision History */
23 /*********************************************************************/
26 * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
27 * Put in virt_to_bus calls to allow Etherboot relocation.
29 * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
30 * Following email from Hyun-Joon Cha, added a disable routine, otherwise
31 * NIC remains live and can crash the kernel later.
33 * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
34 * Shuffled things around, removed the leftovers from the 8129 support
35 * that was in the Linux driver and added a bit more 8139 definitions.
36 * Moved the 8K receive buffer to a fixed, available address outside the
37 * 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
38 * way to make room for the Etherboot features that need substantial amounts
39 * of code like the ANSI console support. Currently the buffer is just below
40 * 0x10000, so this even conforms to the tagged boot image specification,
41 * which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
42 * interpretation of this "reserved" is that Etherboot may do whatever it
43 * likes, as long as its environment is kept intact (like the BIOS
44 * variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
45 * were that if Etherboot was left at the boot menu for several minutes, the
46 * first eth_poll failed. Seems like I am the only person who does this.
47 * First of all I fixed the debugging code and then set out for a long bug
48 * hunting session. It took me about a week full time work - poking around
49 * various places in the driver, reading Don Becker's and Jeff Garzik's Linux
50 * driver and even the FreeBSD driver (what a piece of crap!) - and
51 * eventually spotted the nasty thing: the transmit routine was acknowledging
52 * each and every interrupt pending, including the RxOverrun and RxFIFIOver
53 * interrupts. This confused the RTL8139 thoroughly. It destroyed the
54 * Rx ring contents by dumping the 2K FIFO contents right where we wanted to
55 * get the next packet. Oh well, what fun.
57 * 18 Jan 2000 mdc@thinguin.org (Marty Connor)
58 * Drastically simplified error handling. Basically, if any error
59 * in transmission or reception occurs, the card is reset.
60 * Also, pointed all transmit descriptors to the same buffer to
61 * save buffer space. This should decrease driver size and avoid
62 * corruption because of exceeding 32K during runtime.
64 * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
65 * rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
66 * of the RxBufferEmpty flag which often resulted in very bad
67 * transmission performace - below 1kBytes/s.
80 #include <linux/bitops.h>
81 #include <linux/delay.h>
82 #include <linux/types.h>
84 #define RTL_TIMEOUT 100000
86 /* PCI Tuning Parameters */
87 /* Threshold is bytes transferred to chip before transmission starts. */
88 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
89 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
90 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
91 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
92 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
93 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
94 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
95 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
97 #define DEBUG_TX 0 /* set to 1 to enable debug code */
98 #define DEBUG_RX 0 /* set to 1 to enable debug code */
100 #define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a))
101 #define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a))
103 /* Symbolic offsets to registers. */
104 /* Ethernet hardware address. */
105 #define RTL_REG_MAC0 0x00
106 /* Multicast filter. */
107 #define RTL_REG_MAR0 0x08
108 /* Transmit status (four 32bit registers). */
109 #define RTL_REG_TXSTATUS0 0x10
110 /* Tx descriptors (also four 32bit). */
111 #define RTL_REG_TXADDR0 0x20
112 #define RTL_REG_RXBUF 0x30
113 #define RTL_REG_RXEARLYCNT 0x34
114 #define RTL_REG_RXEARLYSTATUS 0x36
115 #define RTL_REG_CHIPCMD 0x37
116 #define RTL_REG_CHIPCMD_CMDRESET BIT(4)
117 #define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
118 #define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
119 #define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
120 #define RTL_REG_RXBUFPTR 0x38
121 #define RTL_REG_RXBUFADDR 0x3A
122 #define RTL_REG_INTRMASK 0x3C
123 #define RTL_REG_INTRSTATUS 0x3E
124 #define RTL_REG_INTRSTATUS_PCIERR BIT(15)
125 #define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
126 #define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
127 #define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
128 #define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
129 #define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
130 #define RTL_REG_INTRSTATUS_TXERR BIT(3)
131 #define RTL_REG_INTRSTATUS_TXOK BIT(2)
132 #define RTL_REG_INTRSTATUS_RXERR BIT(1)
133 #define RTL_REG_INTRSTATUS_RXOK BIT(0)
134 #define RTL_REG_TXCONFIG 0x40
135 #define RTL_REG_RXCONFIG 0x44
136 #define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
137 #define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
138 #define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
139 #define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
140 #define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
141 #define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
142 #define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
143 /* general-purpose counter. */
144 #define RTL_REG_TIMER 0x48
145 /* 24 bits valid, write clears. */
146 #define RTL_REG_RXMISSED 0x4C
147 #define RTL_REG_CFG9346 0x50
148 #define RTL_REG_CONFIG0 0x51
149 #define RTL_REG_CONFIG1 0x52
150 /* intr if gp counter reaches this value */
151 #define RTL_REG_TIMERINTRREG 0x54
152 #define RTL_REG_MEDIASTATUS 0x58
153 #define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
154 #define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
155 #define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
156 #define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
157 #define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
158 #define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
159 #define RTL_REG_CONFIG3 0x59
160 #define RTL_REG_MULTIINTR 0x5C
161 /* revision of the RTL8139 chip */
162 #define RTL_REG_REVISIONID 0x5E
163 #define RTL_REG_TXSUMMARY 0x60
164 #define RTL_REG_MII_BMCR 0x62
165 #define RTL_REG_MII_BMSR 0x64
166 #define RTL_REG_NWAYADVERT 0x66
167 #define RTL_REG_NWAYLPAR 0x68
168 #define RTL_REG_NWAYEXPANSION 0x6A
169 #define RTL_REG_DISCONNECTCNT 0x6C
170 #define RTL_REG_FALSECARRIERCNT 0x6E
171 #define RTL_REG_NWAYTESTREG 0x70
172 /* packet received counter */
173 #define RTL_REG_RXCNT 0x72
174 /* chip status and configuration register */
175 #define RTL_REG_CSCR 0x74
176 #define RTL_REG_PHYPARM1 0x78
177 #define RTL_REG_TWISTERPARM 0x7c
179 #define RTL_REG_PHYPARM2 0x80
181 * from 0x84 onwards are a number of power management/wakeup frame
182 * definitions we will probably never need to know about.
185 #define RTL_STS_RXMULTICAST BIT(15)
186 #define RTL_STS_RXPHYSICAL BIT(14)
187 #define RTL_STS_RXBROADCAST BIT(13)
188 #define RTL_STS_RXBADSYMBOL BIT(5)
189 #define RTL_STS_RXRUNT BIT(4)
190 #define RTL_STS_RXTOOLONG BIT(3)
191 #define RTL_STS_RXCRCERR BIT(2)
192 #define RTL_STS_RXBADALIGN BIT(1)
193 #define RTL_STS_RXSTATUSOK BIT(0)
195 struct rtl8139_priv {
196 struct udevice *devno;
197 unsigned int rxstatus;
200 unsigned long ioaddr;
201 unsigned char enetaddr[6];
204 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
205 static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
206 static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4);
208 /* Serial EEPROM section. */
210 /* EEPROM_Ctrl bits. */
211 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
212 #define EE_CS 0x08 /* EEPROM chip select. */
213 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
214 #define EE_WRITE_0 0x00
215 #define EE_WRITE_1 0x02
216 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
217 #define EE_ENB (0x80 | EE_CS)
219 /* The EEPROM commands include the alway-set leading bit. */
220 #define EE_WRITE_CMD 5
221 #define EE_READ_CMD 6
222 #define EE_ERASE_CMD 7
224 static void rtl8139_eeprom_delay(struct rtl8139_priv *priv)
227 * Delay between EEPROM clock transitions.
228 * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
230 inl(priv->ioaddr + RTL_REG_CFG9346);
233 static int rtl8139_read_eeprom(struct rtl8139_priv *priv,
234 unsigned int location, unsigned int addr_len)
236 unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
237 uintptr_t ee_addr = priv->ioaddr + RTL_REG_CFG9346;
238 unsigned int retval = 0;
242 outb(EE_ENB & ~EE_CS, ee_addr);
243 outb(EE_ENB, ee_addr);
244 rtl8139_eeprom_delay(priv);
246 /* Shift the read command bits out. */
247 for (i = 4 + addr_len; i >= 0; i--) {
248 dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
249 outb(EE_ENB | dataval, ee_addr);
250 rtl8139_eeprom_delay(priv);
251 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
252 rtl8139_eeprom_delay(priv);
255 outb(EE_ENB, ee_addr);
256 rtl8139_eeprom_delay(priv);
258 for (i = 16; i > 0; i--) {
259 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
260 rtl8139_eeprom_delay(priv);
262 retval |= inb(ee_addr) & EE_DATA_READ;
263 outb(EE_ENB, ee_addr);
264 rtl8139_eeprom_delay(priv);
267 /* Terminate the EEPROM access. */
268 outb(~EE_CS, ee_addr);
269 rtl8139_eeprom_delay(priv);
274 static const unsigned int rtl8139_rx_config =
275 (RX_BUF_LEN_IDX << 11) |
276 (RX_FIFO_THRESH << 13) |
279 static void rtl8139_set_rx_mode(struct rtl8139_priv *priv)
282 unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
283 RTL_REG_RXCONFIG_ACCEPTMULTICAST |
284 RTL_REG_RXCONFIG_ACCEPTMYPHYS;
286 outl(rtl8139_rx_config | rx_mode, priv->ioaddr + RTL_REG_RXCONFIG);
288 outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 0);
289 outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 4);
292 static void rtl8139_hw_reset(struct rtl8139_priv *priv)
297 outb(RTL_REG_CHIPCMD_CMDRESET, priv->ioaddr + RTL_REG_CHIPCMD);
299 /* Give the chip 10ms to finish the reset. */
300 for (i = 0; i < 100; i++) {
301 reg = inb(priv->ioaddr + RTL_REG_CHIPCMD);
302 if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
309 static void rtl8139_reset(struct rtl8139_priv *priv)
316 rtl8139_hw_reset(priv);
318 for (i = 0; i < ETH_ALEN; i++)
319 outb(priv->enetaddr[i], priv->ioaddr + RTL_REG_MAC0 + i);
321 /* Must enable Tx/Rx before setting transfer thresholds! */
322 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
323 priv->ioaddr + RTL_REG_CHIPCMD);
325 /* accept no frames yet! */
326 outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
327 outl((TX_DMA_BURST << 8) | 0x03000000, priv->ioaddr + RTL_REG_TXCONFIG);
330 * The Linux driver changes RTL_REG_CONFIG1 here to use a different
331 * LED pattern for half duplex or full/autodetect duplex (for
332 * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
333 * for half duplex it uses TX/RX, Link100, Link10). This is messy,
334 * because it doesn't match the inscription on the mounting bracket.
335 * It should not be changed from the configuration EEPROM default,
336 * because the card manufacturer should have set that to match the
339 debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
341 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
342 outl(phys_to_bus(priv->devno, (int)rx_ring), priv->ioaddr + RTL_REG_RXBUF);
345 * If we add multicast support, the RTL_REG_MAR0 register would have
346 * to be initialized to 0xffffffffffffffff (two 32 bit accesses).
347 * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
350 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
351 priv->ioaddr + RTL_REG_CHIPCMD);
353 outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG);
355 /* Start the chip's Tx and Rx process. */
356 outl(0, priv->ioaddr + RTL_REG_RXMISSED);
358 rtl8139_set_rx_mode(priv);
360 /* Disable all known interrupts by setting the interrupt mask. */
361 outw(0, priv->ioaddr + RTL_REG_INTRMASK);
364 static int rtl8139_send_common(struct rtl8139_priv *priv,
365 void *packet, int length)
367 unsigned int len = length;
368 unsigned long txstatus;
372 memcpy(tx_buffer, packet, length);
374 debug_cond(DEBUG_TX, "sending %d bytes\n", len);
377 * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
378 * bytes are sent automatically for the FCS, totalling to 64 bytes).
380 while (len < ETH_ZLEN)
381 tx_buffer[len++] = '\0';
383 flush_cache((unsigned long)tx_buffer, length);
384 outl(phys_to_bus(priv->devno, (unsigned long)tx_buffer),
385 priv->ioaddr + RTL_REG_TXADDR0 + priv->cur_tx * 4);
386 outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
387 priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
390 status = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
392 * Only acknlowledge interrupt sources we can properly
393 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
394 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
395 * rtl8139_recv() function.
397 status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
398 RTL_REG_INTRSTATUS_PCIERR;
399 outw(status, priv->ioaddr + RTL_REG_INTRSTATUS);
404 } while (i++ < RTL_TIMEOUT);
406 txstatus = inl(priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4);
408 if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
410 "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
411 10 * i, status, txstatus);
418 priv->cur_tx = (priv->cur_tx + 1) % NUM_TX_DESC;
420 debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
426 static int rtl8139_recv_common(struct rtl8139_priv *priv, unsigned char *rxdata,
429 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
430 RTL_REG_INTRSTATUS_RXOVERFLOW |
431 RTL_REG_INTRSTATUS_RXOK;
432 unsigned int rx_size, rx_status;
433 unsigned int ring_offs;
436 if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
439 priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS);
440 /* See below for the rest of the interrupt acknowledges. */
441 outw(priv->rxstatus & ~rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
443 debug_cond(DEBUG_RX, "%s: int %hX ", __func__, priv->rxstatus);
445 ring_offs = priv->cur_rx % RX_BUF_LEN;
446 /* ring_offs is guaranteed being 4-byte aligned */
447 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
448 rx_size = rx_status >> 16;
451 if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
452 RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
453 RTL_STS_RXBADALIGN)) ||
454 (rx_size < ETH_ZLEN) ||
455 (rx_size > ETH_FRAME_LEN + 4)) {
456 printf("rx error %hX\n", rx_status);
457 /* this clears all interrupts still pending */
462 /* Received a good packet */
463 length = rx_size - 4; /* no one cares about the FCS */
464 if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
465 int semi_count = RX_BUF_LEN - ring_offs - 4;
467 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
468 memcpy(&rxdata[semi_count], rx_ring,
469 rx_size - 4 - semi_count);
472 debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
473 semi_count, rx_size - 4 - semi_count);
475 *packetp = rx_ring + ring_offs + 4;
476 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
482 static int rtl8139_free_pkt_common(struct rtl8139_priv *priv, unsigned int len)
484 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
485 RTL_REG_INTRSTATUS_RXOVERFLOW |
486 RTL_REG_INTRSTATUS_RXOK;
487 unsigned int rx_size = len + 4;
489 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
491 priv->cur_rx = ROUND(priv->cur_rx + rx_size + 4, 4);
492 outw(priv->cur_rx - 16, priv->ioaddr + RTL_REG_RXBUFPTR);
494 * See RTL8139 Programming Guide V0.1 for the official handling of
495 * Rx overflow situations. The document itself contains basically
496 * no usable information, except for a few exception handling rules.
498 outw(priv->rxstatus & rxstat, priv->ioaddr + RTL_REG_INTRSTATUS);
503 static int rtl8139_init_common(struct rtl8139_priv *priv)
507 /* Bring the chip out of low-power mode. */
508 outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
512 reg = inb(priv->ioaddr + RTL_REG_MEDIASTATUS);
513 if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
514 printf("Cable not connected or other link failure\n");
521 static void rtl8139_stop_common(struct rtl8139_priv *priv)
523 rtl8139_hw_reset(priv);
526 static void rtl8139_get_hwaddr(struct rtl8139_priv *priv)
528 unsigned short *ap = (unsigned short *)priv->enetaddr;
531 /* Bring the chip out of low-power mode. */
532 outb(0x00, priv->ioaddr + RTL_REG_CONFIG1);
534 addr_len = rtl8139_read_eeprom(priv, 0, 8) == 0x8129 ? 8 : 6;
535 for (i = 0; i < 3; i++)
536 *ap++ = le16_to_cpu(rtl8139_read_eeprom(priv, i + 7, addr_len));
539 static void rtl8139_name(char *str, int card_number)
541 sprintf(str, "RTL8139#%u", card_number);
544 static struct pci_device_id supported[] = {
545 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139) },
546 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139) },
550 static int rtl8139_start(struct udevice *dev)
552 struct eth_pdata *plat = dev_get_plat(dev);
553 struct rtl8139_priv *priv = dev_get_priv(dev);
555 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
557 return rtl8139_init_common(priv);
560 static void rtl8139_stop(struct udevice *dev)
562 struct rtl8139_priv *priv = dev_get_priv(dev);
564 rtl8139_stop_common(priv);
567 static int rtl8139_send(struct udevice *dev, void *packet, int length)
569 struct rtl8139_priv *priv = dev_get_priv(dev);
572 ret = rtl8139_send_common(priv, packet, length);
574 return ret ? 0 : -ETIMEDOUT;
577 static int rtl8139_recv(struct udevice *dev, int flags, uchar **packetp)
579 struct rtl8139_priv *priv = dev_get_priv(dev);
580 static unsigned char rxdata[RX_BUF_LEN];
582 return rtl8139_recv_common(priv, rxdata, packetp);
585 static int rtl8139_free_pkt(struct udevice *dev, uchar *packet, int length)
587 struct rtl8139_priv *priv = dev_get_priv(dev);
589 rtl8139_free_pkt_common(priv, length);
594 static int rtl8139_write_hwaddr(struct udevice *dev)
596 struct eth_pdata *plat = dev_get_plat(dev);
597 struct rtl8139_priv *priv = dev_get_priv(dev);
599 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr));
606 static int rtl8139_read_rom_hwaddr(struct udevice *dev)
608 struct rtl8139_priv *priv = dev_get_priv(dev);
610 rtl8139_get_hwaddr(priv);
615 static int rtl8139_bind(struct udevice *dev)
617 static int card_number;
620 rtl8139_name(name, card_number++);
622 return device_set_name(dev, name);
625 static int rtl8139_probe(struct udevice *dev)
627 struct eth_pdata *plat = dev_get_plat(dev);
628 struct rtl8139_priv *priv = dev_get_priv(dev);
631 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
634 debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
637 priv->ioaddr = (unsigned long)bus_to_phys(dev, iobase);
639 rtl8139_get_hwaddr(priv);
640 memcpy(plat->enetaddr, priv->enetaddr, sizeof(priv->enetaddr));
642 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20);
647 static const struct eth_ops rtl8139_ops = {
648 .start = rtl8139_start,
649 .send = rtl8139_send,
650 .recv = rtl8139_recv,
651 .stop = rtl8139_stop,
652 .free_pkt = rtl8139_free_pkt,
653 .write_hwaddr = rtl8139_write_hwaddr,
654 .read_rom_hwaddr = rtl8139_read_rom_hwaddr,
657 U_BOOT_DRIVER(eth_rtl8139) = {
658 .name = "eth_rtl8139",
660 .bind = rtl8139_bind,
661 .probe = rtl8139_probe,
663 .priv_auto = sizeof(struct rtl8139_priv),
664 .plat_auto = sizeof(struct eth_pdata),
667 U_BOOT_PCI_DEVICE(eth_rtl8139, supported);