2 * rtl8139.c : U-Boot driver for the RealTek RTL8139
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from rtl8139.c of etherboot
10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
12 ported from the linux driver written by Donald Becker
13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
15 This software may be used and distributed according to the terms
16 of the GNU Public License, incorporated herein by reference.
18 changes to the original driver:
19 - removed support for interrupts, switching to polling mode (yuck!)
20 - removed support for the 8129 chip (external MII)
24 /*********************************************************************/
25 /* Revision History */
26 /*********************************************************************/
29 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
30 Put in virt_to_bus calls to allow Etherboot relocation.
32 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
33 Following email from Hyun-Joon Cha, added a disable routine, otherwise
34 NIC remains live and can crash the kernel later.
36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
37 Shuffled things around, removed the leftovers from the 8129 support
38 that was in the Linux driver and added a bit more 8139 definitions.
39 Moved the 8K receive buffer to a fixed, available address outside the
40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
41 way to make room for the Etherboot features that need substantial amounts
42 of code like the ANSI console support. Currently the buffer is just below
43 0x10000, so this even conforms to the tagged boot image specification,
44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
45 interpretation of this "reserved" is that Etherboot may do whatever it
46 likes, as long as its environment is kept intact (like the BIOS
47 variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
48 were that if Etherboot was left at the boot menu for several minutes, the
49 first eth_poll failed. Seems like I am the only person who does this.
50 First of all I fixed the debugging code and then set out for a long bug
51 hunting session. It took me about a week full time work - poking around
52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux
53 driver and even the FreeBSD driver (what a piece of crap!) - and
54 eventually spotted the nasty thing: the transmit routine was acknowledging
55 each and every interrupt pending, including the RxOverrun and RxFIFIOver
56 interrupts. This confused the RTL8139 thoroughly. It destroyed the
57 Rx ring contents by dumping the 2K FIFO contents right where we wanted to
58 get the next packet. Oh well, what fun.
60 18 Jan 2000 mdc@thinguin.org (Marty Connor)
61 Drastically simplified error handling. Basically, if any error
62 in transmission or reception occurs, the card is reset.
63 Also, pointed all transmit descriptors to the same buffer to
64 save buffer space. This should decrease driver size and avoid
65 corruption because of exceeding 32K during runtime.
67 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
68 rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
69 of the RxBufferEmpty flag which often resulted in very bad
70 transmission performace - below 1kBytes/s.
76 #include <linux/types.h>
83 #define RTL_TIMEOUT 100000
85 /* PCI Tuning Parameters
86 Threshold is bytes transferred to chip before transmission starts. */
87 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
88 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
89 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
90 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
91 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
92 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
93 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
94 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
96 #define DEBUG_TX 0 /* set to 1 to enable debug code */
97 #define DEBUG_RX 0 /* set to 1 to enable debug code */
99 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
100 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
102 /* Symbolic offsets to registers. */
103 /* Ethernet hardware address. */
104 #define RTL_REG_MAC0 0x00
105 /* Multicast filter. */
106 #define RTL_REG_MAR0 0x08
107 /* Transmit status (four 32bit registers). */
108 #define RTL_REG_TXSTATUS0 0x10
109 /* Tx descriptors (also four 32bit). */
110 #define RTL_REG_TXADDR0 0x20
111 #define RTL_REG_RXBUF 0x30
112 #define RTL_REG_RXEARLYCNT 0x34
113 #define RTL_REG_RXEARLYSTATUS 0x36
114 #define RTL_REG_CHIPCMD 0x37
115 #define RTL_REG_CHIPCMD_CMDRESET BIT(4)
116 #define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
117 #define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
118 #define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
119 #define RTL_REG_RXBUFPTR 0x38
120 #define RTL_REG_RXBUFADDR 0x3A
121 #define RTL_REG_INTRMASK 0x3C
122 #define RTL_REG_INTRSTATUS 0x3E
123 #define RTL_REG_INTRSTATUS_PCIERR BIT(15)
124 #define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
125 #define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
126 #define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
127 #define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
128 #define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
129 #define RTL_REG_INTRSTATUS_TXERR BIT(3)
130 #define RTL_REG_INTRSTATUS_TXOK BIT(2)
131 #define RTL_REG_INTRSTATUS_RXERR BIT(1)
132 #define RTL_REG_INTRSTATUS_RXOK BIT(0)
133 #define RTL_REG_TXCONFIG 0x40
134 #define RTL_REG_RXCONFIG 0x44
135 #define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
136 #define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
137 #define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
138 #define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
139 #define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
140 #define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
141 #define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
142 /* general-purpose counter. */
143 #define RTL_REG_TIMER 0x48
144 /* 24 bits valid, write clears. */
145 #define RTL_REG_RXMISSED 0x4C
146 #define RTL_REG_CFG9346 0x50
147 #define RTL_REG_CONFIG0 0x51
148 #define RTL_REG_CONFIG1 0x52
149 /* intr if gp counter reaches this value */
150 #define RTL_REG_TIMERINTRREG 0x54
151 #define RTL_REG_MEDIASTATUS 0x58
152 #define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
153 #define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
154 #define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
155 #define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
156 #define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
157 #define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
158 #define RTL_REG_CONFIG3 0x59
159 #define RTL_REG_MULTIINTR 0x5C
160 /* revision of the RTL8139 chip */
161 #define RTL_REG_REVISIONID 0x5E
162 #define RTL_REG_TXSUMMARY 0x60
163 #define RTL_REG_MII_BMCR 0x62
164 #define RTL_REG_MII_BMSR 0x64
165 #define RTL_REG_NWAYADVERT 0x66
166 #define RTL_REG_NWAYLPAR 0x68
167 #define RTL_REG_NWAYEXPANSION 0x6A
168 #define RTL_REG_DISCONNECTCNT 0x6C
169 #define RTL_REG_FALSECARRIERCNT 0x6E
170 #define RTL_REG_NWAYTESTREG 0x70
171 /* packet received counter */
172 #define RTL_REG_RXCNT 0x72
173 /* chip status and configuration register */
174 #define RTL_REG_CSCR 0x74
175 #define RTL_REG_PHYPARM1 0x78
176 #define RTL_REG_TWISTERPARM 0x7c
178 #define RTL_REG_PHYPARM2 0x80
180 * from 0x84 onwards are a number of power management/wakeup frame
181 * definitions we will probably never need to know about.
184 #define RTL_STS_RXMULTICAST BIT(15)
185 #define RTL_STS_RXPHYSICAL BIT(14)
186 #define RTL_STS_RXBROADCAST BIT(13)
187 #define RTL_STS_RXBADSYMBOL BIT(5)
188 #define RTL_STS_RXRUNT BIT(4)
189 #define RTL_STS_RXTOOLONG BIT(3)
190 #define RTL_STS_RXCRCERR BIT(2)
191 #define RTL_STS_RXBADALIGN BIT(1)
192 #define RTL_STS_RXSTATUSOK BIT(0)
195 static unsigned int cur_rx,cur_tx;
197 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
198 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
199 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
201 static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
202 static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len);
203 static void rtl8139_reset(struct eth_device *dev);
204 static int rtl8139_send(struct eth_device *dev, void *packet, int length);
205 static int rtl8139_recv(struct eth_device *dev);
206 static void rtl_disable(struct eth_device *dev);
207 static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
212 static struct pci_device_id supported[] = {
213 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
214 {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
218 int rtl8139_initialize(bd_t *bis)
222 struct eth_device *dev;
228 if ((devno = pci_find_devices(supported, idx++)) < 0)
231 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
234 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
236 dev = (struct eth_device *)malloc(sizeof *dev);
238 printf("Can not allocate memory of rtl8139\n");
241 memset(dev, 0, sizeof(*dev));
243 sprintf (dev->name, "RTL8139#%d", card_number);
245 dev->priv = (void *) devno;
246 dev->iobase = (int)bus_to_phys(iobase);
247 dev->init = rtl8139_probe;
248 dev->halt = rtl_disable;
249 dev->send = rtl8139_send;
250 dev->recv = rtl8139_recv;
251 dev->mcast = rtl_bcast_addr;
257 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
265 static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
269 unsigned short *ap = (unsigned short *)dev->enetaddr;
271 ioaddr = dev->iobase;
273 /* Bring the chip out of low-power mode. */
274 outb(0x00, ioaddr + RTL_REG_CONFIG1);
276 addr_len = rtl8139_read_eeprom(0,8) == 0x8129 ? 8 : 6;
277 for (i = 0; i < 3; i++)
278 *ap++ = le16_to_cpu (rtl8139_read_eeprom(i + 7, addr_len));
282 if (inb(ioaddr + RTL_REG_MEDIASTATUS) & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
283 printf("Cable not connected or other link failure\n");
290 /* Serial EEPROM section. */
292 /* EEPROM_Ctrl bits. */
293 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
294 #define EE_CS 0x08 /* EEPROM chip select. */
295 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
296 #define EE_WRITE_0 0x00
297 #define EE_WRITE_1 0x02
298 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
299 #define EE_ENB (0x80 | EE_CS)
301 /* The EEPROM commands include the alway-set leading bit. */
302 #define EE_WRITE_CMD 5
303 #define EE_READ_CMD 6
304 #define EE_ERASE_CMD 7
306 static void rtl8139_eeprom_delay(uintptr_t regbase)
309 * Delay between EEPROM clock transitions.
310 * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
312 inl(regbase + RTL_REG_CFG9346);
315 static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len)
317 unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
318 uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346;
319 unsigned int retval = 0;
323 outb(EE_ENB & ~EE_CS, ee_addr);
324 outb(EE_ENB, ee_addr);
325 rtl8139_eeprom_delay(ioaddr);
327 /* Shift the read command bits out. */
328 for (i = 4 + addr_len; i >= 0; i--) {
329 dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
330 outb(EE_ENB | dataval, ee_addr);
331 rtl8139_eeprom_delay(ioaddr);
332 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
333 rtl8139_eeprom_delay(ioaddr);
336 outb(EE_ENB, ee_addr);
337 rtl8139_eeprom_delay(ioaddr);
339 for (i = 16; i > 0; i--) {
340 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
341 rtl8139_eeprom_delay(ioaddr);
343 retval |= inb(ee_addr) & EE_DATA_READ;
344 outb(EE_ENB, ee_addr);
345 rtl8139_eeprom_delay(ioaddr);
348 /* Terminate the EEPROM access. */
349 outb(~EE_CS, ee_addr);
350 rtl8139_eeprom_delay(ioaddr);
355 static const unsigned int rtl8139_rx_config =
356 (RX_BUF_LEN_IDX << 11) |
357 (RX_FIFO_THRESH << 13) |
360 static void rtl8139_set_rx_mode(struct eth_device *dev)
363 unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
364 RTL_REG_RXCONFIG_ACCEPTMULTICAST |
365 RTL_REG_RXCONFIG_ACCEPTMYPHYS;
367 outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
369 outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0);
370 outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4);
373 static void rtl8139_reset(struct eth_device *dev)
378 outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
383 /* Give the chip 10ms to finish the reset. */
384 for (i = 0; i < 100; i++) {
385 reg = inb(ioaddr + RTL_REG_CHIPCMD);
386 if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
393 for (i = 0; i < ETH_ALEN; i++)
394 outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
396 /* Must enable Tx/Rx before setting transfer thresholds! */
397 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
398 ioaddr + RTL_REG_CHIPCMD);
400 /* accept no frames yet! */
401 outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
402 outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG);
405 * The Linux driver changes RTL_REG_CONFIG1 here to use a different
406 * LED pattern for half duplex or full/autodetect duplex (for
407 * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
408 * for half duplex it uses TX/RX, Link100, Link10). This is messy,
409 * because it doesn't match the inscription on the mounting bracket.
410 * It should not be changed from the configuration EEPROM default,
411 * because the card manufacturer should have set that to match the
414 debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
416 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
417 outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
420 * If we add multicast support, the RTL_REG_MAR0 register would have
421 * to be initialized to 0xffffffffffffffff (two 32 bit accesses).
422 * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
425 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
426 ioaddr + RTL_REG_CHIPCMD);
428 outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
430 /* Start the chip's Tx and Rx process. */
431 outl(0, ioaddr + RTL_REG_RXMISSED);
433 rtl8139_set_rx_mode(dev);
435 /* Disable all known interrupts by setting the interrupt mask. */
436 outw(0, ioaddr + RTL_REG_INTRMASK);
439 static int rtl8139_send(struct eth_device *dev, void *packet, int length)
441 unsigned int len = length;
442 unsigned long txstatus;
446 ioaddr = dev->iobase;
448 memcpy(tx_buffer, packet, length);
450 debug_cond(DEBUG_TX, "sending %d bytes\n", len);
453 * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
454 * bytes are sent automatically for the FCS, totalling to 64 bytes).
456 while (len < ETH_ZLEN)
457 tx_buffer[len++] = '\0';
459 flush_cache((unsigned long)tx_buffer, length);
460 outl(phys_to_bus((unsigned long)tx_buffer),
461 ioaddr + RTL_REG_TXADDR0 + cur_tx * 4);
462 outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
463 ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
466 status = inw(ioaddr + RTL_REG_INTRSTATUS);
468 * Only acknlowledge interrupt sources we can properly
469 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
470 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
471 * rtl8139_recv() function.
473 status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
474 RTL_REG_INTRSTATUS_PCIERR;
475 outw(status, ioaddr + RTL_REG_INTRSTATUS);
480 } while (i++ < RTL_TIMEOUT);
482 txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
484 if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
486 "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
487 10 * i, status, txstatus);
494 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
496 debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
502 static int rtl8139_recv(struct eth_device *dev)
504 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
505 RTL_REG_INTRSTATUS_RXOVERFLOW |
506 RTL_REG_INTRSTATUS_RXOK;
507 unsigned int rx_size, rx_status;
508 unsigned int ring_offs;
512 ioaddr = dev->iobase;
514 if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
517 status = inw(ioaddr + RTL_REG_INTRSTATUS);
518 /* See below for the rest of the interrupt acknowledges. */
519 outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS);
521 debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status);
523 ring_offs = cur_rx % RX_BUF_LEN;
524 /* ring_offs is guaranteed being 4-byte aligned */
525 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
526 rx_size = rx_status >> 16;
529 if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
530 RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
531 RTL_STS_RXBADALIGN)) ||
532 (rx_size < ETH_ZLEN) ||
533 (rx_size > ETH_FRAME_LEN + 4)) {
534 printf("rx error %hX\n", rx_status);
535 /* this clears all interrupts still pending */
540 /* Received a good packet */
541 length = rx_size - 4; /* no one cares about the FCS */
542 if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
543 unsigned char rxdata[RX_BUF_LEN];
544 int semi_count = RX_BUF_LEN - ring_offs - 4;
546 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
547 memcpy(&rxdata[semi_count], rx_ring,
548 rx_size - 4 - semi_count);
550 net_process_received_packet(rxdata, length);
551 debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
552 semi_count, rx_size - 4 - semi_count);
554 net_process_received_packet(rx_ring + ring_offs + 4, length);
555 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
557 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
559 cur_rx = ROUND(cur_rx + rx_size + 4, 4);
560 outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
562 * See RTL8139 Programming Guide V0.1 for the official handling of
563 * Rx overflow situations. The document itself contains basically
564 * no usable information, except for a few exception handling rules.
566 outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS);
571 static void rtl_disable(struct eth_device *dev)
575 ioaddr = dev->iobase;
578 outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
580 /* Give the chip 10ms to finish the reset. */
581 for (i=0; i<100; ++i){
582 if ((inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_CMDRESET) == 0) break;
583 udelay (100); /* wait 100us */