1 // SPDX-License-Identifier: GPL-2.0
3 * rtl8139.c : U-Boot driver for the RealTek RTL8139
5 * Masami Komiya (mkomiya@sonare.it)
7 * Most part is taken from rtl8139.c of etherboot
11 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
13 * ported from the linux driver written by Donald Becker
14 * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
16 * changes to the original driver:
17 * - removed support for interrupts, switching to polling mode (yuck!)
18 * - removed support for the 8129 chip (external MII)
21 /*********************************************************************/
22 /* Revision History */
23 /*********************************************************************/
26 * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
27 * Put in virt_to_bus calls to allow Etherboot relocation.
29 * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
30 * Following email from Hyun-Joon Cha, added a disable routine, otherwise
31 * NIC remains live and can crash the kernel later.
33 * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
34 * Shuffled things around, removed the leftovers from the 8129 support
35 * that was in the Linux driver and added a bit more 8139 definitions.
36 * Moved the 8K receive buffer to a fixed, available address outside the
37 * 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
38 * way to make room for the Etherboot features that need substantial amounts
39 * of code like the ANSI console support. Currently the buffer is just below
40 * 0x10000, so this even conforms to the tagged boot image specification,
41 * which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
42 * interpretation of this "reserved" is that Etherboot may do whatever it
43 * likes, as long as its environment is kept intact (like the BIOS
44 * variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
45 * were that if Etherboot was left at the boot menu for several minutes, the
46 * first eth_poll failed. Seems like I am the only person who does this.
47 * First of all I fixed the debugging code and then set out for a long bug
48 * hunting session. It took me about a week full time work - poking around
49 * various places in the driver, reading Don Becker's and Jeff Garzik's Linux
50 * driver and even the FreeBSD driver (what a piece of crap!) - and
51 * eventually spotted the nasty thing: the transmit routine was acknowledging
52 * each and every interrupt pending, including the RxOverrun and RxFIFIOver
53 * interrupts. This confused the RTL8139 thoroughly. It destroyed the
54 * Rx ring contents by dumping the 2K FIFO contents right where we wanted to
55 * get the next packet. Oh well, what fun.
57 * 18 Jan 2000 mdc@thinguin.org (Marty Connor)
58 * Drastically simplified error handling. Basically, if any error
59 * in transmission or reception occurs, the card is reset.
60 * Also, pointed all transmit descriptors to the same buffer to
61 * save buffer space. This should decrease driver size and avoid
62 * corruption because of exceeding 32K during runtime.
64 * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
65 * rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
66 * of the RxBufferEmpty flag which often resulted in very bad
67 * transmission performace - below 1kBytes/s.
79 #include <linux/delay.h>
80 #include <linux/types.h>
82 #define RTL_TIMEOUT 100000
84 /* PCI Tuning Parameters */
85 /* Threshold is bytes transferred to chip before transmission starts. */
86 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
87 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
88 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
89 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
90 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
91 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
92 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
93 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
95 #define DEBUG_TX 0 /* set to 1 to enable debug code */
96 #define DEBUG_RX 0 /* set to 1 to enable debug code */
98 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
99 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
101 /* Symbolic offsets to registers. */
102 /* Ethernet hardware address. */
103 #define RTL_REG_MAC0 0x00
104 /* Multicast filter. */
105 #define RTL_REG_MAR0 0x08
106 /* Transmit status (four 32bit registers). */
107 #define RTL_REG_TXSTATUS0 0x10
108 /* Tx descriptors (also four 32bit). */
109 #define RTL_REG_TXADDR0 0x20
110 #define RTL_REG_RXBUF 0x30
111 #define RTL_REG_RXEARLYCNT 0x34
112 #define RTL_REG_RXEARLYSTATUS 0x36
113 #define RTL_REG_CHIPCMD 0x37
114 #define RTL_REG_CHIPCMD_CMDRESET BIT(4)
115 #define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
116 #define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
117 #define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
118 #define RTL_REG_RXBUFPTR 0x38
119 #define RTL_REG_RXBUFADDR 0x3A
120 #define RTL_REG_INTRMASK 0x3C
121 #define RTL_REG_INTRSTATUS 0x3E
122 #define RTL_REG_INTRSTATUS_PCIERR BIT(15)
123 #define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
124 #define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
125 #define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
126 #define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
127 #define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
128 #define RTL_REG_INTRSTATUS_TXERR BIT(3)
129 #define RTL_REG_INTRSTATUS_TXOK BIT(2)
130 #define RTL_REG_INTRSTATUS_RXERR BIT(1)
131 #define RTL_REG_INTRSTATUS_RXOK BIT(0)
132 #define RTL_REG_TXCONFIG 0x40
133 #define RTL_REG_RXCONFIG 0x44
134 #define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
135 #define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
136 #define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
137 #define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
138 #define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
139 #define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
140 #define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
141 /* general-purpose counter. */
142 #define RTL_REG_TIMER 0x48
143 /* 24 bits valid, write clears. */
144 #define RTL_REG_RXMISSED 0x4C
145 #define RTL_REG_CFG9346 0x50
146 #define RTL_REG_CONFIG0 0x51
147 #define RTL_REG_CONFIG1 0x52
148 /* intr if gp counter reaches this value */
149 #define RTL_REG_TIMERINTRREG 0x54
150 #define RTL_REG_MEDIASTATUS 0x58
151 #define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
152 #define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
153 #define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
154 #define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
155 #define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
156 #define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
157 #define RTL_REG_CONFIG3 0x59
158 #define RTL_REG_MULTIINTR 0x5C
159 /* revision of the RTL8139 chip */
160 #define RTL_REG_REVISIONID 0x5E
161 #define RTL_REG_TXSUMMARY 0x60
162 #define RTL_REG_MII_BMCR 0x62
163 #define RTL_REG_MII_BMSR 0x64
164 #define RTL_REG_NWAYADVERT 0x66
165 #define RTL_REG_NWAYLPAR 0x68
166 #define RTL_REG_NWAYEXPANSION 0x6A
167 #define RTL_REG_DISCONNECTCNT 0x6C
168 #define RTL_REG_FALSECARRIERCNT 0x6E
169 #define RTL_REG_NWAYTESTREG 0x70
170 /* packet received counter */
171 #define RTL_REG_RXCNT 0x72
172 /* chip status and configuration register */
173 #define RTL_REG_CSCR 0x74
174 #define RTL_REG_PHYPARM1 0x78
175 #define RTL_REG_TWISTERPARM 0x7c
177 #define RTL_REG_PHYPARM2 0x80
179 * from 0x84 onwards are a number of power management/wakeup frame
180 * definitions we will probably never need to know about.
183 #define RTL_STS_RXMULTICAST BIT(15)
184 #define RTL_STS_RXPHYSICAL BIT(14)
185 #define RTL_STS_RXBROADCAST BIT(13)
186 #define RTL_STS_RXBADSYMBOL BIT(5)
187 #define RTL_STS_RXRUNT BIT(4)
188 #define RTL_STS_RXTOOLONG BIT(3)
189 #define RTL_STS_RXCRCERR BIT(2)
190 #define RTL_STS_RXBADALIGN BIT(1)
191 #define RTL_STS_RXSTATUSOK BIT(0)
193 static unsigned int cur_rx, cur_tx;
196 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
197 static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
198 static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4);
200 /* Serial EEPROM section. */
202 /* EEPROM_Ctrl bits. */
203 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
204 #define EE_CS 0x08 /* EEPROM chip select. */
205 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
206 #define EE_WRITE_0 0x00
207 #define EE_WRITE_1 0x02
208 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
209 #define EE_ENB (0x80 | EE_CS)
211 /* The EEPROM commands include the alway-set leading bit. */
212 #define EE_WRITE_CMD 5
213 #define EE_READ_CMD 6
214 #define EE_ERASE_CMD 7
216 static void rtl8139_eeprom_delay(uintptr_t regbase)
219 * Delay between EEPROM clock transitions.
220 * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
222 inl(regbase + RTL_REG_CFG9346);
225 static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len)
227 unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
228 uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346;
229 unsigned int retval = 0;
233 outb(EE_ENB & ~EE_CS, ee_addr);
234 outb(EE_ENB, ee_addr);
235 rtl8139_eeprom_delay(ioaddr);
237 /* Shift the read command bits out. */
238 for (i = 4 + addr_len; i >= 0; i--) {
239 dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
240 outb(EE_ENB | dataval, ee_addr);
241 rtl8139_eeprom_delay(ioaddr);
242 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
243 rtl8139_eeprom_delay(ioaddr);
246 outb(EE_ENB, ee_addr);
247 rtl8139_eeprom_delay(ioaddr);
249 for (i = 16; i > 0; i--) {
250 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
251 rtl8139_eeprom_delay(ioaddr);
253 retval |= inb(ee_addr) & EE_DATA_READ;
254 outb(EE_ENB, ee_addr);
255 rtl8139_eeprom_delay(ioaddr);
258 /* Terminate the EEPROM access. */
259 outb(~EE_CS, ee_addr);
260 rtl8139_eeprom_delay(ioaddr);
265 static const unsigned int rtl8139_rx_config =
266 (RX_BUF_LEN_IDX << 11) |
267 (RX_FIFO_THRESH << 13) |
270 static void rtl8139_set_rx_mode(struct eth_device *dev)
273 unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
274 RTL_REG_RXCONFIG_ACCEPTMULTICAST |
275 RTL_REG_RXCONFIG_ACCEPTMYPHYS;
277 outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
279 outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0);
280 outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4);
283 static void rtl8139_hw_reset(struct eth_device *dev)
288 outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
290 /* Give the chip 10ms to finish the reset. */
291 for (i = 0; i < 100; i++) {
292 reg = inb(ioaddr + RTL_REG_CHIPCMD);
293 if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
300 static void rtl8139_reset(struct eth_device *dev)
307 rtl8139_hw_reset(dev);
309 for (i = 0; i < ETH_ALEN; i++)
310 outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
312 /* Must enable Tx/Rx before setting transfer thresholds! */
313 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
314 ioaddr + RTL_REG_CHIPCMD);
316 /* accept no frames yet! */
317 outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
318 outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG);
321 * The Linux driver changes RTL_REG_CONFIG1 here to use a different
322 * LED pattern for half duplex or full/autodetect duplex (for
323 * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
324 * for half duplex it uses TX/RX, Link100, Link10). This is messy,
325 * because it doesn't match the inscription on the mounting bracket.
326 * It should not be changed from the configuration EEPROM default,
327 * because the card manufacturer should have set that to match the
330 debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
332 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
333 outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
336 * If we add multicast support, the RTL_REG_MAR0 register would have
337 * to be initialized to 0xffffffffffffffff (two 32 bit accesses).
338 * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
341 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
342 ioaddr + RTL_REG_CHIPCMD);
344 outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
346 /* Start the chip's Tx and Rx process. */
347 outl(0, ioaddr + RTL_REG_RXMISSED);
349 rtl8139_set_rx_mode(dev);
351 /* Disable all known interrupts by setting the interrupt mask. */
352 outw(0, ioaddr + RTL_REG_INTRMASK);
355 static int rtl8139_send(struct eth_device *dev, void *packet, int length)
357 unsigned int len = length;
358 unsigned long txstatus;
362 ioaddr = dev->iobase;
364 memcpy(tx_buffer, packet, length);
366 debug_cond(DEBUG_TX, "sending %d bytes\n", len);
369 * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
370 * bytes are sent automatically for the FCS, totalling to 64 bytes).
372 while (len < ETH_ZLEN)
373 tx_buffer[len++] = '\0';
375 flush_cache((unsigned long)tx_buffer, length);
376 outl(phys_to_bus((unsigned long)tx_buffer),
377 ioaddr + RTL_REG_TXADDR0 + cur_tx * 4);
378 outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
379 ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
382 status = inw(ioaddr + RTL_REG_INTRSTATUS);
384 * Only acknlowledge interrupt sources we can properly
385 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
386 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
387 * rtl8139_recv() function.
389 status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
390 RTL_REG_INTRSTATUS_PCIERR;
391 outw(status, ioaddr + RTL_REG_INTRSTATUS);
396 } while (i++ < RTL_TIMEOUT);
398 txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
400 if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
402 "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
403 10 * i, status, txstatus);
410 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
412 debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
418 static int rtl8139_recv(struct eth_device *dev)
420 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
421 RTL_REG_INTRSTATUS_RXOVERFLOW |
422 RTL_REG_INTRSTATUS_RXOK;
423 unsigned int rx_size, rx_status;
424 unsigned int ring_offs;
428 ioaddr = dev->iobase;
430 if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
433 status = inw(ioaddr + RTL_REG_INTRSTATUS);
434 /* See below for the rest of the interrupt acknowledges. */
435 outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS);
437 debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status);
439 ring_offs = cur_rx % RX_BUF_LEN;
440 /* ring_offs is guaranteed being 4-byte aligned */
441 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
442 rx_size = rx_status >> 16;
445 if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
446 RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
447 RTL_STS_RXBADALIGN)) ||
448 (rx_size < ETH_ZLEN) ||
449 (rx_size > ETH_FRAME_LEN + 4)) {
450 printf("rx error %hX\n", rx_status);
451 /* this clears all interrupts still pending */
456 /* Received a good packet */
457 length = rx_size - 4; /* no one cares about the FCS */
458 if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
459 unsigned char rxdata[RX_BUF_LEN];
460 int semi_count = RX_BUF_LEN - ring_offs - 4;
462 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
463 memcpy(&rxdata[semi_count], rx_ring,
464 rx_size - 4 - semi_count);
466 net_process_received_packet(rxdata, length);
467 debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
468 semi_count, rx_size - 4 - semi_count);
470 net_process_received_packet(rx_ring + ring_offs + 4, length);
471 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
473 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
475 cur_rx = ROUND(cur_rx + rx_size + 4, 4);
476 outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
478 * See RTL8139 Programming Guide V0.1 for the official handling of
479 * Rx overflow situations. The document itself contains basically
480 * no usable information, except for a few exception handling rules.
482 outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS);
487 static int rtl8139_init(struct eth_device *dev, bd_t *bis)
489 unsigned short *ap = (unsigned short *)dev->enetaddr;
493 ioaddr = dev->iobase;
495 /* Bring the chip out of low-power mode. */
496 outb(0x00, ioaddr + RTL_REG_CONFIG1);
498 addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6;
499 for (i = 0; i < 3; i++)
500 *ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len));
504 reg = inb(ioaddr + RTL_REG_MEDIASTATUS);
505 if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
506 printf("Cable not connected or other link failure\n");
513 static void rtl8139_stop(struct eth_device *dev)
515 ioaddr = dev->iobase;
517 rtl8139_hw_reset(dev);
520 static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
526 static struct pci_device_id supported[] = {
527 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 },
528 { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 },
532 int rtl8139_initialize(bd_t *bis)
534 struct eth_device *dev;
542 devno = pci_find_devices(supported, idx++);
546 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
549 debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
551 dev = (struct eth_device *)malloc(sizeof(*dev));
553 printf("Can not allocate memory of rtl8139\n");
556 memset(dev, 0, sizeof(*dev));
558 sprintf(dev->name, "RTL8139#%d", card_number);
560 dev->priv = (void *)devno;
561 dev->iobase = (int)bus_to_phys(iobase);
562 dev->init = rtl8139_init;
563 dev->halt = rtl8139_stop;
564 dev->send = rtl8139_send;
565 dev->recv = rtl8139_recv;
566 dev->mcast = rtl8139_bcast_addr;
572 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);