1 // SPDX-License-Identifier: GPL-2.0
3 * rtl8139.c : U-Boot driver for the RealTek RTL8139
5 * Masami Komiya (mkomiya@sonare.it)
7 * Most part is taken from rtl8139.c of etherboot
11 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
13 * ported from the linux driver written by Donald Becker
14 * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
16 * changes to the original driver:
17 * - removed support for interrupts, switching to polling mode (yuck!)
18 * - removed support for the 8129 chip (external MII)
21 /*********************************************************************/
22 /* Revision History */
23 /*********************************************************************/
26 * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
27 * Put in virt_to_bus calls to allow Etherboot relocation.
29 * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
30 * Following email from Hyun-Joon Cha, added a disable routine, otherwise
31 * NIC remains live and can crash the kernel later.
33 * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
34 * Shuffled things around, removed the leftovers from the 8129 support
35 * that was in the Linux driver and added a bit more 8139 definitions.
36 * Moved the 8K receive buffer to a fixed, available address outside the
37 * 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
38 * way to make room for the Etherboot features that need substantial amounts
39 * of code like the ANSI console support. Currently the buffer is just below
40 * 0x10000, so this even conforms to the tagged boot image specification,
41 * which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
42 * interpretation of this "reserved" is that Etherboot may do whatever it
43 * likes, as long as its environment is kept intact (like the BIOS
44 * variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms
45 * were that if Etherboot was left at the boot menu for several minutes, the
46 * first eth_poll failed. Seems like I am the only person who does this.
47 * First of all I fixed the debugging code and then set out for a long bug
48 * hunting session. It took me about a week full time work - poking around
49 * various places in the driver, reading Don Becker's and Jeff Garzik's Linux
50 * driver and even the FreeBSD driver (what a piece of crap!) - and
51 * eventually spotted the nasty thing: the transmit routine was acknowledging
52 * each and every interrupt pending, including the RxOverrun and RxFIFIOver
53 * interrupts. This confused the RTL8139 thoroughly. It destroyed the
54 * Rx ring contents by dumping the 2K FIFO contents right where we wanted to
55 * get the next packet. Oh well, what fun.
57 * 18 Jan 2000 mdc@thinguin.org (Marty Connor)
58 * Drastically simplified error handling. Basically, if any error
59 * in transmission or reception occurs, the card is reset.
60 * Also, pointed all transmit descriptors to the same buffer to
61 * save buffer space. This should decrease driver size and avoid
62 * corruption because of exceeding 32K during runtime.
64 * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
65 * rtl8139_recv was quite broken: it used the RxOK interrupt flag instead
66 * of the RxBufferEmpty flag which often resulted in very bad
67 * transmission performace - below 1kBytes/s.
73 #include <linux/types.h>
80 #define RTL_TIMEOUT 100000
82 /* PCI Tuning Parameters */
83 /* Threshold is bytes transferred to chip before transmission starts. */
84 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
85 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
86 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
87 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
88 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
89 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
90 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
91 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
93 #define DEBUG_TX 0 /* set to 1 to enable debug code */
94 #define DEBUG_RX 0 /* set to 1 to enable debug code */
96 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
97 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
99 /* Symbolic offsets to registers. */
100 /* Ethernet hardware address. */
101 #define RTL_REG_MAC0 0x00
102 /* Multicast filter. */
103 #define RTL_REG_MAR0 0x08
104 /* Transmit status (four 32bit registers). */
105 #define RTL_REG_TXSTATUS0 0x10
106 /* Tx descriptors (also four 32bit). */
107 #define RTL_REG_TXADDR0 0x20
108 #define RTL_REG_RXBUF 0x30
109 #define RTL_REG_RXEARLYCNT 0x34
110 #define RTL_REG_RXEARLYSTATUS 0x36
111 #define RTL_REG_CHIPCMD 0x37
112 #define RTL_REG_CHIPCMD_CMDRESET BIT(4)
113 #define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
114 #define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
115 #define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
116 #define RTL_REG_RXBUFPTR 0x38
117 #define RTL_REG_RXBUFADDR 0x3A
118 #define RTL_REG_INTRMASK 0x3C
119 #define RTL_REG_INTRSTATUS 0x3E
120 #define RTL_REG_INTRSTATUS_PCIERR BIT(15)
121 #define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
122 #define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
123 #define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
124 #define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
125 #define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
126 #define RTL_REG_INTRSTATUS_TXERR BIT(3)
127 #define RTL_REG_INTRSTATUS_TXOK BIT(2)
128 #define RTL_REG_INTRSTATUS_RXERR BIT(1)
129 #define RTL_REG_INTRSTATUS_RXOK BIT(0)
130 #define RTL_REG_TXCONFIG 0x40
131 #define RTL_REG_RXCONFIG 0x44
132 #define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
133 #define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
134 #define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
135 #define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
136 #define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
137 #define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
138 #define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
139 /* general-purpose counter. */
140 #define RTL_REG_TIMER 0x48
141 /* 24 bits valid, write clears. */
142 #define RTL_REG_RXMISSED 0x4C
143 #define RTL_REG_CFG9346 0x50
144 #define RTL_REG_CONFIG0 0x51
145 #define RTL_REG_CONFIG1 0x52
146 /* intr if gp counter reaches this value */
147 #define RTL_REG_TIMERINTRREG 0x54
148 #define RTL_REG_MEDIASTATUS 0x58
149 #define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
150 #define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
151 #define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
152 #define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
153 #define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
154 #define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
155 #define RTL_REG_CONFIG3 0x59
156 #define RTL_REG_MULTIINTR 0x5C
157 /* revision of the RTL8139 chip */
158 #define RTL_REG_REVISIONID 0x5E
159 #define RTL_REG_TXSUMMARY 0x60
160 #define RTL_REG_MII_BMCR 0x62
161 #define RTL_REG_MII_BMSR 0x64
162 #define RTL_REG_NWAYADVERT 0x66
163 #define RTL_REG_NWAYLPAR 0x68
164 #define RTL_REG_NWAYEXPANSION 0x6A
165 #define RTL_REG_DISCONNECTCNT 0x6C
166 #define RTL_REG_FALSECARRIERCNT 0x6E
167 #define RTL_REG_NWAYTESTREG 0x70
168 /* packet received counter */
169 #define RTL_REG_RXCNT 0x72
170 /* chip status and configuration register */
171 #define RTL_REG_CSCR 0x74
172 #define RTL_REG_PHYPARM1 0x78
173 #define RTL_REG_TWISTERPARM 0x7c
175 #define RTL_REG_PHYPARM2 0x80
177 * from 0x84 onwards are a number of power management/wakeup frame
178 * definitions we will probably never need to know about.
181 #define RTL_STS_RXMULTICAST BIT(15)
182 #define RTL_STS_RXPHYSICAL BIT(14)
183 #define RTL_STS_RXBROADCAST BIT(13)
184 #define RTL_STS_RXBADSYMBOL BIT(5)
185 #define RTL_STS_RXRUNT BIT(4)
186 #define RTL_STS_RXTOOLONG BIT(3)
187 #define RTL_STS_RXCRCERR BIT(2)
188 #define RTL_STS_RXBADALIGN BIT(1)
189 #define RTL_STS_RXSTATUSOK BIT(0)
191 static unsigned int cur_rx, cur_tx;
194 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
195 static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4);
196 static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4);
198 /* Serial EEPROM section. */
200 /* EEPROM_Ctrl bits. */
201 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
202 #define EE_CS 0x08 /* EEPROM chip select. */
203 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
204 #define EE_WRITE_0 0x00
205 #define EE_WRITE_1 0x02
206 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
207 #define EE_ENB (0x80 | EE_CS)
209 /* The EEPROM commands include the alway-set leading bit. */
210 #define EE_WRITE_CMD 5
211 #define EE_READ_CMD 6
212 #define EE_ERASE_CMD 7
214 static void rtl8139_eeprom_delay(uintptr_t regbase)
217 * Delay between EEPROM clock transitions.
218 * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
220 inl(regbase + RTL_REG_CFG9346);
223 static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len)
225 unsigned int read_cmd = location | (EE_READ_CMD << addr_len);
226 uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346;
227 unsigned int retval = 0;
231 outb(EE_ENB & ~EE_CS, ee_addr);
232 outb(EE_ENB, ee_addr);
233 rtl8139_eeprom_delay(ioaddr);
235 /* Shift the read command bits out. */
236 for (i = 4 + addr_len; i >= 0; i--) {
237 dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0;
238 outb(EE_ENB | dataval, ee_addr);
239 rtl8139_eeprom_delay(ioaddr);
240 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
241 rtl8139_eeprom_delay(ioaddr);
244 outb(EE_ENB, ee_addr);
245 rtl8139_eeprom_delay(ioaddr);
247 for (i = 16; i > 0; i--) {
248 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
249 rtl8139_eeprom_delay(ioaddr);
251 retval |= inb(ee_addr) & EE_DATA_READ;
252 outb(EE_ENB, ee_addr);
253 rtl8139_eeprom_delay(ioaddr);
256 /* Terminate the EEPROM access. */
257 outb(~EE_CS, ee_addr);
258 rtl8139_eeprom_delay(ioaddr);
263 static const unsigned int rtl8139_rx_config =
264 (RX_BUF_LEN_IDX << 11) |
265 (RX_FIFO_THRESH << 13) |
268 static void rtl8139_set_rx_mode(struct eth_device *dev)
271 unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
272 RTL_REG_RXCONFIG_ACCEPTMULTICAST |
273 RTL_REG_RXCONFIG_ACCEPTMYPHYS;
275 outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
277 outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0);
278 outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4);
281 static void rtl8139_hw_reset(struct eth_device *dev)
286 outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
288 /* Give the chip 10ms to finish the reset. */
289 for (i = 0; i < 100; i++) {
290 reg = inb(ioaddr + RTL_REG_CHIPCMD);
291 if (!(reg & RTL_REG_CHIPCMD_CMDRESET))
298 static void rtl8139_reset(struct eth_device *dev)
305 rtl8139_hw_reset(dev);
307 for (i = 0; i < ETH_ALEN; i++)
308 outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
310 /* Must enable Tx/Rx before setting transfer thresholds! */
311 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
312 ioaddr + RTL_REG_CHIPCMD);
314 /* accept no frames yet! */
315 outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
316 outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG);
319 * The Linux driver changes RTL_REG_CONFIG1 here to use a different
320 * LED pattern for half duplex or full/autodetect duplex (for
321 * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while
322 * for half duplex it uses TX/RX, Link100, Link10). This is messy,
323 * because it doesn't match the inscription on the mounting bracket.
324 * It should not be changed from the configuration EEPROM default,
325 * because the card manufacturer should have set that to match the
328 debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring);
330 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
331 outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
334 * If we add multicast support, the RTL_REG_MAR0 register would have
335 * to be initialized to 0xffffffffffffffff (two 32 bit accesses).
336 * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and
339 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
340 ioaddr + RTL_REG_CHIPCMD);
342 outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
344 /* Start the chip's Tx and Rx process. */
345 outl(0, ioaddr + RTL_REG_RXMISSED);
347 rtl8139_set_rx_mode(dev);
349 /* Disable all known interrupts by setting the interrupt mask. */
350 outw(0, ioaddr + RTL_REG_INTRMASK);
353 static int rtl8139_send(struct eth_device *dev, void *packet, int length)
355 unsigned int len = length;
356 unsigned long txstatus;
360 ioaddr = dev->iobase;
362 memcpy(tx_buffer, packet, length);
364 debug_cond(DEBUG_TX, "sending %d bytes\n", len);
367 * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
368 * bytes are sent automatically for the FCS, totalling to 64 bytes).
370 while (len < ETH_ZLEN)
371 tx_buffer[len++] = '\0';
373 flush_cache((unsigned long)tx_buffer, length);
374 outl(phys_to_bus((unsigned long)tx_buffer),
375 ioaddr + RTL_REG_TXADDR0 + cur_tx * 4);
376 outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len,
377 ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
380 status = inw(ioaddr + RTL_REG_INTRSTATUS);
382 * Only acknlowledge interrupt sources we can properly
383 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
384 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
385 * rtl8139_recv() function.
387 status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR |
388 RTL_REG_INTRSTATUS_PCIERR;
389 outw(status, ioaddr + RTL_REG_INTRSTATUS);
394 } while (i++ < RTL_TIMEOUT);
396 txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4);
398 if (!(status & RTL_REG_INTRSTATUS_TXOK)) {
400 "tx timeout/error (%d usecs), status %hX txstatus %lX\n",
401 10 * i, status, txstatus);
408 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
410 debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n",
416 static int rtl8139_recv(struct eth_device *dev)
418 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER |
419 RTL_REG_INTRSTATUS_RXOVERFLOW |
420 RTL_REG_INTRSTATUS_RXOK;
421 unsigned int rx_size, rx_status;
422 unsigned int ring_offs;
426 ioaddr = dev->iobase;
428 if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY)
431 status = inw(ioaddr + RTL_REG_INTRSTATUS);
432 /* See below for the rest of the interrupt acknowledges. */
433 outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS);
435 debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status);
437 ring_offs = cur_rx % RX_BUF_LEN;
438 /* ring_offs is guaranteed being 4-byte aligned */
439 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
440 rx_size = rx_status >> 16;
443 if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
444 RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
445 RTL_STS_RXBADALIGN)) ||
446 (rx_size < ETH_ZLEN) ||
447 (rx_size > ETH_FRAME_LEN + 4)) {
448 printf("rx error %hX\n", rx_status);
449 /* this clears all interrupts still pending */
454 /* Received a good packet */
455 length = rx_size - 4; /* no one cares about the FCS */
456 if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) {
457 unsigned char rxdata[RX_BUF_LEN];
458 int semi_count = RX_BUF_LEN - ring_offs - 4;
460 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
461 memcpy(&rxdata[semi_count], rx_ring,
462 rx_size - 4 - semi_count);
464 net_process_received_packet(rxdata, length);
465 debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
466 semi_count, rx_size - 4 - semi_count);
468 net_process_received_packet(rx_ring + ring_offs + 4, length);
469 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4);
471 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
473 cur_rx = ROUND(cur_rx + rx_size + 4, 4);
474 outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
476 * See RTL8139 Programming Guide V0.1 for the official handling of
477 * Rx overflow situations. The document itself contains basically
478 * no usable information, except for a few exception handling rules.
480 outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS);
485 static int rtl8139_init(struct eth_device *dev, bd_t *bis)
487 unsigned short *ap = (unsigned short *)dev->enetaddr;
491 ioaddr = dev->iobase;
493 /* Bring the chip out of low-power mode. */
494 outb(0x00, ioaddr + RTL_REG_CONFIG1);
496 addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6;
497 for (i = 0; i < 3; i++)
498 *ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len));
502 reg = inb(ioaddr + RTL_REG_MEDIASTATUS);
503 if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
504 printf("Cable not connected or other link failure\n");
511 static void rtl8139_stop(struct eth_device *dev)
513 ioaddr = dev->iobase;
515 rtl8139_hw_reset(dev);
518 static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
524 static struct pci_device_id supported[] = {
525 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 },
526 { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 },
530 int rtl8139_initialize(bd_t *bis)
532 struct eth_device *dev;
540 devno = pci_find_devices(supported, idx++);
544 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
547 debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
549 dev = (struct eth_device *)malloc(sizeof(*dev));
551 printf("Can not allocate memory of rtl8139\n");
554 memset(dev, 0, sizeof(*dev));
556 sprintf(dev->name, "RTL8139#%d", card_number);
558 dev->priv = (void *)devno;
559 dev->iobase = (int)bus_to_phys(iobase);
560 dev->init = rtl8139_init;
561 dev->halt = rtl8139_stop;
562 dev->send = rtl8139_send;
563 dev->recv = rtl8139_recv;
564 dev->mcast = rtl8139_bcast_addr;
570 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);