1 // SPDX-License-Identifier: GPL-2.0+
4 * This file is driver for Renesas Ethernet AVB.
6 * Copyright (C) 2015-2017 Renesas Electronics Corporation
8 * Based on the SuperH Ethernet driver.
19 #include <asm/cache.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
22 #include <linux/mii.h>
28 #define RAVB_REG_CCC 0x000
29 #define RAVB_REG_DBAT 0x004
30 #define RAVB_REG_CSR 0x00C
31 #define RAVB_REG_APSR 0x08C
32 #define RAVB_REG_RCR 0x090
33 #define RAVB_REG_TGC 0x300
34 #define RAVB_REG_TCCR 0x304
35 #define RAVB_REG_RIC0 0x360
36 #define RAVB_REG_RIC1 0x368
37 #define RAVB_REG_RIC2 0x370
38 #define RAVB_REG_TIC 0x378
39 #define RAVB_REG_ECMR 0x500
40 #define RAVB_REG_RFLR 0x508
41 #define RAVB_REG_ECSIPR 0x518
42 #define RAVB_REG_PIR 0x520
43 #define RAVB_REG_GECMR 0x5b0
44 #define RAVB_REG_MAHR 0x5c0
45 #define RAVB_REG_MALR 0x5c8
47 #define CCC_OPC_CONFIG BIT(0)
48 #define CCC_OPC_OPERATION BIT(1)
49 #define CCC_BOC BIT(20)
51 #define CSR_OPS 0x0000000F
52 #define CSR_OPS_CONFIG BIT(1)
54 #define APSR_TDM BIT(14)
56 #define TCCR_TSRQ0 BIT(0)
58 #define RFLR_RFL_MIN 0x05EE
60 #define PIR_MDI BIT(3)
61 #define PIR_MDO BIT(2)
62 #define PIR_MMD BIT(1)
63 #define PIR_MDC BIT(0)
65 #define ECMR_TRCCM BIT(26)
66 #define ECMR_RZPF BIT(20)
67 #define ECMR_PFR BIT(18)
68 #define ECMR_RXF BIT(17)
69 #define ECMR_RE BIT(6)
70 #define ECMR_TE BIT(5)
71 #define ECMR_DM BIT(1)
72 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
75 #define RAVB_NUM_BASE_DESC 16
76 #define RAVB_NUM_TX_DESC 8
77 #define RAVB_NUM_RX_DESC 8
79 #define RAVB_TX_QUEUE_OFFSET 0
80 #define RAVB_RX_QUEUE_OFFSET 4
82 #define RAVB_DESC_DT(n) ((n) << 28)
83 #define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
84 #define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
85 #define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
86 #define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
87 #define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
88 #define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
90 #define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
91 #define RAVB_DESC_DS_MASK 0xfff
93 #define RAVB_RX_DESC_MSC_MC BIT(23)
94 #define RAVB_RX_DESC_MSC_CEEF BIT(22)
95 #define RAVB_RX_DESC_MSC_CRL BIT(21)
96 #define RAVB_RX_DESC_MSC_FRE BIT(20)
97 #define RAVB_RX_DESC_MSC_RTLF BIT(19)
98 #define RAVB_RX_DESC_MSC_RTSF BIT(18)
99 #define RAVB_RX_DESC_MSC_RFE BIT(17)
100 #define RAVB_RX_DESC_MSC_CRC BIT(16)
101 #define RAVB_RX_DESC_MSC_MASK (0xff << 16)
103 #define RAVB_RX_DESC_MSC_RX_ERR_MASK \
104 (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
105 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
107 #define RAVB_TX_TIMEOUT_MS 1000
115 struct ravb_desc data;
116 struct ravb_desc link;
118 u8 packet[PKTSIZE_ALIGN];
122 struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
123 struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
124 struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
128 struct phy_device *phydev;
130 void __iomem *iobase;
132 struct gpio_desc reset_gpio;
135 static inline void ravb_flush_dcache(u32 addr, u32 len)
137 flush_dcache_range(addr, addr + len);
140 static inline void ravb_invalidate_dcache(u32 addr, u32 len)
142 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
143 u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
144 invalidate_dcache_range(start, end);
147 static int ravb_send(struct udevice *dev, void *packet, int len)
149 struct ravb_priv *eth = dev_get_priv(dev);
150 struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx];
153 /* Update TX descriptor */
154 ravb_flush_dcache((uintptr_t)packet, len);
155 memset(desc, 0x0, sizeof(*desc));
156 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
157 desc->dptr = (uintptr_t)packet;
158 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
160 /* Restart the transmitter if disabled */
161 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
162 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
164 /* Wait until packet is transmitted */
165 start = get_timer(0);
166 while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
167 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
168 if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
173 if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
176 eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
180 static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
182 struct ravb_priv *eth = dev_get_priv(dev);
183 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
187 /* Check if the rx descriptor is ready */
188 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
189 if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
192 /* Check for errors */
193 if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
194 desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
198 len = desc->data.ctrl & RAVB_DESC_DS_MASK;
199 packet = (u8 *)(uintptr_t)desc->data.dptr;
200 ravb_invalidate_dcache((uintptr_t)packet, len);
206 static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
208 struct ravb_priv *eth = dev_get_priv(dev);
209 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
211 /* Make current descriptor available again */
212 desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
213 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
215 /* Point to the next descriptor */
216 eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
217 desc = ð->rx_desc[eth->rx_desc_idx];
218 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
223 static int ravb_reset(struct udevice *dev)
225 struct ravb_priv *eth = dev_get_priv(dev);
227 /* Set config mode */
228 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
230 /* Check the operating mode is changed to the config mode. */
231 return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
232 CSR_OPS_CONFIG, true, 100, true);
235 static void ravb_base_desc_init(struct ravb_priv *eth)
237 const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
240 /* Initialize all descriptors */
241 memset(eth->base_desc, 0x0, desc_size);
243 for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
244 eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
246 ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
248 /* Register the descriptor base address table */
249 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
252 static void ravb_tx_desc_init(struct ravb_priv *eth)
254 const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
257 /* Initialize all descriptors */
258 memset(eth->tx_desc, 0x0, desc_size);
259 eth->tx_desc_idx = 0;
261 for (i = 0; i < RAVB_NUM_TX_DESC; i++)
262 eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
264 /* Mark the end of the descriptors */
265 eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
266 eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
267 ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
269 /* Point the controller to the TX descriptor list. */
270 eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
271 eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
272 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET],
273 sizeof(struct ravb_desc));
276 static void ravb_rx_desc_init(struct ravb_priv *eth)
278 const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
281 /* Initialize all descriptors */
282 memset(eth->rx_desc, 0x0, desc_size);
283 eth->rx_desc_idx = 0;
285 for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
286 eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
287 RAVB_DESC_DS(PKTSIZE_ALIGN);
288 eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
290 eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
291 eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1];
294 /* Mark the end of the descriptors */
295 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
296 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
297 ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
299 /* Point the controller to the rx descriptor list */
300 eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
301 eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
302 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET],
303 sizeof(struct ravb_desc));
306 static int ravb_phy_config(struct udevice *dev)
308 struct ravb_priv *eth = dev_get_priv(dev);
309 struct eth_pdata *pdata = dev_get_platdata(dev);
310 struct phy_device *phydev;
311 int mask = 0xffffffff, reg;
313 if (dm_gpio_is_valid(ð->reset_gpio)) {
314 dm_gpio_set_value(ð->reset_gpio, 1);
316 dm_gpio_set_value(ð->reset_gpio, 0);
320 phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
324 phy_connect_dev(phydev, dev);
326 eth->phydev = phydev;
328 phydev->supported &= SUPPORTED_100baseT_Full |
329 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
330 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause |
331 SUPPORTED_Asym_Pause;
333 if (pdata->max_speed != 1000) {
334 phydev->supported &= ~SUPPORTED_1000baseT_Full;
335 reg = phy_read(phydev, -1, MII_CTRL1000);
336 reg &= ~(BIT(9) | BIT(8));
337 phy_write(phydev, -1, MII_CTRL1000, reg);
345 /* Set Mac address */
346 static int ravb_write_hwaddr(struct udevice *dev)
348 struct ravb_priv *eth = dev_get_priv(dev);
349 struct eth_pdata *pdata = dev_get_platdata(dev);
350 unsigned char *mac = pdata->enetaddr;
352 writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
353 eth->iobase + RAVB_REG_MAHR);
355 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
360 /* E-MAC init function */
361 static int ravb_mac_init(struct ravb_priv *eth)
363 /* Disable MAC Interrupt */
364 writel(0, eth->iobase + RAVB_REG_ECSIPR);
366 /* Recv frame limit set register */
367 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
372 /* AVB-DMAC init function */
373 static int ravb_dmac_init(struct udevice *dev)
375 struct ravb_priv *eth = dev_get_priv(dev);
376 struct eth_pdata *pdata = dev_get_platdata(dev);
379 /* Set CONFIG mode */
380 ret = ravb_reset(dev);
384 /* Disable all interrupts */
385 writel(0, eth->iobase + RAVB_REG_RIC0);
386 writel(0, eth->iobase + RAVB_REG_RIC1);
387 writel(0, eth->iobase + RAVB_REG_RIC2);
388 writel(0, eth->iobase + RAVB_REG_TIC);
390 /* Set little endian */
391 clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
394 writel(0x18000001, eth->iobase + RAVB_REG_RCR);
397 writel(0x00222210, eth->iobase + RAVB_REG_TGC);
399 /* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
400 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) ||
401 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
404 if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
405 (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
406 writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
411 static int ravb_config(struct udevice *dev)
413 struct ravb_priv *eth = dev_get_priv(dev);
414 struct phy_device *phy = eth->phydev;
415 u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
418 /* Configure AVB-DMAC register */
421 /* Configure E-MAC registers */
423 ravb_write_hwaddr(dev);
425 ret = phy_startup(phy);
429 /* Set the transfer speed */
430 if (phy->speed == 100)
431 writel(0, eth->iobase + RAVB_REG_GECMR);
432 else if (phy->speed == 1000)
433 writel(1, eth->iobase + RAVB_REG_GECMR);
435 /* Check if full duplex mode is supported by the phy */
439 writel(mask, eth->iobase + RAVB_REG_ECMR);
441 phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
446 static int ravb_start(struct udevice *dev)
448 struct ravb_priv *eth = dev_get_priv(dev);
451 ret = ravb_reset(dev);
455 ravb_base_desc_init(eth);
456 ravb_tx_desc_init(eth);
457 ravb_rx_desc_init(eth);
459 ret = ravb_config(dev);
463 /* Setting the control will start the AVB-DMAC process. */
464 writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
469 static void ravb_stop(struct udevice *dev)
471 struct ravb_priv *eth = dev_get_priv(dev);
473 phy_shutdown(eth->phydev);
477 static int ravb_probe(struct udevice *dev)
479 struct eth_pdata *pdata = dev_get_platdata(dev);
480 struct ravb_priv *eth = dev_get_priv(dev);
481 struct ofnode_phandle_args phandle_args;
482 struct mii_dev *mdiodev;
483 void __iomem *iobase;
486 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
487 eth->iobase = iobase;
489 ret = clk_get_by_index(dev, 0, ð->clk);
493 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
495 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
496 ð->reset_gpio, GPIOD_IS_OUT);
499 if (!dm_gpio_is_valid(ð->reset_gpio)) {
500 gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
504 mdiodev = mdio_alloc();
510 mdiodev->read = bb_miiphy_read;
511 mdiodev->write = bb_miiphy_write;
512 bb_miiphy_buses[0].priv = eth;
513 snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
515 ret = mdio_register(mdiodev);
517 goto err_mdio_register;
519 eth->bus = miiphy_get_dev_by_name(dev->name);
522 ret = clk_enable(ð->clk);
524 goto err_mdio_register;
526 ret = ravb_reset(dev);
530 ret = ravb_phy_config(dev);
537 clk_disable(ð->clk);
541 unmap_physmem(eth->iobase, MAP_NOCACHE);
545 static int ravb_remove(struct udevice *dev)
547 struct ravb_priv *eth = dev_get_priv(dev);
549 clk_disable(ð->clk);
552 mdio_unregister(eth->bus);
554 if (dm_gpio_is_valid(ð->reset_gpio))
555 dm_gpio_free(dev, ð->reset_gpio);
556 unmap_physmem(eth->iobase, MAP_NOCACHE);
561 int ravb_bb_init(struct bb_miiphy_bus *bus)
566 int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
568 struct ravb_priv *eth = bus->priv;
570 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
575 int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
577 struct ravb_priv *eth = bus->priv;
579 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
584 int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
586 struct ravb_priv *eth = bus->priv;
589 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
591 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
596 int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
598 struct ravb_priv *eth = bus->priv;
600 *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
605 int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
607 struct ravb_priv *eth = bus->priv;
610 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
612 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
617 int ravb_bb_delay(struct bb_miiphy_bus *bus)
624 struct bb_miiphy_bus bb_miiphy_buses[] = {
627 .init = ravb_bb_init,
628 .mdio_active = ravb_bb_mdio_active,
629 .mdio_tristate = ravb_bb_mdio_tristate,
630 .set_mdio = ravb_bb_set_mdio,
631 .get_mdio = ravb_bb_get_mdio,
632 .set_mdc = ravb_bb_set_mdc,
633 .delay = ravb_bb_delay,
636 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
638 static const struct eth_ops ravb_ops = {
642 .free_pkt = ravb_free_pkt,
644 .write_hwaddr = ravb_write_hwaddr,
647 int ravb_ofdata_to_platdata(struct udevice *dev)
649 struct eth_pdata *pdata = dev_get_platdata(dev);
650 const char *phy_mode;
654 pdata->iobase = dev_read_addr(dev);
655 pdata->phy_interface = -1;
656 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
659 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
660 if (pdata->phy_interface == -1) {
661 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
665 pdata->max_speed = 1000;
666 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
668 pdata->max_speed = fdt32_to_cpu(*cell);
670 sprintf(bb_miiphy_buses[0].name, dev->name);
675 static const struct udevice_id ravb_ids[] = {
676 { .compatible = "renesas,etheravb-r8a7795" },
677 { .compatible = "renesas,etheravb-r8a7796" },
678 { .compatible = "renesas,etheravb-r8a77965" },
679 { .compatible = "renesas,etheravb-r8a77970" },
680 { .compatible = "renesas,etheravb-r8a77990" },
681 { .compatible = "renesas,etheravb-r8a77995" },
682 { .compatible = "renesas,etheravb-rcar-gen3" },
686 U_BOOT_DRIVER(eth_ravb) = {
689 .of_match = ravb_ids,
690 .ofdata_to_platdata = ravb_ofdata_to_platdata,
692 .remove = ravb_remove,
694 .priv_auto_alloc_size = sizeof(struct ravb_priv),
695 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
696 .flags = DM_FLAG_ALLOC_PRIV_DMA,