2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
30 #include <asm/system.h>
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
43 #define assert(expr) \
45 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
46 #expr,__FILE__,__func__,__LINE__); \
48 #define dprintk(fmt, args...) \
49 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
51 #define assert(expr) do {} while (0)
52 #define dprintk(fmt, args...) do {} while (0)
53 #endif /* RTL8169_DEBUG */
55 #define R8169_MSG_DEFAULT \
56 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
58 #define TX_BUFFS_AVAIL(tp) \
59 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
63 static const int multicast_filter_limit = 32;
65 /* MAC address length */
66 #define MAC_ADDR_LEN 6
68 #define MAX_READ_REQUEST_SHIFT 12
69 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
70 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
71 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
72 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
73 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
75 #define R8169_REGS_SIZE 256
76 #define R8169_NAPI_WEIGHT 64
77 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
78 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
79 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
80 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
81 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
83 #define RTL8169_TX_TIMEOUT (6*HZ)
84 #define RTL8169_PHY_TIMEOUT (10*HZ)
86 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
87 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
88 #define RTL_EEPROM_SIG_ADDR 0x0000
90 /* write/read MMIO register */
91 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
92 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
93 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
94 #define RTL_R8(reg) readb (ioaddr + (reg))
95 #define RTL_R16(reg) readw (ioaddr + (reg))
96 #define RTL_R32(reg) readl (ioaddr + (reg))
99 RTL_GIGA_MAC_NONE = 0x00,
100 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
101 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
102 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
103 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
104 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
105 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
106 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
107 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
108 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
109 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
110 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
111 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
112 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
113 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
114 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
115 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
116 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
117 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
118 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
119 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
120 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
121 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
122 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
123 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
124 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
125 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
126 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
127 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
128 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
129 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
132 #define _R(NAME,MAC,MASK) \
133 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
135 static const struct {
138 u32 RxConfigMask; /* Clears the bits supported by this chip */
139 } rtl_chip_info[] = {
140 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
141 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
142 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
143 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
144 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
145 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
146 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
147 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
148 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
149 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
150 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
153 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
154 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
155 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
156 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
157 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
158 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
159 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
160 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
161 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
162 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
163 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
164 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
165 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
166 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
167 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
168 _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
169 _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880) // PCI-E
179 static void rtl_hw_start_8169(struct net_device *);
180 static void rtl_hw_start_8168(struct net_device *);
181 static void rtl_hw_start_8101(struct net_device *);
183 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
184 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
185 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
188 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
189 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
190 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
191 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
192 { PCI_VENDOR_ID_LINKSYS, 0x1032,
193 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
195 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
199 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
201 static int rx_buf_sz = 16383;
208 MAC0 = 0, /* Ethernet hardware address. */
210 MAR0 = 8, /* Multicast filter. */
211 CounterAddrLow = 0x10,
212 CounterAddrHigh = 0x14,
213 TxDescStartAddrLow = 0x20,
214 TxDescStartAddrHigh = 0x24,
215 TxHDescStartAddrLow = 0x28,
216 TxHDescStartAddrHigh = 0x2c,
239 RxDescAddrLow = 0xe4,
240 RxDescAddrHigh = 0xe8,
241 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
243 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
245 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
247 #define TxPacketMax (8064 >> 7)
250 FuncEventMask = 0xf4,
251 FuncPresetState = 0xf8,
252 FuncForceEvent = 0xfc,
255 enum rtl8110_registers {
261 enum rtl8168_8101_registers {
264 #define CSIAR_FLAG 0x80000000
265 #define CSIAR_WRITE_CMD 0x80000000
266 #define CSIAR_BYTE_ENABLE 0x0f
267 #define CSIAR_BYTE_ENABLE_SHIFT 12
268 #define CSIAR_ADDR_MASK 0x0fff
271 #define EPHYAR_FLAG 0x80000000
272 #define EPHYAR_WRITE_CMD 0x80000000
273 #define EPHYAR_REG_MASK 0x1f
274 #define EPHYAR_REG_SHIFT 16
275 #define EPHYAR_DATA_MASK 0xffff
277 #define PM_SWITCH (1 << 6)
279 #define FIX_NAK_1 (1 << 4)
280 #define FIX_NAK_2 (1 << 3)
283 #define EN_NDP (1 << 3)
284 #define EN_OOB_RESET (1 << 2)
286 #define EFUSEAR_FLAG 0x80000000
287 #define EFUSEAR_WRITE_CMD 0x80000000
288 #define EFUSEAR_READ_CMD 0x00000000
289 #define EFUSEAR_REG_MASK 0x03ff
290 #define EFUSEAR_REG_SHIFT 8
291 #define EFUSEAR_DATA_MASK 0xff
294 enum rtl8168_registers {
297 #define ERIAR_FLAG 0x80000000
298 #define ERIAR_WRITE_CMD 0x80000000
299 #define ERIAR_READ_CMD 0x00000000
300 #define ERIAR_ADDR_BYTE_ALIGN 4
301 #define ERIAR_EXGMAC 0
304 #define ERIAR_TYPE_SHIFT 16
305 #define ERIAR_BYTEEN 0x0f
306 #define ERIAR_BYTEEN_SHIFT 12
307 EPHY_RXER_NUM = 0x7c,
308 OCPDR = 0xb0, /* OCP GPHY access */
309 #define OCPDR_WRITE_CMD 0x80000000
310 #define OCPDR_READ_CMD 0x00000000
311 #define OCPDR_REG_MASK 0x7f
312 #define OCPDR_GPHY_REG_SHIFT 16
313 #define OCPDR_DATA_MASK 0xffff
315 #define OCPAR_FLAG 0x80000000
316 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
317 #define OCPAR_GPHY_READ_CMD 0x0000f060
318 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
321 enum rtl_register_content {
322 /* InterruptStatusBits */
326 TxDescUnavail = 0x0080,
348 /* TXPoll register p.5 */
349 HPQ = 0x80, /* Poll cmd on the high prio queue */
350 NPQ = 0x40, /* Poll cmd on the low prio queue */
351 FSWInt = 0x01, /* Forced software interrupt */
355 Cfg9346_Unlock = 0xc0,
360 AcceptBroadcast = 0x08,
361 AcceptMulticast = 0x04,
363 AcceptAllPhys = 0x01,
370 TxInterFrameGapShift = 24,
371 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
373 /* Config1 register p.24 */
376 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
377 Speed_down = (1 << 4),
381 PMEnable = (1 << 0), /* Power Management Enable */
383 /* Config2 register p. 25 */
384 PCI_Clock_66MHz = 0x01,
385 PCI_Clock_33MHz = 0x00,
387 /* Config3 register p.25 */
388 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
389 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
390 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
392 /* Config5 register p.27 */
393 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
394 MWF = (1 << 5), /* Accept Multicast wakeup frame */
395 UWF = (1 << 4), /* Accept Unicast wakeup frame */
396 LanWake = (1 << 1), /* LanWake enable/disable */
397 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
400 TBIReset = 0x80000000,
401 TBILoopback = 0x40000000,
402 TBINwEnable = 0x20000000,
403 TBINwRestart = 0x10000000,
404 TBILinkOk = 0x02000000,
405 TBINwComplete = 0x01000000,
408 EnableBist = (1 << 15), // 8168 8101
409 Mac_dbgo_oe = (1 << 14), // 8168 8101
410 Normal_mode = (1 << 13), // unused
411 Force_half_dup = (1 << 12), // 8168 8101
412 Force_rxflow_en = (1 << 11), // 8168 8101
413 Force_txflow_en = (1 << 10), // 8168 8101
414 Cxpl_dbg_sel = (1 << 9), // 8168 8101
415 ASF = (1 << 8), // 8168 8101
416 PktCntrDisable = (1 << 7), // 8168 8101
417 Mac_dbgo_sel = 0x001c, // 8168
422 INTT_0 = 0x0000, // 8168
423 INTT_1 = 0x0001, // 8168
424 INTT_2 = 0x0002, // 8168
425 INTT_3 = 0x0003, // 8168
427 /* rtl8169_PHYstatus */
438 TBILinkOK = 0x02000000,
440 /* DumpCounterCommand */
444 enum desc_status_bit {
445 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
446 RingEnd = (1 << 30), /* End of descriptor ring */
447 FirstFrag = (1 << 29), /* First segment of a packet */
448 LastFrag = (1 << 28), /* Final segment of a packet */
451 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
452 MSSShift = 16, /* MSS value position */
453 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
454 IPCS = (1 << 18), /* Calculate IP checksum */
455 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
456 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
457 TxVlanTag = (1 << 17), /* Add VLAN tag */
460 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
461 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
463 #define RxProtoUDP (PID1)
464 #define RxProtoTCP (PID0)
465 #define RxProtoIP (PID1 | PID0)
466 #define RxProtoMask RxProtoIP
468 IPFail = (1 << 16), /* IP checksum failed */
469 UDPFail = (1 << 15), /* UDP/IP checksum failed */
470 TCPFail = (1 << 14), /* TCP/IP checksum failed */
471 RxVlanTag = (1 << 16), /* VLAN tag available */
474 #define RsvdMask 0x3fffc000
491 u8 __pad[sizeof(void *) - sizeof(u32)];
495 RTL_FEATURE_WOL = (1 << 0),
496 RTL_FEATURE_MSI = (1 << 1),
497 RTL_FEATURE_GMII = (1 << 2),
500 struct rtl8169_counters {
507 __le32 tx_one_collision;
508 __le32 tx_multi_collision;
516 struct rtl8169_private {
517 void __iomem *mmio_addr; /* memory map physical address */
518 struct pci_dev *pci_dev; /* Index of PCI device */
519 struct net_device *dev;
520 struct napi_struct napi;
521 spinlock_t lock; /* spin lock flag */
525 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
526 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
529 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
530 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
531 dma_addr_t TxPhyAddr;
532 dma_addr_t RxPhyAddr;
533 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
534 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
535 struct timer_list timer;
540 int phy_1000_ctrl_reg;
543 void (*write)(void __iomem *, int, int);
544 int (*read)(void __iomem *, int);
547 struct pll_power_ops {
548 void (*down)(struct rtl8169_private *);
549 void (*up)(struct rtl8169_private *);
552 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
553 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
554 void (*phy_reset_enable)(struct rtl8169_private *tp);
555 void (*hw_start)(struct net_device *);
556 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
557 unsigned int (*link_ok)(void __iomem *);
558 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
560 struct delayed_work task;
563 struct mii_if_info mii;
564 struct rtl8169_counters counters;
567 const struct firmware *fw;
570 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
571 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
572 module_param(use_dac, int, 0);
573 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
574 module_param_named(debug, debug.msg_enable, int, 0);
575 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
576 MODULE_LICENSE("GPL");
577 MODULE_VERSION(RTL8169_VERSION);
578 MODULE_FIRMWARE(FIRMWARE_8168D_1);
579 MODULE_FIRMWARE(FIRMWARE_8168D_2);
580 MODULE_FIRMWARE(FIRMWARE_8105E_1);
582 static int rtl8169_open(struct net_device *dev);
583 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
584 struct net_device *dev);
585 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
586 static int rtl8169_init_ring(struct net_device *dev);
587 static void rtl_hw_start(struct net_device *dev);
588 static int rtl8169_close(struct net_device *dev);
589 static void rtl_set_rx_mode(struct net_device *dev);
590 static void rtl8169_tx_timeout(struct net_device *dev);
591 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
592 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
593 void __iomem *, u32 budget);
594 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
595 static void rtl8169_down(struct net_device *dev);
596 static void rtl8169_rx_clear(struct rtl8169_private *tp);
597 static int rtl8169_poll(struct napi_struct *napi, int budget);
599 static const unsigned int rtl8169_rx_config =
600 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
602 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
604 void __iomem *ioaddr = tp->mmio_addr;
607 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
608 for (i = 0; i < 20; i++) {
610 if (RTL_R32(OCPAR) & OCPAR_FLAG)
613 return RTL_R32(OCPDR);
616 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
618 void __iomem *ioaddr = tp->mmio_addr;
621 RTL_W32(OCPDR, data);
622 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
623 for (i = 0; i < 20; i++) {
625 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
630 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
632 void __iomem *ioaddr = tp->mmio_addr;
636 RTL_W32(ERIAR, 0x800010e8);
638 for (i = 0; i < 5; i++) {
640 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
644 ocp_write(tp, 0x1, 0x30, 0x00000001);
647 #define OOB_CMD_RESET 0x00
648 #define OOB_CMD_DRIVER_START 0x05
649 #define OOB_CMD_DRIVER_STOP 0x06
651 static void rtl8168_driver_start(struct rtl8169_private *tp)
655 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
657 for (i = 0; i < 10; i++) {
659 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
664 static void rtl8168_driver_stop(struct rtl8169_private *tp)
668 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
670 for (i = 0; i < 10; i++) {
672 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
678 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
682 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
684 for (i = 20; i > 0; i--) {
686 * Check if the RTL8169 has completed writing to the specified
689 if (!(RTL_R32(PHYAR) & 0x80000000))
694 * According to hardware specs a 20us delay is required after write
695 * complete indication, but before sending next command.
700 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
704 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
706 for (i = 20; i > 0; i--) {
708 * Check if the RTL8169 has completed retrieving data from
709 * the specified MII register.
711 if (RTL_R32(PHYAR) & 0x80000000) {
712 value = RTL_R32(PHYAR) & 0xffff;
718 * According to hardware specs a 20us delay is required after read
719 * complete indication, but before sending next command.
726 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
730 RTL_W32(OCPDR, data |
731 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
732 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
733 RTL_W32(EPHY_RXER_NUM, 0);
735 for (i = 0; i < 100; i++) {
737 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
742 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
744 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
745 (value & OCPDR_DATA_MASK));
748 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
752 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
755 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
756 RTL_W32(EPHY_RXER_NUM, 0);
758 for (i = 0; i < 100; i++) {
760 if (RTL_R32(OCPAR) & OCPAR_FLAG)
764 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
767 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
769 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
771 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
774 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
776 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
779 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
781 r8168dp_2_mdio_start(ioaddr);
783 r8169_mdio_write(ioaddr, reg_addr, value);
785 r8168dp_2_mdio_stop(ioaddr);
788 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
792 r8168dp_2_mdio_start(ioaddr);
794 value = r8169_mdio_read(ioaddr, reg_addr);
796 r8168dp_2_mdio_stop(ioaddr);
801 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
803 tp->mdio_ops.write(tp->mmio_addr, location, val);
806 static int rtl_readphy(struct rtl8169_private *tp, int location)
808 return tp->mdio_ops.read(tp->mmio_addr, location);
811 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
813 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
816 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
820 val = rtl_readphy(tp, reg_addr);
821 rtl_writephy(tp, reg_addr, (val | p) & ~m);
824 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
827 struct rtl8169_private *tp = netdev_priv(dev);
829 rtl_writephy(tp, location, val);
832 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
834 struct rtl8169_private *tp = netdev_priv(dev);
836 return rtl_readphy(tp, location);
839 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
843 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
844 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
846 for (i = 0; i < 100; i++) {
847 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
853 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
858 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
860 for (i = 0; i < 100; i++) {
861 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
862 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
871 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
875 RTL_W32(CSIDR, value);
876 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
877 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
879 for (i = 0; i < 100; i++) {
880 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
886 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
891 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
892 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
894 for (i = 0; i < 100; i++) {
895 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
896 value = RTL_R32(CSIDR);
905 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
910 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
912 for (i = 0; i < 300; i++) {
913 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
914 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
923 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
925 RTL_W16(IntrMask, 0x0000);
927 RTL_W16(IntrStatus, 0xffff);
930 static void rtl8169_asic_down(void __iomem *ioaddr)
932 RTL_W8(ChipCmd, 0x00);
933 rtl8169_irq_mask_and_ack(ioaddr);
937 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
939 void __iomem *ioaddr = tp->mmio_addr;
941 return RTL_R32(TBICSR) & TBIReset;
944 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
946 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
949 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
951 return RTL_R32(TBICSR) & TBILinkOk;
954 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
956 return RTL_R8(PHYstatus) & LinkStatus;
959 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
961 void __iomem *ioaddr = tp->mmio_addr;
963 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
966 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
970 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
971 rtl_writephy(tp, MII_BMCR, val & 0xffff);
974 static void __rtl8169_check_link_status(struct net_device *dev,
975 struct rtl8169_private *tp,
976 void __iomem *ioaddr,
981 spin_lock_irqsave(&tp->lock, flags);
982 if (tp->link_ok(ioaddr)) {
983 /* This is to cancel a scheduled suspend if there's one. */
985 pm_request_resume(&tp->pci_dev->dev);
986 netif_carrier_on(dev);
988 netif_info(tp, ifup, dev, "link up\n");
990 netif_carrier_off(dev);
991 netif_info(tp, ifdown, dev, "link down\n");
993 pm_schedule_suspend(&tp->pci_dev->dev, 100);
995 spin_unlock_irqrestore(&tp->lock, flags);
998 static void rtl8169_check_link_status(struct net_device *dev,
999 struct rtl8169_private *tp,
1000 void __iomem *ioaddr)
1002 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1005 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1007 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1009 void __iomem *ioaddr = tp->mmio_addr;
1013 options = RTL_R8(Config1);
1014 if (!(options & PMEnable))
1017 options = RTL_R8(Config3);
1018 if (options & LinkUp)
1019 wolopts |= WAKE_PHY;
1020 if (options & MagicPacket)
1021 wolopts |= WAKE_MAGIC;
1023 options = RTL_R8(Config5);
1025 wolopts |= WAKE_UCAST;
1027 wolopts |= WAKE_BCAST;
1029 wolopts |= WAKE_MCAST;
1034 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1036 struct rtl8169_private *tp = netdev_priv(dev);
1038 spin_lock_irq(&tp->lock);
1040 wol->supported = WAKE_ANY;
1041 wol->wolopts = __rtl8169_get_wol(tp);
1043 spin_unlock_irq(&tp->lock);
1046 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1048 void __iomem *ioaddr = tp->mmio_addr;
1050 static const struct {
1055 { WAKE_ANY, Config1, PMEnable },
1056 { WAKE_PHY, Config3, LinkUp },
1057 { WAKE_MAGIC, Config3, MagicPacket },
1058 { WAKE_UCAST, Config5, UWF },
1059 { WAKE_BCAST, Config5, BWF },
1060 { WAKE_MCAST, Config5, MWF },
1061 { WAKE_ANY, Config5, LanWake }
1064 RTL_W8(Cfg9346, Cfg9346_Unlock);
1066 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1067 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1068 if (wolopts & cfg[i].opt)
1069 options |= cfg[i].mask;
1070 RTL_W8(cfg[i].reg, options);
1073 RTL_W8(Cfg9346, Cfg9346_Lock);
1076 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1078 struct rtl8169_private *tp = netdev_priv(dev);
1080 spin_lock_irq(&tp->lock);
1083 tp->features |= RTL_FEATURE_WOL;
1085 tp->features &= ~RTL_FEATURE_WOL;
1086 __rtl8169_set_wol(tp, wol->wolopts);
1087 spin_unlock_irq(&tp->lock);
1089 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1094 static void rtl8169_get_drvinfo(struct net_device *dev,
1095 struct ethtool_drvinfo *info)
1097 struct rtl8169_private *tp = netdev_priv(dev);
1099 strcpy(info->driver, MODULENAME);
1100 strcpy(info->version, RTL8169_VERSION);
1101 strcpy(info->bus_info, pci_name(tp->pci_dev));
1104 static int rtl8169_get_regs_len(struct net_device *dev)
1106 return R8169_REGS_SIZE;
1109 static int rtl8169_set_speed_tbi(struct net_device *dev,
1110 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1112 struct rtl8169_private *tp = netdev_priv(dev);
1113 void __iomem *ioaddr = tp->mmio_addr;
1117 reg = RTL_R32(TBICSR);
1118 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1119 (duplex == DUPLEX_FULL)) {
1120 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1121 } else if (autoneg == AUTONEG_ENABLE)
1122 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1124 netif_warn(tp, link, dev,
1125 "incorrect speed setting refused in TBI mode\n");
1132 static int rtl8169_set_speed_xmii(struct net_device *dev,
1133 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1135 struct rtl8169_private *tp = netdev_priv(dev);
1136 int giga_ctrl, bmcr;
1139 rtl_writephy(tp, 0x1f, 0x0000);
1141 if (autoneg == AUTONEG_ENABLE) {
1144 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1145 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1146 ADVERTISE_100HALF | ADVERTISE_100FULL);
1148 if (adv & ADVERTISED_10baseT_Half)
1149 auto_nego |= ADVERTISE_10HALF;
1150 if (adv & ADVERTISED_10baseT_Full)
1151 auto_nego |= ADVERTISE_10FULL;
1152 if (adv & ADVERTISED_100baseT_Half)
1153 auto_nego |= ADVERTISE_100HALF;
1154 if (adv & ADVERTISED_100baseT_Full)
1155 auto_nego |= ADVERTISE_100FULL;
1157 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1159 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1160 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1162 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1163 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1164 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1165 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1166 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1167 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1168 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1169 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1170 (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1171 (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1172 (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
1173 if (adv & ADVERTISED_1000baseT_Half)
1174 giga_ctrl |= ADVERTISE_1000HALF;
1175 if (adv & ADVERTISED_1000baseT_Full)
1176 giga_ctrl |= ADVERTISE_1000FULL;
1177 } else if (adv & (ADVERTISED_1000baseT_Half |
1178 ADVERTISED_1000baseT_Full)) {
1179 netif_info(tp, link, dev,
1180 "PHY does not support 1000Mbps\n");
1184 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1186 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1187 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1191 if (speed == SPEED_10)
1193 else if (speed == SPEED_100)
1194 bmcr = BMCR_SPEED100;
1198 if (duplex == DUPLEX_FULL)
1199 bmcr |= BMCR_FULLDPLX;
1202 tp->phy_1000_ctrl_reg = giga_ctrl;
1204 rtl_writephy(tp, MII_BMCR, bmcr);
1206 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1207 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1208 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1209 rtl_writephy(tp, 0x17, 0x2138);
1210 rtl_writephy(tp, 0x0e, 0x0260);
1212 rtl_writephy(tp, 0x17, 0x2108);
1213 rtl_writephy(tp, 0x0e, 0x0000);
1222 static int rtl8169_set_speed(struct net_device *dev,
1223 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1225 struct rtl8169_private *tp = netdev_priv(dev);
1228 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1230 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1231 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1236 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1238 struct rtl8169_private *tp = netdev_priv(dev);
1239 unsigned long flags;
1242 spin_lock_irqsave(&tp->lock, flags);
1243 ret = rtl8169_set_speed(dev,
1244 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1245 spin_unlock_irqrestore(&tp->lock, flags);
1250 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1252 struct rtl8169_private *tp = netdev_priv(dev);
1254 return tp->cp_cmd & RxChkSum;
1257 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1259 struct rtl8169_private *tp = netdev_priv(dev);
1260 void __iomem *ioaddr = tp->mmio_addr;
1261 unsigned long flags;
1263 spin_lock_irqsave(&tp->lock, flags);
1266 tp->cp_cmd |= RxChkSum;
1268 tp->cp_cmd &= ~RxChkSum;
1270 RTL_W16(CPlusCmd, tp->cp_cmd);
1273 spin_unlock_irqrestore(&tp->lock, flags);
1278 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1279 struct sk_buff *skb)
1281 return (vlan_tx_tag_present(skb)) ?
1282 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1285 #define NETIF_F_HW_VLAN_TX_RX (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX)
1287 static void rtl8169_vlan_mode(struct net_device *dev)
1289 struct rtl8169_private *tp = netdev_priv(dev);
1290 void __iomem *ioaddr = tp->mmio_addr;
1291 unsigned long flags;
1293 spin_lock_irqsave(&tp->lock, flags);
1294 if (dev->features & NETIF_F_HW_VLAN_RX)
1295 tp->cp_cmd |= RxVlan;
1297 tp->cp_cmd &= ~RxVlan;
1298 RTL_W16(CPlusCmd, tp->cp_cmd);
1301 spin_unlock_irqrestore(&tp->lock, flags);
1303 dev->vlan_features = dev->features &~ NETIF_F_HW_VLAN_TX_RX;
1306 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1308 u32 opts2 = le32_to_cpu(desc->opts2);
1310 if (opts2 & RxVlanTag)
1311 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1316 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1318 struct rtl8169_private *tp = netdev_priv(dev);
1319 void __iomem *ioaddr = tp->mmio_addr;
1323 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1324 cmd->port = PORT_FIBRE;
1325 cmd->transceiver = XCVR_INTERNAL;
1327 status = RTL_R32(TBICSR);
1328 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1329 cmd->autoneg = !!(status & TBINwEnable);
1331 cmd->speed = SPEED_1000;
1332 cmd->duplex = DUPLEX_FULL; /* Always set */
1337 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1339 struct rtl8169_private *tp = netdev_priv(dev);
1341 return mii_ethtool_gset(&tp->mii, cmd);
1344 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1346 struct rtl8169_private *tp = netdev_priv(dev);
1347 unsigned long flags;
1350 spin_lock_irqsave(&tp->lock, flags);
1352 rc = tp->get_settings(dev, cmd);
1354 spin_unlock_irqrestore(&tp->lock, flags);
1358 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1361 struct rtl8169_private *tp = netdev_priv(dev);
1362 unsigned long flags;
1364 if (regs->len > R8169_REGS_SIZE)
1365 regs->len = R8169_REGS_SIZE;
1367 spin_lock_irqsave(&tp->lock, flags);
1368 memcpy_fromio(p, tp->mmio_addr, regs->len);
1369 spin_unlock_irqrestore(&tp->lock, flags);
1372 static u32 rtl8169_get_msglevel(struct net_device *dev)
1374 struct rtl8169_private *tp = netdev_priv(dev);
1376 return tp->msg_enable;
1379 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1381 struct rtl8169_private *tp = netdev_priv(dev);
1383 tp->msg_enable = value;
1386 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1393 "tx_single_collisions",
1394 "tx_multi_collisions",
1402 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1406 return ARRAY_SIZE(rtl8169_gstrings);
1412 static void rtl8169_update_counters(struct net_device *dev)
1414 struct rtl8169_private *tp = netdev_priv(dev);
1415 void __iomem *ioaddr = tp->mmio_addr;
1416 struct rtl8169_counters *counters;
1420 struct device *d = &tp->pci_dev->dev;
1423 * Some chips are unable to dump tally counters when the receiver
1426 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1429 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1433 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1434 cmd = (u64)paddr & DMA_BIT_MASK(32);
1435 RTL_W32(CounterAddrLow, cmd);
1436 RTL_W32(CounterAddrLow, cmd | CounterDump);
1439 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1440 /* copy updated counters */
1441 memcpy(&tp->counters, counters, sizeof(*counters));
1447 RTL_W32(CounterAddrLow, 0);
1448 RTL_W32(CounterAddrHigh, 0);
1450 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1453 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1454 struct ethtool_stats *stats, u64 *data)
1456 struct rtl8169_private *tp = netdev_priv(dev);
1460 rtl8169_update_counters(dev);
1462 data[0] = le64_to_cpu(tp->counters.tx_packets);
1463 data[1] = le64_to_cpu(tp->counters.rx_packets);
1464 data[2] = le64_to_cpu(tp->counters.tx_errors);
1465 data[3] = le32_to_cpu(tp->counters.rx_errors);
1466 data[4] = le16_to_cpu(tp->counters.rx_missed);
1467 data[5] = le16_to_cpu(tp->counters.align_errors);
1468 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1469 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1470 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1471 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1472 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1473 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1474 data[12] = le16_to_cpu(tp->counters.tx_underun);
1477 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1481 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1486 static int rtl8169_set_flags(struct net_device *dev, u32 data)
1488 struct rtl8169_private *tp = netdev_priv(dev);
1489 unsigned long old_feat = dev->features;
1492 if ((tp->mac_version == RTL_GIGA_MAC_VER_05) &&
1493 !(data & ETH_FLAG_RXVLAN)) {
1494 netif_info(tp, drv, dev, "8110SCd requires hardware Rx VLAN\n");
1498 rc = ethtool_op_set_flags(dev, data, ETH_FLAG_TXVLAN | ETH_FLAG_RXVLAN);
1502 if ((old_feat ^ dev->features) & NETIF_F_HW_VLAN_RX)
1503 rtl8169_vlan_mode(dev);
1508 static const struct ethtool_ops rtl8169_ethtool_ops = {
1509 .get_drvinfo = rtl8169_get_drvinfo,
1510 .get_regs_len = rtl8169_get_regs_len,
1511 .get_link = ethtool_op_get_link,
1512 .get_settings = rtl8169_get_settings,
1513 .set_settings = rtl8169_set_settings,
1514 .get_msglevel = rtl8169_get_msglevel,
1515 .set_msglevel = rtl8169_set_msglevel,
1516 .get_rx_csum = rtl8169_get_rx_csum,
1517 .set_rx_csum = rtl8169_set_rx_csum,
1518 .set_tx_csum = ethtool_op_set_tx_csum,
1519 .set_sg = ethtool_op_set_sg,
1520 .set_tso = ethtool_op_set_tso,
1521 .get_regs = rtl8169_get_regs,
1522 .get_wol = rtl8169_get_wol,
1523 .set_wol = rtl8169_set_wol,
1524 .get_strings = rtl8169_get_strings,
1525 .get_sset_count = rtl8169_get_sset_count,
1526 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1527 .set_flags = rtl8169_set_flags,
1528 .get_flags = ethtool_op_get_flags,
1531 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1532 void __iomem *ioaddr)
1535 * The driver currently handles the 8168Bf and the 8168Be identically
1536 * but they can be identified more specifically through the test below
1539 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1541 * Same thing for the 8101Eb and the 8101Ec:
1543 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1545 static const struct {
1551 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1552 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1553 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1555 /* 8168DP family. */
1556 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1557 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1560 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1561 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1562 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1563 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1564 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1565 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1566 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1567 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1568 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1571 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1572 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1573 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1574 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1577 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1578 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1579 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1580 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1581 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1582 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1583 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1584 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1585 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1586 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1587 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1588 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1589 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1590 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1591 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1592 /* FIXME: where did these entries come from ? -- FR */
1593 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1594 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1597 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1598 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1599 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1600 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1601 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1602 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1605 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1609 reg = RTL_R32(TxConfig);
1610 while ((reg & p->mask) != p->val)
1612 tp->mac_version = p->mac_version;
1615 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1617 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1625 static void rtl_writephy_batch(struct rtl8169_private *tp,
1626 const struct phy_reg *regs, int len)
1629 rtl_writephy(tp, regs->reg, regs->val);
1634 #define PHY_READ 0x00000000
1635 #define PHY_DATA_OR 0x10000000
1636 #define PHY_DATA_AND 0x20000000
1637 #define PHY_BJMPN 0x30000000
1638 #define PHY_READ_EFUSE 0x40000000
1639 #define PHY_READ_MAC_BYTE 0x50000000
1640 #define PHY_WRITE_MAC_BYTE 0x60000000
1641 #define PHY_CLEAR_READCOUNT 0x70000000
1642 #define PHY_WRITE 0x80000000
1643 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1644 #define PHY_COMP_EQ_SKIPN 0xa0000000
1645 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1646 #define PHY_WRITE_PREVIOUS 0xc0000000
1647 #define PHY_SKIPN 0xd0000000
1648 #define PHY_DELAY_MS 0xe0000000
1649 #define PHY_WRITE_ERI_WORD 0xf0000000
1652 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1654 __le32 *phytable = (__le32 *)fw->data;
1655 struct net_device *dev = tp->dev;
1656 size_t index, fw_size = fw->size / sizeof(*phytable);
1659 if (fw->size % sizeof(*phytable)) {
1660 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1664 for (index = 0; index < fw_size; index++) {
1665 u32 action = le32_to_cpu(phytable[index]);
1666 u32 regno = (action & 0x0fff0000) >> 16;
1668 switch(action & 0xf0000000) {
1672 case PHY_READ_EFUSE:
1673 case PHY_CLEAR_READCOUNT:
1675 case PHY_WRITE_PREVIOUS:
1680 if (regno > index) {
1681 netif_err(tp, probe, tp->dev,
1682 "Out of range of firmware\n");
1686 case PHY_READCOUNT_EQ_SKIP:
1687 if (index + 2 >= fw_size) {
1688 netif_err(tp, probe, tp->dev,
1689 "Out of range of firmware\n");
1693 case PHY_COMP_EQ_SKIPN:
1694 case PHY_COMP_NEQ_SKIPN:
1696 if (index + 1 + regno >= fw_size) {
1697 netif_err(tp, probe, tp->dev,
1698 "Out of range of firmware\n");
1703 case PHY_READ_MAC_BYTE:
1704 case PHY_WRITE_MAC_BYTE:
1705 case PHY_WRITE_ERI_WORD:
1707 netif_err(tp, probe, tp->dev,
1708 "Invalid action 0x%08x\n", action);
1716 for (index = 0; index < fw_size; ) {
1717 u32 action = le32_to_cpu(phytable[index]);
1718 u32 data = action & 0x0000ffff;
1719 u32 regno = (action & 0x0fff0000) >> 16;
1724 switch(action & 0xf0000000) {
1726 predata = rtl_readphy(tp, regno);
1741 case PHY_READ_EFUSE:
1742 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1745 case PHY_CLEAR_READCOUNT:
1750 rtl_writephy(tp, regno, data);
1753 case PHY_READCOUNT_EQ_SKIP:
1759 case PHY_COMP_EQ_SKIPN:
1760 if (predata == data)
1764 case PHY_COMP_NEQ_SKIPN:
1765 if (predata != data)
1769 case PHY_WRITE_PREVIOUS:
1770 rtl_writephy(tp, regno, predata);
1781 case PHY_READ_MAC_BYTE:
1782 case PHY_WRITE_MAC_BYTE:
1783 case PHY_WRITE_ERI_WORD:
1790 static void rtl_release_firmware(struct rtl8169_private *tp)
1792 release_firmware(tp->fw);
1796 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1798 const struct firmware **fw = &tp->fw;
1802 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1807 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1808 rtl_phy_write_fw(tp, *fw);
1813 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1815 static const struct phy_reg phy_reg_init[] = {
1877 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1880 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1882 static const struct phy_reg phy_reg_init[] = {
1888 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1891 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1893 struct pci_dev *pdev = tp->pci_dev;
1894 u16 vendor_id, device_id;
1896 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1897 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1899 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1902 rtl_writephy(tp, 0x1f, 0x0001);
1903 rtl_writephy(tp, 0x10, 0xf01b);
1904 rtl_writephy(tp, 0x1f, 0x0000);
1907 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1909 static const struct phy_reg phy_reg_init[] = {
1949 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1951 rtl8169scd_hw_phy_config_quirk(tp);
1954 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1956 static const struct phy_reg phy_reg_init[] = {
2004 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2007 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2009 static const struct phy_reg phy_reg_init[] = {
2014 rtl_writephy(tp, 0x1f, 0x0001);
2015 rtl_patchphy(tp, 0x16, 1 << 0);
2017 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2020 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2022 static const struct phy_reg phy_reg_init[] = {
2028 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2031 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2033 static const struct phy_reg phy_reg_init[] = {
2041 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2044 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2046 static const struct phy_reg phy_reg_init[] = {
2052 rtl_writephy(tp, 0x1f, 0x0000);
2053 rtl_patchphy(tp, 0x14, 1 << 5);
2054 rtl_patchphy(tp, 0x0d, 1 << 5);
2056 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2059 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2061 static const struct phy_reg phy_reg_init[] = {
2081 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2083 rtl_patchphy(tp, 0x14, 1 << 5);
2084 rtl_patchphy(tp, 0x0d, 1 << 5);
2085 rtl_writephy(tp, 0x1f, 0x0000);
2088 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2090 static const struct phy_reg phy_reg_init[] = {
2108 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2110 rtl_patchphy(tp, 0x16, 1 << 0);
2111 rtl_patchphy(tp, 0x14, 1 << 5);
2112 rtl_patchphy(tp, 0x0d, 1 << 5);
2113 rtl_writephy(tp, 0x1f, 0x0000);
2116 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2118 static const struct phy_reg phy_reg_init[] = {
2130 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2132 rtl_patchphy(tp, 0x16, 1 << 0);
2133 rtl_patchphy(tp, 0x14, 1 << 5);
2134 rtl_patchphy(tp, 0x0d, 1 << 5);
2135 rtl_writephy(tp, 0x1f, 0x0000);
2138 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2140 rtl8168c_3_hw_phy_config(tp);
2143 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2145 static const struct phy_reg phy_reg_init_0[] = {
2146 /* Channel Estimation */
2167 * enhance line driver power
2176 * Can not link to 1Gbps with bad cable
2177 * Decrease SNR threshold form 21.07dB to 19.04dB
2185 void __iomem *ioaddr = tp->mmio_addr;
2187 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2191 * Fine Tune Switching regulator parameter
2193 rtl_writephy(tp, 0x1f, 0x0002);
2194 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2195 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2197 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2198 static const struct phy_reg phy_reg_init[] = {
2208 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2210 val = rtl_readphy(tp, 0x0d);
2212 if ((val & 0x00ff) != 0x006c) {
2213 static const u32 set[] = {
2214 0x0065, 0x0066, 0x0067, 0x0068,
2215 0x0069, 0x006a, 0x006b, 0x006c
2219 rtl_writephy(tp, 0x1f, 0x0002);
2222 for (i = 0; i < ARRAY_SIZE(set); i++)
2223 rtl_writephy(tp, 0x0d, val | set[i]);
2226 static const struct phy_reg phy_reg_init[] = {
2234 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2237 /* RSET couple improve */
2238 rtl_writephy(tp, 0x1f, 0x0002);
2239 rtl_patchphy(tp, 0x0d, 0x0300);
2240 rtl_patchphy(tp, 0x0f, 0x0010);
2242 /* Fine tune PLL performance */
2243 rtl_writephy(tp, 0x1f, 0x0002);
2244 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2245 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2247 rtl_writephy(tp, 0x1f, 0x0005);
2248 rtl_writephy(tp, 0x05, 0x001b);
2249 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2250 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2251 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2254 rtl_writephy(tp, 0x1f, 0x0000);
2257 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2259 static const struct phy_reg phy_reg_init_0[] = {
2260 /* Channel Estimation */
2281 * enhance line driver power
2290 * Can not link to 1Gbps with bad cable
2291 * Decrease SNR threshold form 21.07dB to 19.04dB
2299 void __iomem *ioaddr = tp->mmio_addr;
2301 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2303 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2304 static const struct phy_reg phy_reg_init[] = {
2315 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2317 val = rtl_readphy(tp, 0x0d);
2318 if ((val & 0x00ff) != 0x006c) {
2319 static const u32 set[] = {
2320 0x0065, 0x0066, 0x0067, 0x0068,
2321 0x0069, 0x006a, 0x006b, 0x006c
2325 rtl_writephy(tp, 0x1f, 0x0002);
2328 for (i = 0; i < ARRAY_SIZE(set); i++)
2329 rtl_writephy(tp, 0x0d, val | set[i]);
2332 static const struct phy_reg phy_reg_init[] = {
2340 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2343 /* Fine tune PLL performance */
2344 rtl_writephy(tp, 0x1f, 0x0002);
2345 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2346 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2348 /* Switching regulator Slew rate */
2349 rtl_writephy(tp, 0x1f, 0x0002);
2350 rtl_patchphy(tp, 0x0f, 0x0017);
2352 rtl_writephy(tp, 0x1f, 0x0005);
2353 rtl_writephy(tp, 0x05, 0x001b);
2354 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2355 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2356 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2359 rtl_writephy(tp, 0x1f, 0x0000);
2362 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2364 static const struct phy_reg phy_reg_init[] = {
2420 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2423 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2425 static const struct phy_reg phy_reg_init[] = {
2435 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2436 rtl_patchphy(tp, 0x0d, 1 << 5);
2439 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2441 static const struct phy_reg phy_reg_init[] = {
2448 rtl_writephy(tp, 0x1f, 0x0000);
2449 rtl_patchphy(tp, 0x11, 1 << 12);
2450 rtl_patchphy(tp, 0x19, 1 << 13);
2451 rtl_patchphy(tp, 0x10, 1 << 15);
2453 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2456 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2458 static const struct phy_reg phy_reg_init[] = {
2472 /* Disable ALDPS before ram code */
2473 rtl_writephy(tp, 0x1f, 0x0000);
2474 rtl_writephy(tp, 0x18, 0x0310);
2477 if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0)
2478 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2480 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2483 static void rtl_hw_phy_config(struct net_device *dev)
2485 struct rtl8169_private *tp = netdev_priv(dev);
2487 rtl8169_print_mac_version(tp);
2489 switch (tp->mac_version) {
2490 case RTL_GIGA_MAC_VER_01:
2492 case RTL_GIGA_MAC_VER_02:
2493 case RTL_GIGA_MAC_VER_03:
2494 rtl8169s_hw_phy_config(tp);
2496 case RTL_GIGA_MAC_VER_04:
2497 rtl8169sb_hw_phy_config(tp);
2499 case RTL_GIGA_MAC_VER_05:
2500 rtl8169scd_hw_phy_config(tp);
2502 case RTL_GIGA_MAC_VER_06:
2503 rtl8169sce_hw_phy_config(tp);
2505 case RTL_GIGA_MAC_VER_07:
2506 case RTL_GIGA_MAC_VER_08:
2507 case RTL_GIGA_MAC_VER_09:
2508 rtl8102e_hw_phy_config(tp);
2510 case RTL_GIGA_MAC_VER_11:
2511 rtl8168bb_hw_phy_config(tp);
2513 case RTL_GIGA_MAC_VER_12:
2514 rtl8168bef_hw_phy_config(tp);
2516 case RTL_GIGA_MAC_VER_17:
2517 rtl8168bef_hw_phy_config(tp);
2519 case RTL_GIGA_MAC_VER_18:
2520 rtl8168cp_1_hw_phy_config(tp);
2522 case RTL_GIGA_MAC_VER_19:
2523 rtl8168c_1_hw_phy_config(tp);
2525 case RTL_GIGA_MAC_VER_20:
2526 rtl8168c_2_hw_phy_config(tp);
2528 case RTL_GIGA_MAC_VER_21:
2529 rtl8168c_3_hw_phy_config(tp);
2531 case RTL_GIGA_MAC_VER_22:
2532 rtl8168c_4_hw_phy_config(tp);
2534 case RTL_GIGA_MAC_VER_23:
2535 case RTL_GIGA_MAC_VER_24:
2536 rtl8168cp_2_hw_phy_config(tp);
2538 case RTL_GIGA_MAC_VER_25:
2539 rtl8168d_1_hw_phy_config(tp);
2541 case RTL_GIGA_MAC_VER_26:
2542 rtl8168d_2_hw_phy_config(tp);
2544 case RTL_GIGA_MAC_VER_27:
2545 rtl8168d_3_hw_phy_config(tp);
2547 case RTL_GIGA_MAC_VER_28:
2548 rtl8168d_4_hw_phy_config(tp);
2550 case RTL_GIGA_MAC_VER_29:
2551 case RTL_GIGA_MAC_VER_30:
2552 rtl8105e_hw_phy_config(tp);
2560 static void rtl8169_phy_timer(unsigned long __opaque)
2562 struct net_device *dev = (struct net_device *)__opaque;
2563 struct rtl8169_private *tp = netdev_priv(dev);
2564 struct timer_list *timer = &tp->timer;
2565 void __iomem *ioaddr = tp->mmio_addr;
2566 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2568 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2570 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2573 spin_lock_irq(&tp->lock);
2575 if (tp->phy_reset_pending(tp)) {
2577 * A busy loop could burn quite a few cycles on nowadays CPU.
2578 * Let's delay the execution of the timer for a few ticks.
2584 if (tp->link_ok(ioaddr))
2587 netif_warn(tp, link, dev, "PHY reset until link up\n");
2589 tp->phy_reset_enable(tp);
2592 mod_timer(timer, jiffies + timeout);
2594 spin_unlock_irq(&tp->lock);
2597 static inline void rtl8169_delete_timer(struct net_device *dev)
2599 struct rtl8169_private *tp = netdev_priv(dev);
2600 struct timer_list *timer = &tp->timer;
2602 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2605 del_timer_sync(timer);
2608 static inline void rtl8169_request_timer(struct net_device *dev)
2610 struct rtl8169_private *tp = netdev_priv(dev);
2611 struct timer_list *timer = &tp->timer;
2613 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2616 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2619 #ifdef CONFIG_NET_POLL_CONTROLLER
2621 * Polling 'interrupt' - used by things like netconsole to send skbs
2622 * without having to re-enable interrupts. It's not called while
2623 * the interrupt routine is executing.
2625 static void rtl8169_netpoll(struct net_device *dev)
2627 struct rtl8169_private *tp = netdev_priv(dev);
2628 struct pci_dev *pdev = tp->pci_dev;
2630 disable_irq(pdev->irq);
2631 rtl8169_interrupt(pdev->irq, dev);
2632 enable_irq(pdev->irq);
2636 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2637 void __iomem *ioaddr)
2640 pci_release_regions(pdev);
2641 pci_clear_mwi(pdev);
2642 pci_disable_device(pdev);
2646 static void rtl8169_phy_reset(struct net_device *dev,
2647 struct rtl8169_private *tp)
2651 tp->phy_reset_enable(tp);
2652 for (i = 0; i < 100; i++) {
2653 if (!tp->phy_reset_pending(tp))
2657 netif_err(tp, link, dev, "PHY reset failed\n");
2660 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2662 void __iomem *ioaddr = tp->mmio_addr;
2664 rtl_hw_phy_config(dev);
2666 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2667 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2671 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2673 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2674 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2676 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2677 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2679 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2680 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2683 rtl8169_phy_reset(dev, tp);
2685 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2686 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2687 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2688 (tp->mii.supports_gmii ?
2689 ADVERTISED_1000baseT_Half |
2690 ADVERTISED_1000baseT_Full : 0));
2692 if (RTL_R8(PHYstatus) & TBI_Enable)
2693 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2696 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2698 void __iomem *ioaddr = tp->mmio_addr;
2702 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2703 high = addr[4] | (addr[5] << 8);
2705 spin_lock_irq(&tp->lock);
2707 RTL_W8(Cfg9346, Cfg9346_Unlock);
2709 RTL_W32(MAC4, high);
2715 RTL_W8(Cfg9346, Cfg9346_Lock);
2717 spin_unlock_irq(&tp->lock);
2720 static int rtl_set_mac_address(struct net_device *dev, void *p)
2722 struct rtl8169_private *tp = netdev_priv(dev);
2723 struct sockaddr *addr = p;
2725 if (!is_valid_ether_addr(addr->sa_data))
2726 return -EADDRNOTAVAIL;
2728 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2730 rtl_rar_set(tp, dev->dev_addr);
2735 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2737 struct rtl8169_private *tp = netdev_priv(dev);
2738 struct mii_ioctl_data *data = if_mii(ifr);
2740 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2743 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2747 data->phy_id = 32; /* Internal PHY */
2751 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2755 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2761 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2766 static const struct rtl_cfg_info {
2767 void (*hw_start)(struct net_device *);
2768 unsigned int region;
2774 } rtl_cfg_infos [] = {
2776 .hw_start = rtl_hw_start_8169,
2779 .intr_event = SYSErr | LinkChg | RxOverflow |
2780 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2781 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2782 .features = RTL_FEATURE_GMII,
2783 .default_ver = RTL_GIGA_MAC_VER_01,
2786 .hw_start = rtl_hw_start_8168,
2789 .intr_event = SYSErr | LinkChg | RxOverflow |
2790 TxErr | TxOK | RxOK | RxErr,
2791 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2792 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2793 .default_ver = RTL_GIGA_MAC_VER_11,
2796 .hw_start = rtl_hw_start_8101,
2799 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2800 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2801 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2802 .features = RTL_FEATURE_MSI,
2803 .default_ver = RTL_GIGA_MAC_VER_13,
2807 /* Cfg9346_Unlock assumed. */
2808 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2809 const struct rtl_cfg_info *cfg)
2814 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2815 if (cfg->features & RTL_FEATURE_MSI) {
2816 if (pci_enable_msi(pdev)) {
2817 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2820 msi = RTL_FEATURE_MSI;
2823 RTL_W8(Config2, cfg2);
2827 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2829 if (tp->features & RTL_FEATURE_MSI) {
2830 pci_disable_msi(pdev);
2831 tp->features &= ~RTL_FEATURE_MSI;
2835 static const struct net_device_ops rtl8169_netdev_ops = {
2836 .ndo_open = rtl8169_open,
2837 .ndo_stop = rtl8169_close,
2838 .ndo_get_stats = rtl8169_get_stats,
2839 .ndo_start_xmit = rtl8169_start_xmit,
2840 .ndo_tx_timeout = rtl8169_tx_timeout,
2841 .ndo_validate_addr = eth_validate_addr,
2842 .ndo_change_mtu = rtl8169_change_mtu,
2843 .ndo_set_mac_address = rtl_set_mac_address,
2844 .ndo_do_ioctl = rtl8169_ioctl,
2845 .ndo_set_multicast_list = rtl_set_rx_mode,
2846 #ifdef CONFIG_NET_POLL_CONTROLLER
2847 .ndo_poll_controller = rtl8169_netpoll,
2852 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2854 struct mdio_ops *ops = &tp->mdio_ops;
2856 switch (tp->mac_version) {
2857 case RTL_GIGA_MAC_VER_27:
2858 ops->write = r8168dp_1_mdio_write;
2859 ops->read = r8168dp_1_mdio_read;
2861 case RTL_GIGA_MAC_VER_28:
2862 ops->write = r8168dp_2_mdio_write;
2863 ops->read = r8168dp_2_mdio_read;
2866 ops->write = r8169_mdio_write;
2867 ops->read = r8169_mdio_read;
2872 static void r810x_phy_power_down(struct rtl8169_private *tp)
2874 rtl_writephy(tp, 0x1f, 0x0000);
2875 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2878 static void r810x_phy_power_up(struct rtl8169_private *tp)
2880 rtl_writephy(tp, 0x1f, 0x0000);
2881 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2884 static void r810x_pll_power_down(struct rtl8169_private *tp)
2886 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2887 rtl_writephy(tp, 0x1f, 0x0000);
2888 rtl_writephy(tp, MII_BMCR, 0x0000);
2892 r810x_phy_power_down(tp);
2895 static void r810x_pll_power_up(struct rtl8169_private *tp)
2897 r810x_phy_power_up(tp);
2900 static void r8168_phy_power_up(struct rtl8169_private *tp)
2902 rtl_writephy(tp, 0x1f, 0x0000);
2903 rtl_writephy(tp, 0x0e, 0x0000);
2904 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2907 static void r8168_phy_power_down(struct rtl8169_private *tp)
2909 rtl_writephy(tp, 0x1f, 0x0000);
2910 rtl_writephy(tp, 0x0e, 0x0200);
2911 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2914 static void r8168_pll_power_down(struct rtl8169_private *tp)
2916 void __iomem *ioaddr = tp->mmio_addr;
2918 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2919 (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2920 (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
2924 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2925 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2926 (RTL_R16(CPlusCmd) & ASF)) {
2930 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2931 rtl_writephy(tp, 0x1f, 0x0000);
2932 rtl_writephy(tp, MII_BMCR, 0x0000);
2934 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2935 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2939 r8168_phy_power_down(tp);
2941 switch (tp->mac_version) {
2942 case RTL_GIGA_MAC_VER_25:
2943 case RTL_GIGA_MAC_VER_26:
2944 case RTL_GIGA_MAC_VER_27:
2945 case RTL_GIGA_MAC_VER_28:
2946 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2951 static void r8168_pll_power_up(struct rtl8169_private *tp)
2953 void __iomem *ioaddr = tp->mmio_addr;
2955 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2956 (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2957 (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
2961 switch (tp->mac_version) {
2962 case RTL_GIGA_MAC_VER_25:
2963 case RTL_GIGA_MAC_VER_26:
2964 case RTL_GIGA_MAC_VER_27:
2965 case RTL_GIGA_MAC_VER_28:
2966 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2970 r8168_phy_power_up(tp);
2973 static void rtl_pll_power_op(struct rtl8169_private *tp,
2974 void (*op)(struct rtl8169_private *))
2980 static void rtl_pll_power_down(struct rtl8169_private *tp)
2982 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2985 static void rtl_pll_power_up(struct rtl8169_private *tp)
2987 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2990 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2992 struct pll_power_ops *ops = &tp->pll_power_ops;
2994 switch (tp->mac_version) {
2995 case RTL_GIGA_MAC_VER_07:
2996 case RTL_GIGA_MAC_VER_08:
2997 case RTL_GIGA_MAC_VER_09:
2998 case RTL_GIGA_MAC_VER_10:
2999 case RTL_GIGA_MAC_VER_16:
3000 case RTL_GIGA_MAC_VER_29:
3001 case RTL_GIGA_MAC_VER_30:
3002 ops->down = r810x_pll_power_down;
3003 ops->up = r810x_pll_power_up;
3006 case RTL_GIGA_MAC_VER_11:
3007 case RTL_GIGA_MAC_VER_12:
3008 case RTL_GIGA_MAC_VER_17:
3009 case RTL_GIGA_MAC_VER_18:
3010 case RTL_GIGA_MAC_VER_19:
3011 case RTL_GIGA_MAC_VER_20:
3012 case RTL_GIGA_MAC_VER_21:
3013 case RTL_GIGA_MAC_VER_22:
3014 case RTL_GIGA_MAC_VER_23:
3015 case RTL_GIGA_MAC_VER_24:
3016 case RTL_GIGA_MAC_VER_25:
3017 case RTL_GIGA_MAC_VER_26:
3018 case RTL_GIGA_MAC_VER_27:
3019 case RTL_GIGA_MAC_VER_28:
3020 ops->down = r8168_pll_power_down;
3021 ops->up = r8168_pll_power_up;
3031 static int __devinit
3032 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3034 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3035 const unsigned int region = cfg->region;
3036 struct rtl8169_private *tp;
3037 struct mii_if_info *mii;
3038 struct net_device *dev;
3039 void __iomem *ioaddr;
3043 if (netif_msg_drv(&debug)) {
3044 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3045 MODULENAME, RTL8169_VERSION);
3048 dev = alloc_etherdev(sizeof (*tp));
3050 if (netif_msg_drv(&debug))
3051 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3056 SET_NETDEV_DEV(dev, &pdev->dev);
3057 dev->netdev_ops = &rtl8169_netdev_ops;
3058 tp = netdev_priv(dev);
3061 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3065 mii->mdio_read = rtl_mdio_read;
3066 mii->mdio_write = rtl_mdio_write;
3067 mii->phy_id_mask = 0x1f;
3068 mii->reg_num_mask = 0x1f;
3069 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3071 /* disable ASPM completely as that cause random device stop working
3072 * problems as well as full system hangs for some PCIe devices users */
3073 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3074 PCIE_LINK_STATE_CLKPM);
3076 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3077 rc = pci_enable_device(pdev);
3079 netif_err(tp, probe, dev, "enable failure\n");
3080 goto err_out_free_dev_1;
3083 if (pci_set_mwi(pdev) < 0)
3084 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3086 /* make sure PCI base addr 1 is MMIO */
3087 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3088 netif_err(tp, probe, dev,
3089 "region #%d not an MMIO resource, aborting\n",
3095 /* check for weird/broken PCI region reporting */
3096 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3097 netif_err(tp, probe, dev,
3098 "Invalid PCI region size(s), aborting\n");
3103 rc = pci_request_regions(pdev, MODULENAME);
3105 netif_err(tp, probe, dev, "could not request regions\n");
3109 tp->cp_cmd = RxChkSum;
3111 if ((sizeof(dma_addr_t) > 4) &&
3112 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3113 tp->cp_cmd |= PCIDAC;
3114 dev->features |= NETIF_F_HIGHDMA;
3116 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3118 netif_err(tp, probe, dev, "DMA configuration failed\n");
3119 goto err_out_free_res_3;
3123 /* ioremap MMIO region */
3124 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3126 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3128 goto err_out_free_res_3;
3131 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3133 netif_info(tp, probe, dev, "no PCI Express capability\n");
3135 RTL_W16(IntrMask, 0x0000);
3137 /* Soft reset the chip. */
3138 RTL_W8(ChipCmd, CmdReset);
3140 /* Check that the chip has finished the reset. */
3141 for (i = 0; i < 100; i++) {
3142 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3144 msleep_interruptible(1);
3147 RTL_W16(IntrStatus, 0xffff);
3149 pci_set_master(pdev);
3151 /* Identify chip attached to board */
3152 rtl8169_get_mac_version(tp, ioaddr);
3155 * Pretend we are using VLANs; This bypasses a nasty bug where
3156 * Interrupts stop flowing on high load on 8110SCd controllers.
3158 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3159 tp->cp_cmd |= RxVlan;
3161 rtl_init_mdio_ops(tp);
3162 rtl_init_pll_power_ops(tp);
3164 /* Use appropriate default if unknown */
3165 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3166 netif_notice(tp, probe, dev,
3167 "unknown MAC, using family default\n");
3168 tp->mac_version = cfg->default_ver;
3171 rtl8169_print_mac_version(tp);
3173 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3174 if (tp->mac_version == rtl_chip_info[i].mac_version)
3177 if (i == ARRAY_SIZE(rtl_chip_info)) {
3179 "driver bug, MAC version not found in rtl_chip_info\n");
3184 RTL_W8(Cfg9346, Cfg9346_Unlock);
3185 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3186 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3187 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3188 tp->features |= RTL_FEATURE_WOL;
3189 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3190 tp->features |= RTL_FEATURE_WOL;
3191 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3192 RTL_W8(Cfg9346, Cfg9346_Lock);
3194 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3195 (RTL_R8(PHYstatus) & TBI_Enable)) {
3196 tp->set_speed = rtl8169_set_speed_tbi;
3197 tp->get_settings = rtl8169_gset_tbi;
3198 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3199 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3200 tp->link_ok = rtl8169_tbi_link_ok;
3201 tp->do_ioctl = rtl_tbi_ioctl;
3203 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3205 tp->set_speed = rtl8169_set_speed_xmii;
3206 tp->get_settings = rtl8169_gset_xmii;
3207 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3208 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3209 tp->link_ok = rtl8169_xmii_link_ok;
3210 tp->do_ioctl = rtl_xmii_ioctl;
3213 spin_lock_init(&tp->lock);
3215 tp->mmio_addr = ioaddr;
3217 /* Get MAC address */
3218 for (i = 0; i < MAC_ADDR_LEN; i++)
3219 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3220 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3222 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3223 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3224 dev->irq = pdev->irq;
3225 dev->base_addr = (unsigned long) ioaddr;
3227 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3229 dev->features |= NETIF_F_HW_VLAN_TX_RX | NETIF_F_GRO;
3231 tp->intr_mask = 0xffff;
3232 tp->hw_start = cfg->hw_start;
3233 tp->intr_event = cfg->intr_event;
3234 tp->napi_event = cfg->napi_event;
3236 init_timer(&tp->timer);
3237 tp->timer.data = (unsigned long) dev;
3238 tp->timer.function = rtl8169_phy_timer;
3240 rc = register_netdev(dev);
3244 pci_set_drvdata(pdev, dev);
3246 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3247 rtl_chip_info[tp->chipset].name,
3248 dev->base_addr, dev->dev_addr,
3249 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3251 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3252 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3253 rtl8168_driver_start(tp);
3256 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3258 if (pci_dev_run_wake(pdev))
3259 pm_runtime_put_noidle(&pdev->dev);
3261 netif_carrier_off(dev);
3267 rtl_disable_msi(pdev, tp);
3270 pci_release_regions(pdev);
3272 pci_clear_mwi(pdev);
3273 pci_disable_device(pdev);
3279 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3281 struct net_device *dev = pci_get_drvdata(pdev);
3282 struct rtl8169_private *tp = netdev_priv(dev);
3284 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3285 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3286 rtl8168_driver_stop(tp);
3289 cancel_delayed_work_sync(&tp->task);
3291 rtl_release_firmware(tp);
3293 unregister_netdev(dev);
3295 if (pci_dev_run_wake(pdev))
3296 pm_runtime_get_noresume(&pdev->dev);
3298 /* restore original MAC address */
3299 rtl_rar_set(tp, dev->perm_addr);
3301 rtl_disable_msi(pdev, tp);
3302 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3303 pci_set_drvdata(pdev, NULL);
3306 static int rtl8169_open(struct net_device *dev)
3308 struct rtl8169_private *tp = netdev_priv(dev);
3309 void __iomem *ioaddr = tp->mmio_addr;
3310 struct pci_dev *pdev = tp->pci_dev;
3311 int retval = -ENOMEM;
3313 pm_runtime_get_sync(&pdev->dev);
3316 * Rx and Tx desscriptors needs 256 bytes alignment.
3317 * dma_alloc_coherent provides more.
3319 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3320 &tp->TxPhyAddr, GFP_KERNEL);
3321 if (!tp->TxDescArray)
3322 goto err_pm_runtime_put;
3324 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3325 &tp->RxPhyAddr, GFP_KERNEL);
3326 if (!tp->RxDescArray)
3329 retval = rtl8169_init_ring(dev);
3333 INIT_DELAYED_WORK(&tp->task, NULL);
3337 retval = request_irq(dev->irq, rtl8169_interrupt,
3338 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3341 goto err_release_ring_2;
3343 napi_enable(&tp->napi);
3345 rtl8169_init_phy(dev, tp);
3347 rtl8169_vlan_mode(dev);
3349 rtl_pll_power_up(tp);
3353 rtl8169_request_timer(dev);
3355 tp->saved_wolopts = 0;
3356 pm_runtime_put_noidle(&pdev->dev);
3358 rtl8169_check_link_status(dev, tp, ioaddr);
3363 rtl8169_rx_clear(tp);
3365 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3367 tp->RxDescArray = NULL;
3369 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3371 tp->TxDescArray = NULL;
3373 pm_runtime_put_noidle(&pdev->dev);
3377 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3379 void __iomem *ioaddr = tp->mmio_addr;
3381 /* Disable interrupts */
3382 rtl8169_irq_mask_and_ack(ioaddr);
3384 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3385 tp->mac_version == RTL_GIGA_MAC_VER_28) {
3386 while (RTL_R8(TxPoll) & NPQ)
3391 /* Reset the chipset */
3392 RTL_W8(ChipCmd, CmdReset);
3398 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3400 void __iomem *ioaddr = tp->mmio_addr;
3401 u32 cfg = rtl8169_rx_config;
3403 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3404 RTL_W32(RxConfig, cfg);
3406 /* Set DMA burst size and Interframe Gap Time */
3407 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3408 (InterFrameGap << TxInterFrameGapShift));
3411 static void rtl_hw_start(struct net_device *dev)
3413 struct rtl8169_private *tp = netdev_priv(dev);
3414 void __iomem *ioaddr = tp->mmio_addr;
3417 /* Soft reset the chip. */
3418 RTL_W8(ChipCmd, CmdReset);
3420 /* Check that the chip has finished the reset. */
3421 for (i = 0; i < 100; i++) {
3422 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3424 msleep_interruptible(1);
3429 netif_start_queue(dev);
3433 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3434 void __iomem *ioaddr)
3437 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3438 * register to be written before TxDescAddrLow to work.
3439 * Switching from MMIO to I/O access fixes the issue as well.
3441 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3442 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3443 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3444 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3447 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3451 cmd = RTL_R16(CPlusCmd);
3452 RTL_W16(CPlusCmd, cmd);
3456 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3458 /* Low hurts. Let's disable the filtering. */
3459 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3462 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3464 static const struct {
3469 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3470 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3471 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3472 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3477 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3478 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3479 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3480 RTL_W32(0x7c, p->val);
3486 static void rtl_hw_start_8169(struct net_device *dev)
3488 struct rtl8169_private *tp = netdev_priv(dev);
3489 void __iomem *ioaddr = tp->mmio_addr;
3490 struct pci_dev *pdev = tp->pci_dev;
3492 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3493 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3494 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3497 RTL_W8(Cfg9346, Cfg9346_Unlock);
3498 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3499 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3500 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3501 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3502 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3504 RTL_W8(EarlyTxThres, NoEarlyTx);
3506 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3508 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3509 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3510 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3511 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3512 rtl_set_rx_tx_config_registers(tp);
3514 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3516 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3517 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3518 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3519 "Bit-3 and bit-14 MUST be 1\n");
3520 tp->cp_cmd |= (1 << 14);
3523 RTL_W16(CPlusCmd, tp->cp_cmd);
3525 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3528 * Undocumented corner. Supposedly:
3529 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3531 RTL_W16(IntrMitigate, 0x0000);
3533 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3535 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3536 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3537 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3538 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3539 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3540 rtl_set_rx_tx_config_registers(tp);
3543 RTL_W8(Cfg9346, Cfg9346_Lock);
3545 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3548 RTL_W32(RxMissed, 0);
3550 rtl_set_rx_mode(dev);
3552 /* no early-rx interrupts */
3553 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3555 /* Enable all known interrupts by setting the interrupt mask. */
3556 RTL_W16(IntrMask, tp->intr_event);
3559 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3561 struct net_device *dev = pci_get_drvdata(pdev);
3562 struct rtl8169_private *tp = netdev_priv(dev);
3563 int cap = tp->pcie_cap;
3568 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3569 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3570 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3574 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3578 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3579 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3582 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3584 rtl_csi_access_enable(ioaddr, 0x17000000);
3587 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3589 rtl_csi_access_enable(ioaddr, 0x27000000);
3593 unsigned int offset;
3598 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3603 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3604 rtl_ephy_write(ioaddr, e->offset, w);
3609 static void rtl_disable_clock_request(struct pci_dev *pdev)
3611 struct net_device *dev = pci_get_drvdata(pdev);
3612 struct rtl8169_private *tp = netdev_priv(dev);
3613 int cap = tp->pcie_cap;
3618 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3619 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3620 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3624 static void rtl_enable_clock_request(struct pci_dev *pdev)
3626 struct net_device *dev = pci_get_drvdata(pdev);
3627 struct rtl8169_private *tp = netdev_priv(dev);
3628 int cap = tp->pcie_cap;
3633 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3634 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3635 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3639 #define R8168_CPCMD_QUIRK_MASK (\
3650 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3652 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3654 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3656 rtl_tx_performance_tweak(pdev,
3657 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3660 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3662 rtl_hw_start_8168bb(ioaddr, pdev);
3664 RTL_W8(MaxTxPacketSize, TxPacketMax);
3666 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3669 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3671 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3673 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3675 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3677 rtl_disable_clock_request(pdev);
3679 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3682 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3684 static const struct ephy_info e_info_8168cp[] = {
3685 { 0x01, 0, 0x0001 },
3686 { 0x02, 0x0800, 0x1000 },
3687 { 0x03, 0, 0x0042 },
3688 { 0x06, 0x0080, 0x0000 },
3692 rtl_csi_access_enable_2(ioaddr);
3694 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3696 __rtl_hw_start_8168cp(ioaddr, pdev);
3699 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3701 rtl_csi_access_enable_2(ioaddr);
3703 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3705 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3707 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3710 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3712 rtl_csi_access_enable_2(ioaddr);
3714 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3717 RTL_W8(DBG_REG, 0x20);
3719 RTL_W8(MaxTxPacketSize, TxPacketMax);
3721 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3723 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3726 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3728 static const struct ephy_info e_info_8168c_1[] = {
3729 { 0x02, 0x0800, 0x1000 },
3730 { 0x03, 0, 0x0002 },
3731 { 0x06, 0x0080, 0x0000 }
3734 rtl_csi_access_enable_2(ioaddr);
3736 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3738 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3740 __rtl_hw_start_8168cp(ioaddr, pdev);
3743 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3745 static const struct ephy_info e_info_8168c_2[] = {
3746 { 0x01, 0, 0x0001 },
3747 { 0x03, 0x0400, 0x0220 }
3750 rtl_csi_access_enable_2(ioaddr);
3752 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3754 __rtl_hw_start_8168cp(ioaddr, pdev);
3757 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3759 rtl_hw_start_8168c_2(ioaddr, pdev);
3762 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3764 rtl_csi_access_enable_2(ioaddr);
3766 __rtl_hw_start_8168cp(ioaddr, pdev);
3769 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3771 rtl_csi_access_enable_2(ioaddr);
3773 rtl_disable_clock_request(pdev);
3775 RTL_W8(MaxTxPacketSize, TxPacketMax);
3777 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3779 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3782 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3784 static const struct ephy_info e_info_8168d_4[] = {
3786 { 0x19, 0x20, 0x50 },
3791 rtl_csi_access_enable_1(ioaddr);
3793 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3795 RTL_W8(MaxTxPacketSize, TxPacketMax);
3797 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3798 const struct ephy_info *e = e_info_8168d_4 + i;
3801 w = rtl_ephy_read(ioaddr, e->offset);
3802 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3805 rtl_enable_clock_request(pdev);
3808 static void rtl_hw_start_8168(struct net_device *dev)
3810 struct rtl8169_private *tp = netdev_priv(dev);
3811 void __iomem *ioaddr = tp->mmio_addr;
3812 struct pci_dev *pdev = tp->pci_dev;
3814 RTL_W8(Cfg9346, Cfg9346_Unlock);
3816 RTL_W8(MaxTxPacketSize, TxPacketMax);
3818 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3820 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3822 RTL_W16(CPlusCmd, tp->cp_cmd);
3824 RTL_W16(IntrMitigate, 0x5151);
3826 /* Work around for RxFIFO overflow. */
3827 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3828 tp->mac_version == RTL_GIGA_MAC_VER_22) {
3829 tp->intr_event |= RxFIFOOver | PCSTimeout;
3830 tp->intr_event &= ~RxOverflow;
3833 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3835 rtl_set_rx_mode(dev);
3837 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3838 (InterFrameGap << TxInterFrameGapShift));
3842 switch (tp->mac_version) {
3843 case RTL_GIGA_MAC_VER_11:
3844 rtl_hw_start_8168bb(ioaddr, pdev);
3847 case RTL_GIGA_MAC_VER_12:
3848 case RTL_GIGA_MAC_VER_17:
3849 rtl_hw_start_8168bef(ioaddr, pdev);
3852 case RTL_GIGA_MAC_VER_18:
3853 rtl_hw_start_8168cp_1(ioaddr, pdev);
3856 case RTL_GIGA_MAC_VER_19:
3857 rtl_hw_start_8168c_1(ioaddr, pdev);
3860 case RTL_GIGA_MAC_VER_20:
3861 rtl_hw_start_8168c_2(ioaddr, pdev);
3864 case RTL_GIGA_MAC_VER_21:
3865 rtl_hw_start_8168c_3(ioaddr, pdev);
3868 case RTL_GIGA_MAC_VER_22:
3869 rtl_hw_start_8168c_4(ioaddr, pdev);
3872 case RTL_GIGA_MAC_VER_23:
3873 rtl_hw_start_8168cp_2(ioaddr, pdev);
3876 case RTL_GIGA_MAC_VER_24:
3877 rtl_hw_start_8168cp_3(ioaddr, pdev);
3880 case RTL_GIGA_MAC_VER_25:
3881 case RTL_GIGA_MAC_VER_26:
3882 case RTL_GIGA_MAC_VER_27:
3883 rtl_hw_start_8168d(ioaddr, pdev);
3886 case RTL_GIGA_MAC_VER_28:
3887 rtl_hw_start_8168d_4(ioaddr, pdev);
3891 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3892 dev->name, tp->mac_version);
3896 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3898 RTL_W8(Cfg9346, Cfg9346_Lock);
3900 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3902 RTL_W16(IntrMask, tp->intr_event);
3905 #define R810X_CPCMD_QUIRK_MASK (\
3916 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3918 static const struct ephy_info e_info_8102e_1[] = {
3919 { 0x01, 0, 0x6e65 },
3920 { 0x02, 0, 0x091f },
3921 { 0x03, 0, 0xc2f9 },
3922 { 0x06, 0, 0xafb5 },
3923 { 0x07, 0, 0x0e00 },
3924 { 0x19, 0, 0xec80 },
3925 { 0x01, 0, 0x2e65 },
3930 rtl_csi_access_enable_2(ioaddr);
3932 RTL_W8(DBG_REG, FIX_NAK_1);
3934 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3937 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3938 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3940 cfg1 = RTL_R8(Config1);
3941 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3942 RTL_W8(Config1, cfg1 & ~LEDS0);
3944 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3947 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3949 rtl_csi_access_enable_2(ioaddr);
3951 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3953 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3954 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3957 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3959 rtl_hw_start_8102e_2(ioaddr, pdev);
3961 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3964 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3966 static const struct ephy_info e_info_8105e_1[] = {
3967 { 0x07, 0, 0x4000 },
3968 { 0x19, 0, 0x0200 },
3969 { 0x19, 0, 0x0020 },
3970 { 0x1e, 0, 0x2000 },
3971 { 0x03, 0, 0x0001 },
3972 { 0x19, 0, 0x0100 },
3973 { 0x19, 0, 0x0004 },
3977 /* Force LAN exit from ASPM if Rx/Tx are not idel */
3978 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
3980 /* disable Early Tally Counter */
3981 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
3983 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
3984 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
3986 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
3989 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3991 rtl_hw_start_8105e_1(ioaddr, pdev);
3992 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
3995 static void rtl_hw_start_8101(struct net_device *dev)
3997 struct rtl8169_private *tp = netdev_priv(dev);
3998 void __iomem *ioaddr = tp->mmio_addr;
3999 struct pci_dev *pdev = tp->pci_dev;
4001 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4002 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
4003 int cap = tp->pcie_cap;
4006 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4007 PCI_EXP_DEVCTL_NOSNOOP_EN);
4011 RTL_W8(Cfg9346, Cfg9346_Unlock);
4013 switch (tp->mac_version) {
4014 case RTL_GIGA_MAC_VER_07:
4015 rtl_hw_start_8102e_1(ioaddr, pdev);
4018 case RTL_GIGA_MAC_VER_08:
4019 rtl_hw_start_8102e_3(ioaddr, pdev);
4022 case RTL_GIGA_MAC_VER_09:
4023 rtl_hw_start_8102e_2(ioaddr, pdev);
4026 case RTL_GIGA_MAC_VER_29:
4027 rtl_hw_start_8105e_1(ioaddr, pdev);
4029 case RTL_GIGA_MAC_VER_30:
4030 rtl_hw_start_8105e_2(ioaddr, pdev);
4034 RTL_W8(Cfg9346, Cfg9346_Lock);
4036 RTL_W8(MaxTxPacketSize, TxPacketMax);
4038 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4040 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4041 RTL_W16(CPlusCmd, tp->cp_cmd);
4043 RTL_W16(IntrMitigate, 0x0000);
4045 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4047 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4048 rtl_set_rx_tx_config_registers(tp);
4052 rtl_set_rx_mode(dev);
4054 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4056 RTL_W16(IntrMask, tp->intr_event);
4059 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4061 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4068 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4070 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4071 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4074 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4075 void **data_buff, struct RxDesc *desc)
4077 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4082 rtl8169_make_unusable_by_asic(desc);
4085 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4087 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4089 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4092 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4095 desc->addr = cpu_to_le64(mapping);
4097 rtl8169_mark_to_asic(desc, rx_buf_sz);
4100 static inline void *rtl8169_align(void *data)
4102 return (void *)ALIGN((long)data, 16);
4105 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4106 struct RxDesc *desc)
4110 struct device *d = &tp->pci_dev->dev;
4111 struct net_device *dev = tp->dev;
4112 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4114 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4118 if (rtl8169_align(data) != data) {
4120 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4125 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4127 if (unlikely(dma_mapping_error(d, mapping))) {
4128 if (net_ratelimit())
4129 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4133 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4141 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4145 for (i = 0; i < NUM_RX_DESC; i++) {
4146 if (tp->Rx_databuff[i]) {
4147 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4148 tp->RxDescArray + i);
4153 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4155 desc->opts1 |= cpu_to_le32(RingEnd);
4158 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4162 for (i = 0; i < NUM_RX_DESC; i++) {
4165 if (tp->Rx_databuff[i])
4168 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4170 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4173 tp->Rx_databuff[i] = data;
4176 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4180 rtl8169_rx_clear(tp);
4184 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4186 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4189 static int rtl8169_init_ring(struct net_device *dev)
4191 struct rtl8169_private *tp = netdev_priv(dev);
4193 rtl8169_init_ring_indexes(tp);
4195 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4196 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4198 return rtl8169_rx_fill(tp);
4201 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4202 struct TxDesc *desc)
4204 unsigned int len = tx_skb->len;
4206 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4214 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4219 for (i = 0; i < n; i++) {
4220 unsigned int entry = (start + i) % NUM_TX_DESC;
4221 struct ring_info *tx_skb = tp->tx_skb + entry;
4222 unsigned int len = tx_skb->len;
4225 struct sk_buff *skb = tx_skb->skb;
4227 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4228 tp->TxDescArray + entry);
4230 tp->dev->stats.tx_dropped++;
4238 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4240 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4241 tp->cur_tx = tp->dirty_tx = 0;
4244 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4246 struct rtl8169_private *tp = netdev_priv(dev);
4248 PREPARE_DELAYED_WORK(&tp->task, task);
4249 schedule_delayed_work(&tp->task, 4);
4252 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4254 struct rtl8169_private *tp = netdev_priv(dev);
4255 void __iomem *ioaddr = tp->mmio_addr;
4257 synchronize_irq(dev->irq);
4259 /* Wait for any pending NAPI task to complete */
4260 napi_disable(&tp->napi);
4262 rtl8169_irq_mask_and_ack(ioaddr);
4264 tp->intr_mask = 0xffff;
4265 RTL_W16(IntrMask, tp->intr_event);
4266 napi_enable(&tp->napi);
4269 static void rtl8169_reinit_task(struct work_struct *work)
4271 struct rtl8169_private *tp =
4272 container_of(work, struct rtl8169_private, task.work);
4273 struct net_device *dev = tp->dev;
4278 if (!netif_running(dev))
4281 rtl8169_wait_for_quiescence(dev);
4284 ret = rtl8169_open(dev);
4285 if (unlikely(ret < 0)) {
4286 if (net_ratelimit())
4287 netif_err(tp, drv, dev,
4288 "reinit failure (status = %d). Rescheduling\n",
4290 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4297 static void rtl8169_reset_task(struct work_struct *work)
4299 struct rtl8169_private *tp =
4300 container_of(work, struct rtl8169_private, task.work);
4301 struct net_device *dev = tp->dev;
4305 if (!netif_running(dev))
4308 rtl8169_wait_for_quiescence(dev);
4310 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4311 rtl8169_tx_clear(tp);
4313 if (tp->dirty_rx == tp->cur_rx) {
4314 rtl8169_init_ring_indexes(tp);
4316 netif_wake_queue(dev);
4317 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4319 if (net_ratelimit())
4320 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4321 rtl8169_schedule_work(dev, rtl8169_reset_task);
4328 static void rtl8169_tx_timeout(struct net_device *dev)
4330 struct rtl8169_private *tp = netdev_priv(dev);
4332 rtl8169_hw_reset(tp);
4334 /* Let's wait a bit while any (async) irq lands on */
4335 rtl8169_schedule_work(dev, rtl8169_reset_task);
4338 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4341 struct skb_shared_info *info = skb_shinfo(skb);
4342 unsigned int cur_frag, entry;
4343 struct TxDesc * uninitialized_var(txd);
4344 struct device *d = &tp->pci_dev->dev;
4347 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4348 skb_frag_t *frag = info->frags + cur_frag;
4353 entry = (entry + 1) % NUM_TX_DESC;
4355 txd = tp->TxDescArray + entry;
4357 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4358 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4359 if (unlikely(dma_mapping_error(d, mapping))) {
4360 if (net_ratelimit())
4361 netif_err(tp, drv, tp->dev,
4362 "Failed to map TX fragments DMA!\n");
4366 /* anti gcc 2.95.3 bugware (sic) */
4367 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4369 txd->opts1 = cpu_to_le32(status);
4370 txd->addr = cpu_to_le64(mapping);
4372 tp->tx_skb[entry].len = len;
4376 tp->tx_skb[entry].skb = skb;
4377 txd->opts1 |= cpu_to_le32(LastFrag);
4383 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4387 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4389 if (dev->features & NETIF_F_TSO) {
4390 u32 mss = skb_shinfo(skb)->gso_size;
4393 return LargeSend | ((mss & MSSMask) << MSSShift);
4395 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4396 const struct iphdr *ip = ip_hdr(skb);
4398 if (ip->protocol == IPPROTO_TCP)
4399 return IPCS | TCPCS;
4400 else if (ip->protocol == IPPROTO_UDP)
4401 return IPCS | UDPCS;
4402 WARN_ON(1); /* we need a WARN() */
4407 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4408 struct net_device *dev)
4410 struct rtl8169_private *tp = netdev_priv(dev);
4411 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4412 struct TxDesc *txd = tp->TxDescArray + entry;
4413 void __iomem *ioaddr = tp->mmio_addr;
4414 struct device *d = &tp->pci_dev->dev;
4420 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4421 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4425 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4428 len = skb_headlen(skb);
4429 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4430 if (unlikely(dma_mapping_error(d, mapping))) {
4431 if (net_ratelimit())
4432 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4436 tp->tx_skb[entry].len = len;
4437 txd->addr = cpu_to_le64(mapping);
4438 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4440 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4442 frags = rtl8169_xmit_frags(tp, skb, opts1);
4448 opts1 |= FirstFrag | LastFrag;
4449 tp->tx_skb[entry].skb = skb;
4454 /* anti gcc 2.95.3 bugware (sic) */
4455 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4456 txd->opts1 = cpu_to_le32(status);
4458 tp->cur_tx += frags + 1;
4462 RTL_W8(TxPoll, NPQ); /* set polling bit */
4464 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4465 netif_stop_queue(dev);
4467 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4468 netif_wake_queue(dev);
4471 return NETDEV_TX_OK;
4474 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4477 dev->stats.tx_dropped++;
4478 return NETDEV_TX_OK;
4481 netif_stop_queue(dev);
4482 dev->stats.tx_dropped++;
4483 return NETDEV_TX_BUSY;
4486 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4488 struct rtl8169_private *tp = netdev_priv(dev);
4489 struct pci_dev *pdev = tp->pci_dev;
4490 u16 pci_status, pci_cmd;
4492 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4493 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4495 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4496 pci_cmd, pci_status);
4499 * The recovery sequence below admits a very elaborated explanation:
4500 * - it seems to work;
4501 * - I did not see what else could be done;
4502 * - it makes iop3xx happy.
4504 * Feel free to adjust to your needs.
4506 if (pdev->broken_parity_status)
4507 pci_cmd &= ~PCI_COMMAND_PARITY;
4509 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4511 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4513 pci_write_config_word(pdev, PCI_STATUS,
4514 pci_status & (PCI_STATUS_DETECTED_PARITY |
4515 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4516 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4518 /* The infamous DAC f*ckup only happens at boot time */
4519 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4520 void __iomem *ioaddr = tp->mmio_addr;
4522 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4523 tp->cp_cmd &= ~PCIDAC;
4524 RTL_W16(CPlusCmd, tp->cp_cmd);
4525 dev->features &= ~NETIF_F_HIGHDMA;
4528 rtl8169_hw_reset(tp);
4530 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4533 static void rtl8169_tx_interrupt(struct net_device *dev,
4534 struct rtl8169_private *tp,
4535 void __iomem *ioaddr)
4537 unsigned int dirty_tx, tx_left;
4539 dirty_tx = tp->dirty_tx;
4541 tx_left = tp->cur_tx - dirty_tx;
4543 while (tx_left > 0) {
4544 unsigned int entry = dirty_tx % NUM_TX_DESC;
4545 struct ring_info *tx_skb = tp->tx_skb + entry;
4549 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4550 if (status & DescOwn)
4553 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4554 tp->TxDescArray + entry);
4555 if (status & LastFrag) {
4556 dev->stats.tx_packets++;
4557 dev->stats.tx_bytes += tx_skb->skb->len;
4558 dev_kfree_skb(tx_skb->skb);
4565 if (tp->dirty_tx != dirty_tx) {
4566 tp->dirty_tx = dirty_tx;
4568 if (netif_queue_stopped(dev) &&
4569 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4570 netif_wake_queue(dev);
4573 * 8168 hack: TxPoll requests are lost when the Tx packets are
4574 * too close. Let's kick an extra TxPoll request when a burst
4575 * of start_xmit activity is detected (if it is not detected,
4576 * it is slow enough). -- FR
4579 if (tp->cur_tx != dirty_tx)
4580 RTL_W8(TxPoll, NPQ);
4584 static inline int rtl8169_fragmented_frame(u32 status)
4586 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4589 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4591 u32 status = opts1 & RxProtoMask;
4593 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4594 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4595 skb->ip_summed = CHECKSUM_UNNECESSARY;
4597 skb_checksum_none_assert(skb);
4600 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4601 struct rtl8169_private *tp,
4605 struct sk_buff *skb;
4606 struct device *d = &tp->pci_dev->dev;
4608 data = rtl8169_align(data);
4609 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4611 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4613 memcpy(skb->data, data, pkt_size);
4614 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4620 * Warning : rtl8169_rx_interrupt() might be called :
4621 * 1) from NAPI (softirq) context
4622 * (polling = 1 : we should call netif_receive_skb())
4623 * 2) from process context (rtl8169_reset_task())
4624 * (polling = 0 : we must call netif_rx() instead)
4626 static int rtl8169_rx_interrupt(struct net_device *dev,
4627 struct rtl8169_private *tp,
4628 void __iomem *ioaddr, u32 budget)
4630 unsigned int cur_rx, rx_left;
4632 int polling = (budget != ~(u32)0) ? 1 : 0;
4634 cur_rx = tp->cur_rx;
4635 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4636 rx_left = min(rx_left, budget);
4638 for (; rx_left > 0; rx_left--, cur_rx++) {
4639 unsigned int entry = cur_rx % NUM_RX_DESC;
4640 struct RxDesc *desc = tp->RxDescArray + entry;
4644 status = le32_to_cpu(desc->opts1);
4646 if (status & DescOwn)
4648 if (unlikely(status & RxRES)) {
4649 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4651 dev->stats.rx_errors++;
4652 if (status & (RxRWT | RxRUNT))
4653 dev->stats.rx_length_errors++;
4655 dev->stats.rx_crc_errors++;
4656 if (status & RxFOVF) {
4657 rtl8169_schedule_work(dev, rtl8169_reset_task);
4658 dev->stats.rx_fifo_errors++;
4660 rtl8169_mark_to_asic(desc, rx_buf_sz);
4662 struct sk_buff *skb;
4663 dma_addr_t addr = le64_to_cpu(desc->addr);
4664 int pkt_size = (status & 0x00001FFF) - 4;
4667 * The driver does not support incoming fragmented
4668 * frames. They are seen as a symptom of over-mtu
4671 if (unlikely(rtl8169_fragmented_frame(status))) {
4672 dev->stats.rx_dropped++;
4673 dev->stats.rx_length_errors++;
4674 rtl8169_mark_to_asic(desc, rx_buf_sz);
4678 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4679 tp, pkt_size, addr);
4680 rtl8169_mark_to_asic(desc, rx_buf_sz);
4682 dev->stats.rx_dropped++;
4686 rtl8169_rx_csum(skb, status);
4687 skb_put(skb, pkt_size);
4688 skb->protocol = eth_type_trans(skb, dev);
4690 rtl8169_rx_vlan_tag(desc, skb);
4692 if (likely(polling))
4693 napi_gro_receive(&tp->napi, skb);
4697 dev->stats.rx_bytes += pkt_size;
4698 dev->stats.rx_packets++;
4701 /* Work around for AMD plateform. */
4702 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4703 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4709 count = cur_rx - tp->cur_rx;
4710 tp->cur_rx = cur_rx;
4712 tp->dirty_rx += count;
4717 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4719 struct net_device *dev = dev_instance;
4720 struct rtl8169_private *tp = netdev_priv(dev);
4721 void __iomem *ioaddr = tp->mmio_addr;
4725 /* loop handling interrupts until we have no new ones or
4726 * we hit a invalid/hotplug case.
4728 status = RTL_R16(IntrStatus);
4729 while (status && status != 0xffff) {
4732 /* Handle all of the error cases first. These will reset
4733 * the chip, so just exit the loop.
4735 if (unlikely(!netif_running(dev))) {
4736 rtl8169_asic_down(ioaddr);
4740 if (unlikely(status & RxFIFOOver)) {
4741 switch (tp->mac_version) {
4742 /* Work around for rx fifo overflow */
4743 case RTL_GIGA_MAC_VER_11:
4744 case RTL_GIGA_MAC_VER_22:
4745 case RTL_GIGA_MAC_VER_26:
4746 netif_stop_queue(dev);
4747 rtl8169_tx_timeout(dev);
4749 /* Testers needed. */
4750 case RTL_GIGA_MAC_VER_17:
4751 case RTL_GIGA_MAC_VER_19:
4752 case RTL_GIGA_MAC_VER_20:
4753 case RTL_GIGA_MAC_VER_21:
4754 case RTL_GIGA_MAC_VER_23:
4755 case RTL_GIGA_MAC_VER_24:
4756 case RTL_GIGA_MAC_VER_27:
4757 case RTL_GIGA_MAC_VER_28:
4758 /* Experimental science. Pktgen proof. */
4759 case RTL_GIGA_MAC_VER_12:
4760 case RTL_GIGA_MAC_VER_25:
4761 if (status == RxFIFOOver)
4769 if (unlikely(status & SYSErr)) {
4770 rtl8169_pcierr_interrupt(dev);
4774 if (status & LinkChg)
4775 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4777 /* We need to see the lastest version of tp->intr_mask to
4778 * avoid ignoring an MSI interrupt and having to wait for
4779 * another event which may never come.
4782 if (status & tp->intr_mask & tp->napi_event) {
4783 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4784 tp->intr_mask = ~tp->napi_event;
4786 if (likely(napi_schedule_prep(&tp->napi)))
4787 __napi_schedule(&tp->napi);
4789 netif_info(tp, intr, dev,
4790 "interrupt %04x in poll\n", status);
4793 /* We only get a new MSI interrupt when all active irq
4794 * sources on the chip have been acknowledged. So, ack
4795 * everything we've seen and check if new sources have become
4796 * active to avoid blocking all interrupts from the chip.
4799 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4800 status = RTL_R16(IntrStatus);
4803 return IRQ_RETVAL(handled);
4806 static int rtl8169_poll(struct napi_struct *napi, int budget)
4808 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4809 struct net_device *dev = tp->dev;
4810 void __iomem *ioaddr = tp->mmio_addr;
4813 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4814 rtl8169_tx_interrupt(dev, tp, ioaddr);
4816 if (work_done < budget) {
4817 napi_complete(napi);
4819 /* We need for force the visibility of tp->intr_mask
4820 * for other CPUs, as we can loose an MSI interrupt
4821 * and potentially wait for a retransmit timeout if we don't.
4822 * The posted write to IntrMask is safe, as it will
4823 * eventually make it to the chip and we won't loose anything
4826 tp->intr_mask = 0xffff;
4828 RTL_W16(IntrMask, tp->intr_event);
4834 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4836 struct rtl8169_private *tp = netdev_priv(dev);
4838 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4841 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4842 RTL_W32(RxMissed, 0);
4845 static void rtl8169_down(struct net_device *dev)
4847 struct rtl8169_private *tp = netdev_priv(dev);
4848 void __iomem *ioaddr = tp->mmio_addr;
4850 rtl8169_delete_timer(dev);
4852 netif_stop_queue(dev);
4854 napi_disable(&tp->napi);
4856 spin_lock_irq(&tp->lock);
4858 rtl8169_asic_down(ioaddr);
4860 * At this point device interrupts can not be enabled in any function,
4861 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4862 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4864 rtl8169_rx_missed(dev, ioaddr);
4866 spin_unlock_irq(&tp->lock);
4868 synchronize_irq(dev->irq);
4870 /* Give a racing hard_start_xmit a few cycles to complete. */
4871 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4873 rtl8169_tx_clear(tp);
4875 rtl8169_rx_clear(tp);
4877 rtl_pll_power_down(tp);
4880 static int rtl8169_close(struct net_device *dev)
4882 struct rtl8169_private *tp = netdev_priv(dev);
4883 struct pci_dev *pdev = tp->pci_dev;
4885 pm_runtime_get_sync(&pdev->dev);
4887 /* update counters before going down */
4888 rtl8169_update_counters(dev);
4892 free_irq(dev->irq, dev);
4894 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4896 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4898 tp->TxDescArray = NULL;
4899 tp->RxDescArray = NULL;
4901 pm_runtime_put_sync(&pdev->dev);
4906 static void rtl_set_rx_mode(struct net_device *dev)
4908 struct rtl8169_private *tp = netdev_priv(dev);
4909 void __iomem *ioaddr = tp->mmio_addr;
4910 unsigned long flags;
4911 u32 mc_filter[2]; /* Multicast hash filter */
4915 if (dev->flags & IFF_PROMISC) {
4916 /* Unconditionally log net taps. */
4917 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4919 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4921 mc_filter[1] = mc_filter[0] = 0xffffffff;
4922 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4923 (dev->flags & IFF_ALLMULTI)) {
4924 /* Too many to filter perfectly -- accept all multicasts. */
4925 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4926 mc_filter[1] = mc_filter[0] = 0xffffffff;
4928 struct netdev_hw_addr *ha;
4930 rx_mode = AcceptBroadcast | AcceptMyPhys;
4931 mc_filter[1] = mc_filter[0] = 0;
4932 netdev_for_each_mc_addr(ha, dev) {
4933 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4934 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4935 rx_mode |= AcceptMulticast;
4939 spin_lock_irqsave(&tp->lock, flags);
4941 tmp = rtl8169_rx_config | rx_mode |
4942 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4944 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4945 u32 data = mc_filter[0];
4947 mc_filter[0] = swab32(mc_filter[1]);
4948 mc_filter[1] = swab32(data);
4951 RTL_W32(MAR0 + 4, mc_filter[1]);
4952 RTL_W32(MAR0 + 0, mc_filter[0]);
4954 RTL_W32(RxConfig, tmp);
4956 spin_unlock_irqrestore(&tp->lock, flags);
4960 * rtl8169_get_stats - Get rtl8169 read/write statistics
4961 * @dev: The Ethernet Device to get statistics for
4963 * Get TX/RX statistics for rtl8169
4965 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4967 struct rtl8169_private *tp = netdev_priv(dev);
4968 void __iomem *ioaddr = tp->mmio_addr;
4969 unsigned long flags;
4971 if (netif_running(dev)) {
4972 spin_lock_irqsave(&tp->lock, flags);
4973 rtl8169_rx_missed(dev, ioaddr);
4974 spin_unlock_irqrestore(&tp->lock, flags);
4980 static void rtl8169_net_suspend(struct net_device *dev)
4982 struct rtl8169_private *tp = netdev_priv(dev);
4984 if (!netif_running(dev))
4987 rtl_pll_power_down(tp);
4989 netif_device_detach(dev);
4990 netif_stop_queue(dev);
4995 static int rtl8169_suspend(struct device *device)
4997 struct pci_dev *pdev = to_pci_dev(device);
4998 struct net_device *dev = pci_get_drvdata(pdev);
5000 rtl8169_net_suspend(dev);
5005 static void __rtl8169_resume(struct net_device *dev)
5007 struct rtl8169_private *tp = netdev_priv(dev);
5009 netif_device_attach(dev);
5011 rtl_pll_power_up(tp);
5013 rtl8169_schedule_work(dev, rtl8169_reset_task);
5016 static int rtl8169_resume(struct device *device)
5018 struct pci_dev *pdev = to_pci_dev(device);
5019 struct net_device *dev = pci_get_drvdata(pdev);
5020 struct rtl8169_private *tp = netdev_priv(dev);
5022 rtl8169_init_phy(dev, tp);
5024 if (netif_running(dev))
5025 __rtl8169_resume(dev);
5030 static int rtl8169_runtime_suspend(struct device *device)
5032 struct pci_dev *pdev = to_pci_dev(device);
5033 struct net_device *dev = pci_get_drvdata(pdev);
5034 struct rtl8169_private *tp = netdev_priv(dev);
5036 if (!tp->TxDescArray)
5039 spin_lock_irq(&tp->lock);
5040 tp->saved_wolopts = __rtl8169_get_wol(tp);
5041 __rtl8169_set_wol(tp, WAKE_ANY);
5042 spin_unlock_irq(&tp->lock);
5044 rtl8169_net_suspend(dev);
5049 static int rtl8169_runtime_resume(struct device *device)
5051 struct pci_dev *pdev = to_pci_dev(device);
5052 struct net_device *dev = pci_get_drvdata(pdev);
5053 struct rtl8169_private *tp = netdev_priv(dev);
5055 if (!tp->TxDescArray)
5058 spin_lock_irq(&tp->lock);
5059 __rtl8169_set_wol(tp, tp->saved_wolopts);
5060 tp->saved_wolopts = 0;
5061 spin_unlock_irq(&tp->lock);
5063 rtl8169_init_phy(dev, tp);
5065 __rtl8169_resume(dev);
5070 static int rtl8169_runtime_idle(struct device *device)
5072 struct pci_dev *pdev = to_pci_dev(device);
5073 struct net_device *dev = pci_get_drvdata(pdev);
5074 struct rtl8169_private *tp = netdev_priv(dev);
5076 return tp->TxDescArray ? -EBUSY : 0;
5079 static const struct dev_pm_ops rtl8169_pm_ops = {
5080 .suspend = rtl8169_suspend,
5081 .resume = rtl8169_resume,
5082 .freeze = rtl8169_suspend,
5083 .thaw = rtl8169_resume,
5084 .poweroff = rtl8169_suspend,
5085 .restore = rtl8169_resume,
5086 .runtime_suspend = rtl8169_runtime_suspend,
5087 .runtime_resume = rtl8169_runtime_resume,
5088 .runtime_idle = rtl8169_runtime_idle,
5091 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5093 #else /* !CONFIG_PM */
5095 #define RTL8169_PM_OPS NULL
5097 #endif /* !CONFIG_PM */
5099 static void rtl_shutdown(struct pci_dev *pdev)
5101 struct net_device *dev = pci_get_drvdata(pdev);
5102 struct rtl8169_private *tp = netdev_priv(dev);
5103 void __iomem *ioaddr = tp->mmio_addr;
5105 rtl8169_net_suspend(dev);
5107 /* restore original MAC address */
5108 rtl_rar_set(tp, dev->perm_addr);
5110 spin_lock_irq(&tp->lock);
5112 rtl8169_asic_down(ioaddr);
5114 spin_unlock_irq(&tp->lock);
5116 if (system_state == SYSTEM_POWER_OFF) {
5117 /* WoL fails with some 8168 when the receiver is disabled. */
5118 if (tp->features & RTL_FEATURE_WOL) {
5119 pci_clear_master(pdev);
5121 RTL_W8(ChipCmd, CmdRxEnb);
5126 pci_wake_from_d3(pdev, true);
5127 pci_set_power_state(pdev, PCI_D3hot);
5131 static struct pci_driver rtl8169_pci_driver = {
5133 .id_table = rtl8169_pci_tbl,
5134 .probe = rtl8169_init_one,
5135 .remove = __devexit_p(rtl8169_remove_one),
5136 .shutdown = rtl_shutdown,
5137 .driver.pm = RTL8169_PM_OPS,
5140 static int __init rtl8169_init_module(void)
5142 return pci_register_driver(&rtl8169_pci_driver);
5145 static void __exit rtl8169_cleanup_module(void)
5147 pci_unregister_driver(&rtl8169_pci_driver);
5150 module_init(rtl8169_init_module);
5151 module_exit(rtl8169_cleanup_module);