1 // SPDX-License-Identifier: GPL-2.0+
3 * QE UEC ethernet controller driver
5 * based on drivers/qe/uec.c from NXP
7 * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
17 #include "dm_qe_uec.h"
19 #define QE_UEC_DRIVER_NAME "ucc_geth"
21 /* Default UTBIPAR SMI address */
22 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
23 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
26 static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
31 uec_regs = uec->uec_regs;
32 maccfg1 = in_be32(&uec_regs->maccfg1);
34 if (mode & COMM_DIR_TX) {
35 maccfg1 |= MACCFG1_ENABLE_TX;
36 out_be32(&uec_regs->maccfg1, maccfg1);
37 uec->mac_tx_enabled = 1;
40 if (mode & COMM_DIR_RX) {
41 maccfg1 |= MACCFG1_ENABLE_RX;
42 out_be32(&uec_regs->maccfg1, maccfg1);
43 uec->mac_rx_enabled = 1;
49 static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode)
54 uec_regs = uec->uec_regs;
55 maccfg1 = in_be32(&uec_regs->maccfg1);
57 if (mode & COMM_DIR_TX) {
58 maccfg1 &= ~MACCFG1_ENABLE_TX;
59 out_be32(&uec_regs->maccfg1, maccfg1);
60 uec->mac_tx_enabled = 0;
63 if (mode & COMM_DIR_RX) {
64 maccfg1 &= ~MACCFG1_ENABLE_RX;
65 out_be32(&uec_regs->maccfg1, maccfg1);
66 uec->mac_rx_enabled = 0;
72 static int uec_restart_tx(struct uec_priv *uec)
74 struct uec_inf *ui = uec->uec_info;
77 cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num);
78 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
79 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
81 uec->grace_stopped_tx = 0;
86 static int uec_restart_rx(struct uec_priv *uec)
88 struct uec_inf *ui = uec->uec_info;
91 cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num);
92 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
93 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
95 uec->grace_stopped_rx = 0;
100 static int uec_open(struct uec_priv *uec, comm_dir_e mode)
102 struct ucc_fast_priv *uccf;
106 /* check if the UCC number is in range. */
107 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
108 printf("%s: ucc_num out of range.\n", __func__);
113 uec_mac_enable(uec, mode);
115 /* Enable UCC fast */
116 ucc_fast_enable(uccf, mode);
118 /* RISC microcode start */
119 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx)
122 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx)
128 static int uec_set_mac_if_mode(struct uec_priv *uec)
130 struct uec_inf *uec_info = uec->uec_info;
131 phy_interface_t enet_if_mode;
136 uec_regs = uec->uec_regs;
137 enet_if_mode = uec_info->enet_interface_type;
139 maccfg2 = in_be32(&uec_regs->maccfg2);
140 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
142 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
143 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
145 switch (uec_info->speed) {
147 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
148 switch (enet_if_mode) {
149 case PHY_INTERFACE_MODE_MII:
151 case PHY_INTERFACE_MODE_RGMII:
152 upsmr |= (UPSMR_RPM | UPSMR_R10M);
154 case PHY_INTERFACE_MODE_RMII:
155 upsmr |= (UPSMR_R10M | UPSMR_RMM);
162 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
163 switch (enet_if_mode) {
164 case PHY_INTERFACE_MODE_MII:
166 case PHY_INTERFACE_MODE_RGMII:
169 case PHY_INTERFACE_MODE_RMII:
177 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
178 switch (enet_if_mode) {
179 case PHY_INTERFACE_MODE_GMII:
181 case PHY_INTERFACE_MODE_TBI:
184 case PHY_INTERFACE_MODE_RTBI:
185 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
187 case PHY_INTERFACE_MODE_RGMII_RXID:
188 case PHY_INTERFACE_MODE_RGMII_TXID:
189 case PHY_INTERFACE_MODE_RGMII_ID:
190 case PHY_INTERFACE_MODE_RGMII:
193 case PHY_INTERFACE_MODE_SGMII:
204 out_be32(&uec_regs->maccfg2, maccfg2);
205 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
210 static int qe_uec_start(struct udevice *dev)
212 struct qe_uec_priv *priv = dev_get_priv(dev);
213 struct uec_priv *uec = priv->uec;
214 struct phy_device *phydev = priv->phydev;
215 struct uec_inf *uec_info = uec->uec_info;
221 /* Setup MAC interface mode */
222 genphy_update_link(phydev);
223 genphy_parse_link(phydev);
224 uec_info->speed = phydev->speed;
225 uec_set_mac_if_mode(uec);
227 err = uec_open(uec, COMM_DIR_RX_AND_TX);
229 printf("%s: cannot enable UEC device\n", dev->name);
233 return (phydev->link ? 0 : -EINVAL);
236 static int qe_uec_send(struct udevice *dev, void *packet, int length)
238 struct qe_uec_priv *priv = dev_get_priv(dev);
239 struct uec_priv *uec = priv->uec;
240 struct ucc_fast_priv *uccf = uec->uccf;
241 struct buffer_descriptor *bd;
249 /* Find an empty TxBD */
250 for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
252 printf("%s: tx buffer not ready\n", dev->name);
258 BD_DATA_SET(bd, packet);
259 BD_LENGTH_SET(bd, length);
260 status = BD_STATUS(bd);
262 status |= (TX_BD_READY | TX_BD_LAST);
263 BD_STATUS_SET(bd, status);
265 /* Tell UCC to transmit the buffer */
266 ucc_fast_transmit_on_demand(uccf);
268 /* Wait for buffer to be transmitted */
269 for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
271 printf("%s: tx error\n", dev->name);
276 /* Ok, the buffer be transimitted */
277 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
286 * - wait for the next BD to get ready bit set
287 * - clean up the descriptor
288 * - move on and indicate to HW that the cleaned BD is available for Rx
290 static int qe_uec_recv(struct udevice *dev, int flags, uchar **packetp)
292 struct qe_uec_priv *priv = dev_get_priv(dev);
293 struct uec_priv *uec = priv->uec;
294 struct buffer_descriptor *bd;
299 *packetp = memalign(ARCH_DMA_MINALIGN, MAX_RXBUF_LEN);
301 printf("%s: error allocating packetp\n", __func__);
306 status = BD_STATUS(bd);
308 while (!(status & RX_BD_EMPTY)) {
309 if (!(status & RX_BD_ERROR)) {
312 memcpy(*packetp, (char *)data, len);
314 printf("%s: Rx error\n", dev->name);
317 BD_LENGTH_SET(bd, 0);
318 BD_STATUS_SET(bd, status | RX_BD_EMPTY);
319 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
320 status = BD_STATUS(bd);
327 static int uec_graceful_stop_tx(struct uec_priv *uec)
333 uf_regs = uec->uccf->uf_regs;
335 /* Clear the grace stop event */
336 out_be32(&uf_regs->ucce, UCCE_GRA);
338 /* Issue host command */
340 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
341 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
342 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
344 /* Wait for command to complete */
346 ucce = in_be32(&uf_regs->ucce);
347 } while (!(ucce & UCCE_GRA));
349 uec->grace_stopped_tx = 1;
354 static int uec_graceful_stop_rx(struct uec_priv *uec)
359 if (!uec->p_rx_glbl_pram) {
360 printf("%s: No init rx global parameter\n", __func__);
364 /* Clear acknowledge bit */
365 ack = uec->p_rx_glbl_pram->rxgstpack;
366 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
367 uec->p_rx_glbl_pram->rxgstpack = ack;
369 /* Keep issuing cmd and checking ack bit until it is asserted */
371 /* Issue host command */
373 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
374 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
375 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
376 ack = uec->p_rx_glbl_pram->rxgstpack;
377 } while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX));
379 uec->grace_stopped_rx = 1;
384 static int uec_stop(struct uec_priv *uec, comm_dir_e mode)
386 /* check if the UCC number is in range. */
387 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
388 printf("%s: ucc_num out of range.\n", __func__);
391 /* Stop any transmissions */
392 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx)
393 uec_graceful_stop_tx(uec);
395 /* Stop any receptions */
396 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx)
397 uec_graceful_stop_rx(uec);
399 /* Disable the UCC fast */
400 ucc_fast_disable(uec->uccf, mode);
402 /* Disable the MAC */
403 uec_mac_disable(uec, mode);
408 static void qe_uec_stop(struct udevice *dev)
410 struct qe_uec_priv *priv = dev_get_priv(dev);
411 struct uec_priv *uec = priv->uec;
413 uec_stop(uec, COMM_DIR_RX_AND_TX);
416 static int qe_uec_set_hwaddr(struct udevice *dev)
418 struct qe_uec_priv *priv = dev_get_priv(dev);
419 struct eth_pdata *pdata = dev_get_platdata(dev);
420 struct uec_priv *uec = priv->uec;
421 uec_t *uec_regs = uec->uec_regs;
422 uchar *mac = pdata->enetaddr;
427 * if a station address of 0x12345678ABCD, perform a write to
428 * MACSTNADDR1 of 0xCDAB7856,
429 * MACSTNADDR2 of 0x34120000
432 mac_addr1 = (mac[5] << 24) | (mac[4] << 16) |
433 (mac[3] << 8) | (mac[2]);
434 out_be32(&uec_regs->macstnaddr1, mac_addr1);
436 mac_addr2 = ((mac[1] << 24) | (mac[0] << 16)) & 0xffff0000;
437 out_be32(&uec_regs->macstnaddr2, mac_addr2);
442 static int qe_uec_free_pkt(struct udevice *dev, uchar *packet, int length)
450 static const struct eth_ops qe_uec_eth_ops = {
451 .start = qe_uec_start,
454 .free_pkt = qe_uec_free_pkt,
456 .write_hwaddr = qe_uec_set_hwaddr,
459 static int uec_convert_threads_num(enum uec_num_of_threads threads_num,
460 int *threads_num_ret)
462 int num_threads_numerica;
464 switch (threads_num) {
465 case UEC_NUM_OF_THREADS_1:
466 num_threads_numerica = 1;
468 case UEC_NUM_OF_THREADS_2:
469 num_threads_numerica = 2;
471 case UEC_NUM_OF_THREADS_4:
472 num_threads_numerica = 4;
474 case UEC_NUM_OF_THREADS_6:
475 num_threads_numerica = 6;
477 case UEC_NUM_OF_THREADS_8:
478 num_threads_numerica = 8;
481 printf("%s: Bad number of threads value.",
486 *threads_num_ret = num_threads_numerica;
491 static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx)
493 struct uec_inf *uec_info;
498 uec_info = uec->uec_info;
500 /* Alloc global Tx parameter RAM page */
501 uec->tx_glbl_pram_offset =
502 qe_muram_alloc(sizeof(struct uec_tx_global_pram),
503 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
504 uec->p_tx_glbl_pram = (struct uec_tx_global_pram *)
505 qe_muram_addr(uec->tx_glbl_pram_offset);
507 /* Zero the global Tx prameter RAM */
508 memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram));
510 /* Init global Tx parameter RAM */
512 /* TEMODER, RMON statistics disable, one Tx queue */
513 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
516 uec->send_q_mem_reg_offset =
517 qe_muram_alloc(sizeof(struct uec_send_queue_qd),
518 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
519 uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *)
520 qe_muram_addr(uec->send_q_mem_reg_offset);
521 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
523 /* Setup the table with TxBDs ring */
524 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
526 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
527 (u32)(uec->p_tx_bd_ring));
528 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
531 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
532 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
534 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
535 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
537 /* TSTATE, global snooping, big endian, the CSB bus selected */
538 bmrx = BMR_INIT_VALUE;
539 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
542 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++)
543 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
546 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++)
547 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
550 uec->thread_dat_tx_offset =
551 qe_muram_alloc(num_threads_tx *
552 sizeof(struct uec_thread_data_tx) +
553 32 * (num_threads_tx == 1),
554 UEC_THREAD_DATA_ALIGNMENT);
556 uec->p_thread_data_tx = (struct uec_thread_data_tx *)
557 qe_muram_addr(uec->thread_dat_tx_offset);
558 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
561 static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx)
565 struct uec_82xx_add_filtering_pram *p_af_pram;
567 /* Allocate global Rx parameter RAM page */
568 uec->rx_glbl_pram_offset =
569 qe_muram_alloc(sizeof(struct uec_rx_global_pram),
570 UEC_RX_GLOBAL_PRAM_ALIGNMENT);
571 uec->p_rx_glbl_pram = (struct uec_rx_global_pram *)
572 qe_muram_addr(uec->rx_glbl_pram_offset);
574 /* Zero Global Rx parameter RAM */
575 memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram));
577 /* Init global Rx parameter RAM */
579 * REMODER, Extended feature mode disable, VLAN disable,
580 * LossLess flow control disable, Receive firmware statisic disable,
581 * Extended address parsing mode disable, One Rx queues,
582 * Dynamic maximum/minimum frame length disable, IP checksum check
583 * disable, IP address alignment disable
585 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
588 uec->thread_dat_rx_offset =
589 qe_muram_alloc(num_threads_rx *
590 sizeof(struct uec_thread_data_rx),
591 UEC_THREAD_DATA_ALIGNMENT);
592 uec->p_thread_data_rx = (struct uec_thread_data_rx *)
593 qe_muram_addr(uec->thread_dat_rx_offset);
594 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
597 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
599 /* RxRMON base pointer, we don't need it */
600 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
602 /* IntCoalescingPTR, we don't need it, no interrupt */
603 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
605 /* RSTATE, global snooping, big endian, the CSB bus selected */
606 bmrx = BMR_INIT_VALUE;
607 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
610 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
613 uec->rx_bd_qs_tbl_offset =
614 qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) +
615 sizeof(struct uec_rx_pref_bds),
616 UEC_RX_BD_QUEUES_ALIGNMENT);
617 uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *)
618 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
621 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) +
622 sizeof(struct uec_rx_pref_bds));
623 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
624 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
625 (u32)uec->p_rx_bd_ring);
628 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
630 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
632 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
634 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
636 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
638 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
640 for (i = 0; i < 8; i++)
641 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
644 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
646 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
648 /* Clear PQ2 style address filtering hash table */
649 p_af_pram = (struct uec_82xx_add_filtering_pram *)
650 uec->p_rx_glbl_pram->addressfiltering;
652 p_af_pram->iaddr_h = 0;
653 p_af_pram->iaddr_l = 0;
654 p_af_pram->gaddr_h = 0;
655 p_af_pram->gaddr_l = 0;
658 static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec,
659 int thread_tx, int thread_rx)
661 struct uec_init_cmd_pram *p_init_enet_param;
662 u32 init_enet_param_offset;
663 struct uec_inf *uec_info;
664 struct ucc_fast_inf *uf_info;
672 uec_info = uec->uec_info;
673 uf_info = &uec_info->uf_info;
675 /* Allocate init enet command parameter */
676 uec->init_enet_param_offset =
677 qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4);
678 init_enet_param_offset = uec->init_enet_param_offset;
679 uec->p_init_enet_param = (struct uec_init_cmd_pram *)
680 qe_muram_addr(uec->init_enet_param_offset);
682 /* Zero init enet command struct */
683 memset((void *)uec->p_init_enet_param, 0,
684 sizeof(struct uec_init_cmd_pram));
686 /* Init the command struct */
687 p_init_enet_param = uec->p_init_enet_param;
688 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
689 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
690 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
691 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
692 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
693 p_init_enet_param->largestexternallookupkeysize = 0;
695 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
696 << ENET_INIT_PARAM_RGF_SHIFT;
697 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
698 << ENET_INIT_PARAM_TGF_SHIFT;
700 /* Init Rx global parameter pointer */
701 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
702 (u32)uec_info->risc_rx;
704 /* Init Rx threads */
705 for (i = 0; i < (thread_rx + 1); i++) {
706 snum = qe_get_snum();
708 printf("%s can not get snum\n", __func__);
715 off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram),
716 UEC_THREAD_RX_PRAM_ALIGNMENT);
719 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
720 off | (u32)uec_info->risc_rx;
721 p_init_enet_param->rxthread[i] = entry_val;
724 /* Init Tx global parameter pointer */
725 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
726 (u32)uec_info->risc_tx;
728 /* Init Tx threads */
729 for (i = 0; i < thread_tx; i++) {
730 snum = qe_get_snum();
732 printf("%s can not get snum\n", __func__);
736 off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram),
737 UEC_THREAD_TX_PRAM_ALIGNMENT);
739 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
740 off | (u32)uec_info->risc_tx;
741 p_init_enet_param->txthread[i] = entry_val;
744 __asm__ __volatile__("sync");
746 /* Issue QE command */
747 command = QE_INIT_TX_RX;
748 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
749 qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET,
750 init_enet_param_offset);
755 static int uec_startup(struct udevice *dev)
757 struct qe_uec_priv *priv = dev_get_priv(dev);
758 struct uec_priv *uec = priv->uec;
759 struct uec_inf *uec_info;
760 struct ucc_fast_inf *uf_info;
761 struct ucc_fast_priv *uccf;
769 struct buffer_descriptor *bd;
773 uec_info = uec->uec_info;
774 uf_info = &uec_info->uf_info;
776 /* Check if Rx BD ring len is illegal */
777 if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN ||
778 uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT) {
779 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
784 /* Check if Tx BD ring len is illegal */
785 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
786 printf("%s: Tx BD ring length must not be smaller than 2.\n",
791 /* Check if MRBLR is illegal */
792 if (MAX_RXBUF_LEN == 0 || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
793 printf("%s: max rx buffer length must be mutliple of 128.\n",
798 /* Both Rx and Tx are stopped */
799 uec->grace_stopped_rx = 1;
800 uec->grace_stopped_tx = 1;
803 if (ucc_fast_init(uf_info, &uccf)) {
804 printf("%s: failed to init ucc fast\n", __func__);
811 /* Convert the Tx threads number */
812 if (uec_convert_threads_num(uec_info->num_threads_tx,
816 /* Convert the Rx threads number */
817 if (uec_convert_threads_num(uec_info->num_threads_rx,
821 uf_regs = uccf->uf_regs;
823 /* UEC register is following UCC fast registers */
824 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
826 /* Save the UEC register pointer to UEC private struct */
827 uec->uec_regs = uec_regs;
829 /* Init UPSMR, enable hardware statistics (UCC) */
830 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
832 /* Init MACCFG1, flow control disable, disable Tx and Rx */
833 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
835 /* Init MACCFG2, length check, MAC PAD and CRC enable */
836 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
839 utbipar = in_be32(&uec_regs->utbipar);
840 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
842 /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
843 * This frees up the remaining SMI addresses for use.
845 utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
846 out_be32(&uec_regs->utbipar, utbipar);
848 /* Allocate Tx BDs */
849 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
850 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
851 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
852 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
853 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
854 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
856 align = UEC_TX_BD_RING_ALIGNMENT;
857 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
858 if (uec->tx_bd_ring_offset != 0)
859 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
862 /* Zero all of Tx BDs */
863 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
865 /* Allocate Rx BDs */
866 length = uec_info->rx_bd_ring_len * SIZEOFBD;
867 align = UEC_RX_BD_RING_ALIGNMENT;
868 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
869 if (uec->rx_bd_ring_offset != 0)
870 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
873 /* Zero all of Rx BDs */
874 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
876 /* Allocate Rx buffer */
877 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
878 align = UEC_RX_DATA_BUF_ALIGNMENT;
879 uec->rx_buf_offset = (u32)malloc(length + align);
880 if (uec->rx_buf_offset != 0)
881 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
884 /* Zero all of the Rx buffer */
885 memset((void *)(uec->rx_buf_offset), 0, length + align);
888 bd = (struct buffer_descriptor *)uec->p_tx_bd_ring;
891 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
893 BD_STATUS_SET(bd, 0);
894 BD_LENGTH_SET(bd, 0);
897 BD_STATUS_SET((--bd), TX_BD_WRAP);
900 bd = (struct buffer_descriptor *)uec->p_rx_bd_ring;
903 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
904 BD_DATA_SET(bd, buf);
905 BD_LENGTH_SET(bd, 0);
906 BD_STATUS_SET(bd, RX_BD_EMPTY);
907 buf += MAX_RXBUF_LEN;
910 BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY);
912 /* Init global Tx parameter RAM */
913 uec_init_tx_parameter(uec, num_threads_tx);
915 /* Init global Rx parameter RAM */
916 uec_init_rx_parameter(uec, num_threads_rx);
918 /* Init ethernet Tx and Rx parameter command */
919 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
921 printf("%s issue init enet cmd failed\n", __func__);
927 /* Convert a string to a QE clock source enum
929 * This function takes a string, typically from a property in the device
930 * tree, and returns the corresponding "enum qe_clock" value.
932 enum qe_clock qe_clock_source(const char *source)
936 if (strcasecmp(source, "none") == 0)
939 if (strncasecmp(source, "brg", 3) == 0) {
940 i = simple_strtoul(source + 3, NULL, 10);
941 if (i >= 1 && i <= 16)
942 return (QE_BRG1 - 1) + i;
947 if (strncasecmp(source, "clk", 3) == 0) {
948 i = simple_strtoul(source + 3, NULL, 10);
949 if (i >= 1 && i <= 24)
950 return (QE_CLK1 - 1) + i;
958 static void qe_uec_set_eth_type(struct udevice *dev)
960 struct qe_uec_priv *priv = dev_get_priv(dev);
961 struct uec_priv *uec = priv->uec;
962 struct uec_inf *uec_info = uec->uec_info;
963 struct ucc_fast_inf *uf_info = &uec_info->uf_info;
965 switch (uec_info->enet_interface_type) {
966 case PHY_INTERFACE_MODE_GMII:
967 case PHY_INTERFACE_MODE_RGMII:
968 case PHY_INTERFACE_MODE_RGMII_ID:
969 case PHY_INTERFACE_MODE_RGMII_RXID:
970 case PHY_INTERFACE_MODE_RGMII_TXID:
971 case PHY_INTERFACE_MODE_TBI:
972 case PHY_INTERFACE_MODE_RTBI:
973 case PHY_INTERFACE_MODE_SGMII:
974 uf_info->eth_type = GIGA_ETH;
977 uf_info->eth_type = FAST_ETH;
982 static int qe_uec_set_uec_info(struct udevice *dev)
984 struct qe_uec_priv *priv = dev_get_priv(dev);
985 struct eth_pdata *pdata = dev_get_platdata(dev);
986 struct uec_priv *uec = priv->uec;
987 struct uec_inf *uec_info;
988 struct ucc_fast_inf *uf_info;
993 uec_info = (struct uec_inf *)malloc(sizeof(struct uec_inf));
997 uf_info = &uec_info->uf_info;
999 ret = dev_read_u32(dev, "cell-index", &val);
1001 ret = dev_read_u32(dev, "device-id", &val);
1003 pr_err("no cell-index nor device-id found!");
1008 uf_info->ucc_num = val - 1;
1009 if (uf_info->ucc_num < 0 || uf_info->ucc_num > 7) {
1014 ret = dev_read_string_index(dev, "rx-clock-name", 0, &s);
1016 uf_info->rx_clock = qe_clock_source(s);
1017 if (uf_info->rx_clock < QE_CLK_NONE ||
1018 uf_info->rx_clock > QE_CLK24) {
1019 pr_err("invalid rx-clock-name property\n");
1024 ret = dev_read_u32(dev, "rx-clock", &val);
1027 * If both rx-clock-name and rx-clock are missing,
1028 * we want to tell people to use rx-clock-name.
1030 pr_err("missing rx-clock-name property\n");
1033 if (val < QE_CLK_NONE || val > QE_CLK24) {
1034 pr_err("invalid rx-clock property\n");
1038 uf_info->rx_clock = val;
1041 ret = dev_read_string_index(dev, "tx-clock-name", 0, &s);
1043 uf_info->tx_clock = qe_clock_source(s);
1044 if (uf_info->tx_clock < QE_CLK_NONE ||
1045 uf_info->tx_clock > QE_CLK24) {
1046 pr_err("invalid tx-clock-name property\n");
1051 ret = dev_read_u32(dev, "tx-clock", &val);
1053 pr_err("missing tx-clock-name property\n");
1056 if (val < QE_CLK_NONE || val > QE_CLK24) {
1057 pr_err("invalid tx-clock property\n");
1061 uf_info->tx_clock = val;
1064 uec_info->num_threads_tx = UEC_NUM_OF_THREADS_1;
1065 uec_info->num_threads_rx = UEC_NUM_OF_THREADS_1;
1066 uec_info->risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2;
1067 uec_info->risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2;
1068 uec_info->tx_bd_ring_len = 16;
1069 uec_info->rx_bd_ring_len = 16;
1070 #if (MAX_QE_RISC == 4)
1071 uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1072 uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1075 uec_info->enet_interface_type = pdata->phy_interface;
1077 uec->uec_info = uec_info;
1078 qe_uec_set_eth_type(dev);
1086 static int qe_uec_probe(struct udevice *dev)
1088 struct qe_uec_priv *priv = dev_get_priv(dev);
1089 struct eth_pdata *pdata = dev_get_platdata(dev);
1090 struct uec_priv *uec;
1093 /* Allocate the UEC private struct */
1094 uec = (struct uec_priv *)malloc(sizeof(struct uec_priv));
1098 memset(uec, 0, sizeof(struct uec_priv));
1100 uec->uec_regs = (uec_t *)pdata->iobase;
1102 /* setup uec info struct */
1103 ret = qe_uec_set_uec_info(dev);
1109 ret = uec_startup(dev);
1111 free(uec->uec_info);
1116 priv->phydev = dm_eth_phy_connect(dev);
1121 * Remove the driver from an interface:
1122 * - free up allocated memory
1124 static int qe_uec_remove(struct udevice *dev)
1126 struct qe_uec_priv *priv = dev_get_priv(dev);
1132 static int qe_uec_ofdata_to_platdata(struct udevice *dev)
1134 struct eth_pdata *pdata = dev_get_platdata(dev);
1135 const char *phy_mode;
1137 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1139 pdata->phy_interface = -1;
1140 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
1141 "phy-connection-type", NULL);
1143 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1144 if (pdata->phy_interface == -1) {
1145 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1152 static const struct udevice_id qe_uec_ids[] = {
1153 { .compatible = QE_UEC_DRIVER_NAME },
1157 U_BOOT_DRIVER(eth_qe_uec) = {
1158 .name = QE_UEC_DRIVER_NAME,
1160 .of_match = qe_uec_ids,
1161 .ofdata_to_platdata = qe_uec_ofdata_to_platdata,
1162 .probe = qe_uec_probe,
1163 .remove = qe_uec_remove,
1164 .ops = &qe_uec_eth_ops,
1165 .priv_auto_alloc_size = sizeof(struct qe_uec_priv),
1166 .platdata_auto_alloc_size = sizeof(struct eth_pdata),