1 // SPDX-License-Identifier: GPL-2.0+
3 * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
17 #include <linux/mii.h>
19 #include "pic32_eth.h"
21 #define MAX_RX_BUF_SIZE 1536
22 #define MAX_RX_DESCR PKTBUFSRX
23 #define MAX_TX_DESCR 2
25 DECLARE_GLOBAL_DATA_PTR;
28 struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
29 struct eth_dma_desc txd_ring[MAX_TX_DESCR];
30 u32 rxd_idx; /* index of RX desc to read */
32 struct pic32_ectl_regs *ectl_regs;
33 struct pic32_emac_regs *emac_regs;
35 struct phy_device *phydev;
36 phy_interface_t phyif;
38 struct gpio_desc rst_gpio;
41 void __weak board_netphy_reset(void *dev)
43 struct pic32eth_dev *priv = dev;
45 if (!dm_gpio_is_valid(&priv->rst_gpio))
49 dm_gpio_set_value(&priv->rst_gpio, 0);
51 dm_gpio_set_value(&priv->rst_gpio, 1);
55 /* Initialize mii(MDIO) interface, discover which PHY is
56 * attached to the device, and configure it properly.
58 static int pic32_mii_init(struct pic32eth_dev *priv)
60 struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
61 struct pic32_emac_regs *emac_p = priv->emac_regs;
64 board_netphy_reset(priv);
66 /* disable RX, TX & all transactions */
67 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
70 wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
71 CONFIG_SYS_HZ, false);
73 /* turn controller ON to access PHY over MII */
74 writel(ETHCON_ON, &ectl_p->con1.set);
79 writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
81 writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
83 /* initialize MDIO/MII */
84 if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
85 writel(EMAC_RMII_RESET, &emac_p->supp.set);
87 writel(EMAC_RMII_RESET, &emac_p->supp.clr);
90 return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
93 static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
97 mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
99 /* find & connect PHY */
100 priv->phydev = phy_connect(mii, priv->phy_addr,
103 printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
107 /* Wait for phy to complete reset */
110 /* configure supported modes */
111 priv->phydev->supported = SUPPORTED_10baseT_Half |
112 SUPPORTED_10baseT_Full |
113 SUPPORTED_100baseT_Half |
114 SUPPORTED_100baseT_Full |
117 priv->phydev->advertising = ADVERTISED_10baseT_Half |
118 ADVERTISED_10baseT_Full |
119 ADVERTISED_100baseT_Half |
120 ADVERTISED_100baseT_Full |
123 priv->phydev->autoneg = AUTONEG_ENABLE;
128 /* Configure MAC based on negotiated speed and duplex
131 static int pic32_mac_adjust_link(struct pic32eth_dev *priv)
133 struct phy_device *phydev = priv->phydev;
134 struct pic32_emac_regs *emac_p = priv->emac_regs;
137 printf("%s: No link.\n", phydev->dev->name);
141 if (phydev->duplex) {
142 writel(EMAC_FULLDUP, &emac_p->cfg2.set);
143 writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw);
145 writel(EMAC_FULLDUP, &emac_p->cfg2.clr);
146 writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
149 switch (phydev->speed) {
151 writel(EMAC_RMII_SPD100, &emac_p->supp.set);
154 writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
157 printf("%s: Speed was bad\n", phydev->dev->name);
161 printf("pic32eth: PHY is %s with %dbase%s, %s\n",
162 phydev->drv->name, phydev->speed,
163 (phydev->port == PORT_TP) ? "T" : "X",
164 (phydev->duplex) ? "full" : "half");
169 static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr)
171 struct pic32_emac_regs *emac_p = priv->emac_regs;
175 v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE;
176 writel(v, &emac_p->cfg1.raw);
178 v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE |
179 EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP;
180 writel(v, &emac_p->cfg2.raw);
182 /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */
183 writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
185 /* recommended non-back-to-back interpacket gap is 0xc12 */
186 writel(0xc12, &emac_p->ipgr.raw);
188 /* recommended collision window retry limit is 0x370F */
189 writel(0x370f, &emac_p->clrt.raw);
191 /* set maximum frame length: allow VLAN tagged frame */
192 writel(0x600, &emac_p->maxf.raw);
194 /* set the mac address */
195 writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw);
196 writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw);
197 writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw);
199 /* default, enable 10 Mbps operation */
200 writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
202 /* wait until link status UP or deadline elapsed */
203 expire = get_ticks() + get_tbclk() * 2;
204 for (; get_ticks() < expire;) {
205 stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR);
206 if (stat & BMSR_LSTATUS)
210 if (!(stat & BMSR_LSTATUS))
211 printf("MAC: Link is DOWN!\n");
213 /* delay to stabilize before any tx/rx */
217 static void pic32_mac_reset(struct pic32eth_dev *priv)
219 struct pic32_emac_regs *emac_p = priv->emac_regs;
223 writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
227 writel(0, &emac_p->cfg1.raw);
230 mii = priv->phydev->bus;
231 if (mii && mii->reset)
235 /* initializes the MAC and PHY, then establishes a link */
236 static void pic32_ctrl_reset(struct pic32eth_dev *priv)
238 struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
241 /* disable RX, TX & any other transactions */
242 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
245 wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
246 CONFIG_SYS_HZ, false);
247 /* decrement received buffcnt to zero. */
248 while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
249 writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
251 /* clear any existing interrupt event */
252 writel(0xffffffff, &ectl_p->irq.clr);
254 /* clear RX/TX start address */
255 writel(0xffffffff, &ectl_p->txst.clr);
256 writel(0xffffffff, &ectl_p->rxst.clr);
258 /* clear the receive filters */
259 writel(0x00ff, &ectl_p->rxfc.clr);
261 /* set the receive filters
262 * ETH_FILT_CRC_ERR_REJECT
263 * ETH_FILT_RUNT_REJECT
264 * ETH_FILT_UCAST_ACCEPT
265 * ETH_FILT_MCAST_ACCEPT
266 * ETH_FILT_BCAST_ACCEPT
268 v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN |
269 ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN;
270 writel(v, &ectl_p->rxfc.set);
272 /* turn controller ON to access PHY over MII */
273 writel(ETHCON_ON, &ectl_p->con1.set);
276 static void pic32_rx_desc_init(struct pic32eth_dev *priv)
278 struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
279 struct eth_dma_desc *rxd;
283 for (idx = 0; idx < MAX_RX_DESCR; idx++) {
284 rxd = &priv->rxd_ring[idx];
287 rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY;
289 /* packet buffer address */
290 rxd->data_buff = virt_to_phys(net_rx_packets[idx]);
292 /* link to next desc */
293 rxd->next_ed = virt_to_phys(rxd + 1);
299 /* decrement bufcnt */
300 writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
303 /* link last descr to beginning of list */
304 rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]);
307 flush_dcache_range((ulong)priv->rxd_ring,
308 (ulong)priv->rxd_ring + sizeof(priv->rxd_ring));
310 /* set rx desc-ring start address */
311 writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw);
314 bufsz = readl(&ectl_p->con2.raw);
315 bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT);
316 bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT);
317 writel(bufsz, &ectl_p->con2.raw);
319 /* enable the receiver in hardware which allows hardware
320 * to DMA received pkts to the descriptor pointer address.
322 writel(ETHCON_RXEN, &ectl_p->con1.set);
325 static int pic32_eth_start(struct udevice *dev)
327 struct eth_pdata *pdata = dev_get_platdata(dev);
328 struct pic32eth_dev *priv = dev_get_priv(dev);
331 pic32_ctrl_reset(priv);
334 pic32_mac_reset(priv);
337 phy_config(priv->phydev);
340 pic32_mac_init(priv, &pdata->enetaddr[0]);
342 /* init RX descriptor; TX descriptors are handled in xmit */
343 pic32_rx_desc_init(priv);
345 /* Start up & update link status of PHY */
346 phy_startup(priv->phydev);
348 /* adjust mac with phy link status */
349 return pic32_mac_adjust_link(priv);
352 static void pic32_eth_stop(struct udevice *dev)
354 struct pic32eth_dev *priv = dev_get_priv(dev);
355 struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
356 struct pic32_emac_regs *emac_p = priv->emac_regs;
358 /* Reset the phy if the controller is enabled */
359 if (readl(&ectl_p->con1.raw) & ETHCON_ON)
360 phy_reset(priv->phydev);
362 /* Shut down the PHY */
363 phy_shutdown(priv->phydev);
366 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
370 writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
373 writel(0, &emac_p->cfg1.raw);
376 /* disable controller */
377 writel(ETHCON_ON, &ectl_p->con1.clr);
380 /* wait until everything is down */
381 wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
382 2 * CONFIG_SYS_HZ, false);
384 /* clear any existing interrupt event */
385 writel(0xffffffff, &ectl_p->irq.clr);
388 static int pic32_eth_send(struct udevice *dev, void *packet, int length)
390 struct pic32eth_dev *priv = dev_get_priv(dev);
391 struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
392 struct eth_dma_desc *txd;
395 txd = &priv->txd_ring[0];
397 /* set proper flags & length in descriptor header */
398 txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length);
400 /* pass buffer address to hardware */
401 txd->data_buff = virt_to_phys(packet);
403 debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n",
404 __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2,
407 /* cache flush (packet) */
408 flush_dcache_range((ulong)packet, (ulong)packet + length);
410 /* cache flush (txd) */
411 flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
413 /* pass descriptor table base to h/w */
414 writel(virt_to_phys(txd), &ectl_p->txst.raw);
416 /* ready to send enabled, hardware can now send the packet(s) */
417 writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set);
419 /* wait until tx has completed and h/w has released ownership
420 * of the tx descriptor or timeout elapsed.
422 deadline = get_ticks() + get_tbclk();
425 if (get_ticks() > deadline)
432 if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) {
437 /* h/w not released ownership yet? */
438 invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
439 if (!(txd->hdr & EDH_EOWN))
446 static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp)
448 struct pic32eth_dev *priv = dev_get_priv(dev);
449 struct eth_dma_desc *rxd;
450 u32 idx = priv->rxd_idx;
453 /* find the next ready to receive */
454 rxd = &priv->rxd_ring[idx];
456 invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
457 /* check if owned by MAC */
458 if (rxd->hdr & EDH_EOWN)
461 /* Sanity check on header: SOP and EOP */
462 if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) {
463 printf("%s: %s, rx pkt across multiple descr\n",
468 debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n",
469 __func__, __LINE__, idx, rxd->hdr,
470 rxd->data_buff, rxd->stat2, rxd->next_ed);
472 /* Sanity check on rx_stat: OK, CRC */
473 if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) {
474 debug("%s: %s: Error, rx problem detected\n",
479 /* invalidate dcache */
480 rx_count = RSV_RX_COUNT(rxd->stat2);
481 invalidate_dcache_range((ulong)net_rx_packets[idx],
482 (ulong)net_rx_packets[idx] + rx_count);
484 /* Pass the packet to protocol layer */
485 *packetp = net_rx_packets[idx];
487 /* increment number of bytes rcvd (ignore CRC) */
491 static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
493 struct pic32eth_dev *priv = dev_get_priv(dev);
494 struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
495 struct eth_dma_desc *rxd;
496 int idx = priv->rxd_idx;
499 if (packet != net_rx_packets[idx]) {
500 printf("rxd_id %d: packet is not matched,\n", idx);
504 /* prepare for receive */
505 rxd = &priv->rxd_ring[idx];
506 rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN;
508 flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
510 /* decrement rx pkt count */
511 writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
513 debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n",
514 __func__, __LINE__, idx, rxd->hdr, rxd->data_buff,
515 rxd->stat2, rxd->next_ed);
517 priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR;
522 static const struct eth_ops pic32_eth_ops = {
523 .start = pic32_eth_start,
524 .send = pic32_eth_send,
525 .recv = pic32_eth_recv,
526 .free_pkt = pic32_eth_free_pkt,
527 .stop = pic32_eth_stop,
530 static int pic32_eth_probe(struct udevice *dev)
532 struct eth_pdata *pdata = dev_get_platdata(dev);
533 struct pic32eth_dev *priv = dev_get_priv(dev);
534 const char *phy_mode;
535 void __iomem *iobase;
541 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
543 if (addr == FDT_ADDR_T_NONE)
546 iobase = ioremap(addr, size);
547 pdata->iobase = (phys_addr_t)addr;
550 pdata->phy_interface = -1;
551 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
554 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
555 if (pdata->phy_interface == -1) {
556 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
561 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
564 phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
567 gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
568 &priv->rst_gpio, GPIOD_IS_OUT);
570 priv->phyif = pdata->phy_interface;
571 priv->phy_addr = phy_addr;
572 priv->ectl_regs = iobase;
573 priv->emac_regs = iobase + PIC32_EMAC1CFG1;
575 pic32_mii_init(priv);
577 return pic32_phy_init(priv, dev);
580 static int pic32_eth_remove(struct udevice *dev)
582 struct pic32eth_dev *priv = dev_get_priv(dev);
585 dm_gpio_free(dev, &priv->rst_gpio);
586 phy_shutdown(priv->phydev);
588 bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
589 mdio_unregister(bus);
591 iounmap(priv->ectl_regs);
595 static const struct udevice_id pic32_eth_ids[] = {
596 { .compatible = "microchip,pic32mzda-eth" },
600 U_BOOT_DRIVER(pic32_ethernet) = {
601 .name = "pic32_ethernet",
603 .of_match = pic32_eth_ids,
604 .probe = pic32_eth_probe,
605 .remove = pic32_eth_remove,
606 .ops = &pic32_eth_ops,
607 .priv_auto_alloc_size = sizeof(struct pic32eth_dev),
608 .platdata_auto_alloc_size = sizeof(struct eth_pdata),