drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/realtek.c
   4  *
   5  * Driver for Realtek PHYs
   6  *
   7  * Author: Johnson Leung <r58129@freescale.com>
   8  *
   9  * Copyright (c) 2004 Freescale Semiconductor, Inc.
  10  */
  11 #include <linux/bitops.h>
  12 #include <linux/phy.h>
  13 #include <linux/module.h>
  14
  15 #define RTL821x_PHYSR                           0x11
  16 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  17 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  18
  19 #define RTL821x_INER                            0x12
  20 #define RTL8211B_INER_INIT                      0x6400
  21 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  22 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  23
  24 #define RTL821x_INSR                            0x13
  25
  26 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  27 #define RTL821x_PAGE_SELECT                     0x1f
  28
  29 #define RTL8211F_INSR                           0x1d
  30
  31 #define RTL8211F_TX_DELAY                       BIT(8)
  32 #define RTL8211E_TX_DELAY                       BIT(1)
  33 #define RTL8211E_RX_DELAY                       BIT(2)
  34 #define RTL8211E_MODE_MII_GMII                  BIT(3)
  35
  36 #define RTL8201F_ISR                            0x1e
  37 #define RTL8201F_IER                            0x13
  38
  39 #define RTL8366RB_POWER_SAVE                    0x15
  40 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  41
  42 #define RTL_SUPPORTS_5000FULL                   BIT(14)
  43 #define RTL_SUPPORTS_2500FULL                   BIT(13)
  44 #define RTL_SUPPORTS_10000FULL                  BIT(0)
  45 #define RTL_ADV_2500FULL                        BIT(7)
  46 #define RTL_LPADV_10000FULL                     BIT(11)
  47 #define RTL_LPADV_5000FULL                      BIT(6)
  48 #define RTL_LPADV_2500FULL                      BIT(5)
  49
  50 #define RTL_GENERIC_PHYID                       0x001cc800
  51
  52 MODULE_DESCRIPTION("Realtek PHY driver");
  53 MODULE_AUTHOR("Johnson Leung");
  54 MODULE_LICENSE("GPL");
  55
  56 static int rtl821x_read_page(struct phy_device *phydev)
  57 {
  58         return __phy_read(phydev, RTL821x_PAGE_SELECT);
  59 }
  60
  61 static int rtl821x_write_page(struct phy_device *phydev, int page)
  62 {
  63         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
  64 }
  65
  66 static int rtl8201_ack_interrupt(struct phy_device *phydev)
  67 {
  68         int err;
  69
  70         err = phy_read(phydev, RTL8201F_ISR);
  71
  72         return (err < 0) ? err : 0;
  73 }
  74
  75 static int rtl821x_ack_interrupt(struct phy_device *phydev)
  76 {
  77         int err;
  78
  79         err = phy_read(phydev, RTL821x_INSR);
  80
  81         return (err < 0) ? err : 0;
  82 }
  83
  84 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
  85 {
  86         int err;
  87
  88         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
  89
  90         return (err < 0) ? err : 0;
  91 }
  92
  93 static int rtl8201_config_intr(struct phy_device *phydev)
  94 {
  95         u16 val;
  96
  97         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  98                 val = BIT(13) | BIT(12) | BIT(11);
  99         else
 100                 val = 0;
 101
 102         return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 103 }
 104
 105 static int rtl8211b_config_intr(struct phy_device *phydev)
 106 {
 107         int err;
 108
 109         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 110                 err = phy_write(phydev, RTL821x_INER,
 111                                 RTL8211B_INER_INIT);
 112         else
 113                 err = phy_write(phydev, RTL821x_INER, 0);
 114
 115         return err;
 116 }
 117
 118 static int rtl8211e_config_intr(struct phy_device *phydev)
 119 {
 120         int err;
 121
 122         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 123                 err = phy_write(phydev, RTL821x_INER,
 124                                 RTL8211E_INER_LINK_STATUS);
 125         else
 126                 err = phy_write(phydev, RTL821x_INER, 0);
 127
 128         return err;
 129 }
 130
 131 static int rtl8211f_config_intr(struct phy_device *phydev)
 132 {
 133         u16 val;
 134
 135         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 136                 val = RTL8211F_INER_LINK_STATUS;
 137         else
 138                 val = 0;
 139
 140         return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 141 }
 142
 143 static int rtl8211_config_aneg(struct phy_device *phydev)
 144 {
 145         int ret;
 146
 147         ret = genphy_config_aneg(phydev);
 148         if (ret < 0)
 149                 return ret;
 150
 151         /* Quirk was copied from vendor driver. Unfortunately it includes no
 152          * description of the magic numbers.
 153          */
 154         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 155                 phy_write(phydev, 0x17, 0x2138);
 156                 phy_write(phydev, 0x0e, 0x0260);
 157         } else {
 158                 phy_write(phydev, 0x17, 0x2108);
 159                 phy_write(phydev, 0x0e, 0x0000);
 160         }
 161
 162         return 0;
 163 }
 164
 165 static int rtl8211c_config_init(struct phy_device *phydev)
 166 {
 167         /* RTL8211C has an issue when operating in Gigabit slave mode */
 168         return phy_set_bits(phydev, MII_CTRL1000,
 169                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 170 }
 171
 172 static int rtl8211f_config_init(struct phy_device *phydev)
 173 {
 174         struct device *dev = &phydev->mdio.dev;
 175         u16 val;
 176         int ret;
 177
 178         /* enable TX-delay for rgmii-{id,txid}, and disable it for rgmii and
 179          * rgmii-rxid. The RX-delay can be enabled by the external RXDLY pin.
 180          */
 181         switch (phydev->interface) {
 182         case PHY_INTERFACE_MODE_RGMII:
 183         case PHY_INTERFACE_MODE_RGMII_RXID:
 184                 val = 0;
 185                 break;
 186         case PHY_INTERFACE_MODE_RGMII_ID:
 187         case PHY_INTERFACE_MODE_RGMII_TXID:
 188                 val = RTL8211F_TX_DELAY;
 189                 break;
 190         default: /* the rest of the modes imply leaving delay as is. */
 191                 return 0;
 192         }
 193
 194         ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
 195                                        val);
 196         if (ret < 0) {
 197                 dev_err(dev, "Failed to update the TX delay register\n");
 198                 return ret;
 199         } else if (ret) {
 200                 dev_dbg(dev,
 201                         "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
 202                         val ? "Enabling" : "Disabling");
 203         } else {
 204                 dev_dbg(dev,
 205                         "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
 206                         val ? "enabled" : "disabled");
 207         }
 208
 209         return 0;
 210 }
 211
 212 static int rtl8211e_config_init(struct phy_device *phydev)
 213 {
 214         int ret = 0, oldpage;
 215         u16 val;
 216
 217         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 218         switch (phydev->interface) {
 219         case PHY_INTERFACE_MODE_RGMII:
 220                 val = 0;
 221                 break;
 222         case PHY_INTERFACE_MODE_RGMII_ID:
 223                 val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 224                 break;
 225         case PHY_INTERFACE_MODE_RGMII_RXID:
 226                 val = RTL8211E_RX_DELAY;
 227                 break;
 228         case PHY_INTERFACE_MODE_RGMII_TXID:
 229                 val = RTL8211E_TX_DELAY;
 230                 break;
 231         default: /* the rest of the modes imply leaving delays as is. */
 232                 return 0;
 233         }
 234
 235         /* According to a sample driver there is a 0x1c config register on the
 236          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 237          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
 238          * also be used to customize the whole configuration register:
 239          * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
 240          * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
 241          * for details).
 242          */
 243         oldpage = phy_select_page(phydev, 0x7);
 244         if (oldpage < 0)
 245                 goto err_restore_page;
 246
 247         ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 248         if (ret)
 249                 goto err_restore_page;
 250
 251         ret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 252                            val);
 253
 254 err_restore_page:
 255         return phy_restore_page(phydev, oldpage, ret);
 256 }
 257
 258 static int rtl8211b_suspend(struct phy_device *phydev)
 259 {
 260         phy_write(phydev, MII_MMD_DATA, BIT(9));
 261
 262         return genphy_suspend(phydev);
 263 }
 264
 265 static int rtl8211b_resume(struct phy_device *phydev)
 266 {
 267         phy_write(phydev, MII_MMD_DATA, 0);
 268
 269         return genphy_resume(phydev);
 270 }
 271
 272 static int rtl8366rb_config_init(struct phy_device *phydev)
 273 {
 274         int ret;
 275
 276         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 277                            RTL8366RB_POWER_SAVE_ON);
 278         if (ret) {
 279                 dev_err(&phydev->mdio.dev,
 280                         "error enabling power management\n");
 281         }
 282
 283         return ret;
 284 }
 285
 286 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 287 {
 288         int ret;
 289
 290         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
 291                 rtl821x_write_page(phydev, 0xa5c);
 292                 ret = __phy_read(phydev, 0x12);
 293                 rtl821x_write_page(phydev, 0);
 294         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 295                 rtl821x_write_page(phydev, 0xa5d);
 296                 ret = __phy_read(phydev, 0x10);
 297                 rtl821x_write_page(phydev, 0);
 298         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
 299                 rtl821x_write_page(phydev, 0xa5d);
 300                 ret = __phy_read(phydev, 0x11);
 301                 rtl821x_write_page(phydev, 0);
 302         } else {
 303                 ret = -EOPNOTSUPP;
 304         }
 305
 306         return ret;
 307 }
 308
 309 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 310                             u16 val)
 311 {
 312         int ret;
 313
 314         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 315                 rtl821x_write_page(phydev, 0xa5d);
 316                 ret = __phy_write(phydev, 0x10, val);
 317                 rtl821x_write_page(phydev, 0);
 318         } else {
 319                 ret = -EOPNOTSUPP;
 320         }
 321
 322         return ret;
 323 }
 324
 325 static int rtl8125_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 326 {
 327         int ret = rtlgen_read_mmd(phydev, devnum, regnum);
 328
 329         if (ret != -EOPNOTSUPP)
 330                 return ret;
 331
 332         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
 333                 rtl821x_write_page(phydev, 0xa6e);
 334                 ret = __phy_read(phydev, 0x16);
 335                 rtl821x_write_page(phydev, 0);
 336         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 337                 rtl821x_write_page(phydev, 0xa6d);
 338                 ret = __phy_read(phydev, 0x12);
 339                 rtl821x_write_page(phydev, 0);
 340         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
 341                 rtl821x_write_page(phydev, 0xa6d);
 342                 ret = __phy_read(phydev, 0x10);
 343                 rtl821x_write_page(phydev, 0);
 344         }
 345
 346         return ret;
 347 }
 348
 349 static int rtl8125_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 350                              u16 val)
 351 {
 352         int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
 353
 354         if (ret != -EOPNOTSUPP)
 355                 return ret;
 356
 357         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 358                 rtl821x_write_page(phydev, 0xa6d);
 359                 ret = __phy_write(phydev, 0x12, val);
 360                 rtl821x_write_page(phydev, 0);
 361         }
 362
 363         return ret;
 364 }
 365
 366 static int rtl8125_get_features(struct phy_device *phydev)
 367 {
 368         int val;
 369
 370         val = phy_read_paged(phydev, 0xa61, 0x13);
 371         if (val < 0)
 372                 return val;
 373
 374         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 375                          phydev->supported, val & RTL_SUPPORTS_2500FULL);
 376         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 377                          phydev->supported, val & RTL_SUPPORTS_5000FULL);
 378         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 379                          phydev->supported, val & RTL_SUPPORTS_10000FULL);
 380
 381         return genphy_read_abilities(phydev);
 382 }
 383
 384 static int rtl8125_config_aneg(struct phy_device *phydev)
 385 {
 386         int ret = 0;
 387
 388         if (phydev->autoneg == AUTONEG_ENABLE) {
 389                 u16 adv2500 = 0;
 390
 391                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 392                                       phydev->advertising))
 393                         adv2500 = RTL_ADV_2500FULL;
 394
 395                 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
 396                                                RTL_ADV_2500FULL, adv2500);
 397                 if (ret < 0)
 398                         return ret;
 399         }
 400
 401         return __genphy_config_aneg(phydev, ret);
 402 }
 403
 404 static int rtl8125_read_status(struct phy_device *phydev)
 405 {
 406         if (phydev->autoneg == AUTONEG_ENABLE) {
 407                 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
 408
 409                 if (lpadv < 0)
 410                         return lpadv;
 411
 412                 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 413                         phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
 414                 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 415                         phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
 416                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 417                         phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
 418         }
 419
 420         return genphy_read_status(phydev);
 421 }
 422
 423 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
 424 {
 425         int val;
 426
 427         phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
 428         val = phy_read(phydev, 0x13);
 429         phy_write(phydev, RTL821x_PAGE_SELECT, 0);
 430
 431         return val >= 0 && val & RTL_SUPPORTS_2500FULL;
 432 }
 433
 434 static int rtlgen_match_phy_device(struct phy_device *phydev)
 435 {
 436         return phydev->phy_id == RTL_GENERIC_PHYID &&
 437                !rtlgen_supports_2_5gbps(phydev);
 438 }
 439
 440 static int rtl8125_match_phy_device(struct phy_device *phydev)
 441 {
 442         return phydev->phy_id == RTL_GENERIC_PHYID &&
 443                rtlgen_supports_2_5gbps(phydev);
 444 }
 445
 446 static struct phy_driver realtek_drvs[] = {
 447         {
 448                 PHY_ID_MATCH_EXACT(0x00008201),
 449                 .name           = "RTL8201CP Ethernet",
 450         }, {
 451                 PHY_ID_MATCH_EXACT(0x001cc816),
 452                 .name           = "RTL8201F Fast Ethernet",
 453                 .ack_interrupt  = &rtl8201_ack_interrupt,
 454                 .config_intr    = &rtl8201_config_intr,
 455                 .suspend        = genphy_suspend,
 456                 .resume         = genphy_resume,
 457                 .read_page      = rtl821x_read_page,
 458                 .write_page     = rtl821x_write_page,
 459         }, {
 460                 PHY_ID_MATCH_MODEL(0x001cc880),
 461                 .name           = "RTL8208 Fast Ethernet",
 462                 .read_mmd       = genphy_read_mmd_unsupported,
 463                 .write_mmd      = genphy_write_mmd_unsupported,
 464                 .suspend        = genphy_suspend,
 465                 .resume         = genphy_resume,
 466                 .read_page      = rtl821x_read_page,
 467                 .write_page     = rtl821x_write_page,
 468         }, {
 469                 PHY_ID_MATCH_EXACT(0x001cc910),
 470                 .name           = "RTL8211 Gigabit Ethernet",
 471                 .config_aneg    = rtl8211_config_aneg,
 472                 .read_mmd       = &genphy_read_mmd_unsupported,
 473                 .write_mmd      = &genphy_write_mmd_unsupported,
 474                 .read_page      = rtl821x_read_page,
 475                 .write_page     = rtl821x_write_page,
 476         }, {
 477                 PHY_ID_MATCH_EXACT(0x001cc912),
 478                 .name           = "RTL8211B Gigabit Ethernet",
 479                 .ack_interrupt  = &rtl821x_ack_interrupt,
 480                 .config_intr    = &rtl8211b_config_intr,
 481                 .read_mmd       = &genphy_read_mmd_unsupported,
 482                 .write_mmd      = &genphy_write_mmd_unsupported,
 483                 .suspend        = rtl8211b_suspend,
 484                 .resume         = rtl8211b_resume,
 485                 .read_page      = rtl821x_read_page,
 486                 .write_page     = rtl821x_write_page,
 487         }, {
 488                 PHY_ID_MATCH_EXACT(0x001cc913),
 489                 .name           = "RTL8211C Gigabit Ethernet",
 490                 .config_init    = rtl8211c_config_init,
 491                 .read_mmd       = &genphy_read_mmd_unsupported,
 492                 .write_mmd      = &genphy_write_mmd_unsupported,
 493                 .read_page      = rtl821x_read_page,
 494                 .write_page     = rtl821x_write_page,
 495         }, {
 496                 PHY_ID_MATCH_EXACT(0x001cc914),
 497                 .name           = "RTL8211DN Gigabit Ethernet",
 498                 .ack_interrupt  = rtl821x_ack_interrupt,
 499                 .config_intr    = rtl8211e_config_intr,
 500                 .suspend        = genphy_suspend,
 501                 .resume         = genphy_resume,
 502                 .read_page      = rtl821x_read_page,
 503                 .write_page     = rtl821x_write_page,
 504         }, {
 505                 PHY_ID_MATCH_EXACT(0x001cc915),
 506                 .name           = "RTL8211E Gigabit Ethernet",
 507                 .config_init    = &rtl8211e_config_init,
 508                 .ack_interrupt  = &rtl821x_ack_interrupt,
 509                 .config_intr    = &rtl8211e_config_intr,
 510                 .suspend        = genphy_suspend,
 511                 .resume         = genphy_resume,
 512                 .read_page      = rtl821x_read_page,
 513                 .write_page     = rtl821x_write_page,
 514         }, {
 515                 PHY_ID_MATCH_EXACT(0x001cc916),
 516                 .name           = "RTL8211F Gigabit Ethernet",
 517                 .config_init    = &rtl8211f_config_init,
 518                 .ack_interrupt  = &rtl8211f_ack_interrupt,
 519                 .config_intr    = &rtl8211f_config_intr,
 520                 .suspend        = genphy_suspend,
 521                 .resume         = genphy_resume,
 522                 .read_page      = rtl821x_read_page,
 523                 .write_page     = rtl821x_write_page,
 524         }, {
 525                 .name           = "Generic FE-GE Realtek PHY",
 526                 .match_phy_device = rtlgen_match_phy_device,
 527                 .suspend        = genphy_suspend,
 528                 .resume         = genphy_resume,
 529                 .read_page      = rtl821x_read_page,
 530                 .write_page     = rtl821x_write_page,
 531                 .read_mmd       = rtlgen_read_mmd,
 532                 .write_mmd      = rtlgen_write_mmd,
 533         }, {
 534                 .name           = "RTL8125 2.5Gbps internal",
 535                 .match_phy_device = rtl8125_match_phy_device,
 536                 .get_features   = rtl8125_get_features,
 537                 .config_aneg    = rtl8125_config_aneg,
 538                 .read_status    = rtl8125_read_status,
 539                 .suspend        = genphy_suspend,
 540                 .resume         = genphy_resume,
 541                 .read_page      = rtl821x_read_page,
 542                 .write_page     = rtl821x_write_page,
 543                 .read_mmd       = rtl8125_read_mmd,
 544                 .write_mmd      = rtl8125_write_mmd,
 545         }, {
 546                 PHY_ID_MATCH_EXACT(0x001cc961),
 547                 .name           = "RTL8366RB Gigabit Ethernet",
 548                 .config_init    = &rtl8366rb_config_init,
 549                 /* These interrupts are handled by the irq controller
 550                  * embedded inside the RTL8366RB, they get unmasked when the
 551                  * irq is requested and ACKed by reading the status register,
 552                  * which is done by the irqchip code.
 553                  */
 554                 .ack_interrupt  = genphy_no_ack_interrupt,
 555                 .config_intr    = genphy_no_config_intr,
 556                 .suspend        = genphy_suspend,
 557                 .resume         = genphy_resume,
 558         },
 559 };
 560
 561 module_phy_driver(realtek_drvs);
 562
 563 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
 564         { PHY_ID_MATCH_VENDOR(0x001cc800) },
 565         { }
 566 };
 567
 568 MODULE_DEVICE_TABLE(mdio, realtek_tbl);