1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
7 * Copyright 2016 Karsten Merker <merker@debian.org>
10 #include <linux/bitops.h>
12 #include <linux/delay.h>
14 #define PHY_RTL8211x_FORCE_MASTER BIT(1)
15 #define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3)
16 #define PHY_RTL8201F_S700_RMII_TIMINGS BIT(4)
18 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
20 /* RTL8211x 1000BASE-T Control Register */
21 #define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
22 #define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
24 /* RTL8211x PHY Status Register */
25 #define MIIM_RTL8211x_PHY_STATUS 0x11
26 #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
27 #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
28 #define MIIM_RTL8211x_PHYSTAT_100 0x4000
29 #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
30 #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
31 #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
33 /* RTL8211x PHY Interrupt Enable Register */
34 #define MIIM_RTL8211x_PHY_INER 0x12
35 #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
36 #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
38 /* RTL8211x PHY Interrupt Status Register */
39 #define MIIM_RTL8211x_PHY_INSR 0x13
41 /* RTL8211F PHY Status Register */
42 #define MIIM_RTL8211F_PHY_STATUS 0x1a
43 #define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000
44 #define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030
45 #define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020
46 #define MIIM_RTL8211F_PHYSTAT_100 0x0010
47 #define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008
48 #define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
49 #define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
51 #define MIIM_RTL8211E_CONFREG 0x1c
52 #define MIIM_RTL8211E_CTRL_DELAY BIT(13)
53 #define MIIM_RTL8211E_TX_DELAY BIT(12)
54 #define MIIM_RTL8211E_RX_DELAY BIT(11)
56 #define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
58 #define MIIM_RTL8211F_PAGE_SELECT 0x1f
59 #define MIIM_RTL8211F_TX_DELAY 0x100
60 #define MIIM_RTL8211F_RX_DELAY 0x8
61 #define MIIM_RTL8211F_LCR 0x10
63 #define RTL8201F_RMSR 0x10
65 #define RMSR_RX_TIMING_SHIFT BIT(2)
66 #define RMSR_RX_TIMING_MASK GENMASK(7, 4)
67 #define RMSR_RX_TIMING_VAL 0x4
68 #define RMSR_TX_TIMING_SHIFT BIT(3)
69 #define RMSR_TX_TIMING_MASK GENMASK(11, 8)
70 #define RMSR_TX_TIMING_VAL 0x5
72 static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
73 int devaddr, int regnum)
75 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
76 MIIM_RTL8211F_PAGE_SELECT);
79 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
80 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
81 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
86 static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
87 int devaddr, int regnum, u16 val)
89 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
90 MIIM_RTL8211F_PAGE_SELECT);
92 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
93 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
94 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
99 static int rtl8211b_probe(struct phy_device *phydev)
101 #ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
102 phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
108 static int rtl8211e_probe(struct phy_device *phydev)
113 static int rtl8211f_probe(struct phy_device *phydev)
115 #ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON
116 phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON;
122 static int rtl8210f_probe(struct phy_device *phydev)
124 #ifdef CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS
125 phydev->flags |= PHY_RTL8201F_S700_RMII_TIMINGS;
131 /* RealTek RTL8211x */
132 static int rtl8211x_config(struct phy_device *phydev)
134 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
136 /* mask interrupt at init; if the interrupt is
137 * needed indeed, it should be explicitly enabled
139 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
140 MIIM_RTL8211x_PHY_INTR_DIS);
142 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
145 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
146 /* force manual master/slave configuration */
147 reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
148 /* force master mode */
149 reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
150 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
152 /* read interrupt status just to clear it */
153 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
155 genphy_config_aneg(phydev);
160 /* RealTek RTL8201F */
161 static int rtl8201f_config(struct phy_device *phydev)
165 if (phydev->flags & PHY_RTL8201F_S700_RMII_TIMINGS) {
166 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
168 reg = phy_read(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR);
169 reg &= ~(RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK);
170 /* Set the needed Rx/Tx Timings for proper PHY operation */
171 reg |= (RMSR_RX_TIMING_VAL << RMSR_RX_TIMING_SHIFT)
172 | (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT);
173 phy_write(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR, reg);
174 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
178 genphy_config_aneg(phydev);
183 static int rtl8211e_config(struct phy_device *phydev)
187 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
188 switch (phydev->interface) {
189 case PHY_INTERFACE_MODE_RGMII:
190 val = MIIM_RTL8211E_CTRL_DELAY;
192 case PHY_INTERFACE_MODE_RGMII_ID:
193 val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_TX_DELAY |
194 MIIM_RTL8211E_RX_DELAY;
196 case PHY_INTERFACE_MODE_RGMII_RXID:
197 val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_RX_DELAY;
199 case PHY_INTERFACE_MODE_RGMII_TXID:
200 val = MIIM_RTL8211E_CTRL_DELAY | MIIM_RTL8211E_TX_DELAY;
202 default: /* the rest of the modes imply leaving delays as is. */
206 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 7);
207 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
209 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
210 reg &= ~(MIIM_RTL8211E_TX_DELAY | MIIM_RTL8211E_RX_DELAY);
211 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg | val);
213 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0);
216 genphy_config_aneg(phydev);
221 static int rtl8211f_config(struct phy_device *phydev)
225 if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) {
228 reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
229 reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN;
230 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg);
233 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
235 phy_write(phydev, MDIO_DEVAD_NONE,
236 MIIM_RTL8211F_PAGE_SELECT, 0xd08);
237 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
239 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
240 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
241 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
242 reg |= MIIM_RTL8211F_TX_DELAY;
244 reg &= ~MIIM_RTL8211F_TX_DELAY;
246 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
248 /* enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it */
249 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
250 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
251 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
252 reg |= MIIM_RTL8211F_RX_DELAY;
254 reg &= ~MIIM_RTL8211F_RX_DELAY;
255 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg);
257 /* restore to default page 0 */
258 phy_write(phydev, MDIO_DEVAD_NONE,
259 MIIM_RTL8211F_PAGE_SELECT, 0x0);
261 /* Set green LED for Link, yellow LED for Active */
262 phy_write(phydev, MDIO_DEVAD_NONE,
263 MIIM_RTL8211F_PAGE_SELECT, 0xd04);
264 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
265 phy_write(phydev, MDIO_DEVAD_NONE,
266 MIIM_RTL8211F_PAGE_SELECT, 0x0);
268 genphy_config_aneg(phydev);
273 static int rtl8211x_parse_status(struct phy_device *phydev)
276 unsigned int mii_reg;
278 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
280 if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
283 /* in case of timeout ->link is cleared */
285 puts("Waiting for PHY realtime link");
286 while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
287 /* Timeout reached ? */
288 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
289 puts(" TIMEOUT !\n");
294 if ((i++ % 1000) == 0)
296 udelay(1000); /* 1 ms */
297 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
298 MIIM_RTL8211x_PHY_STATUS);
301 udelay(500000); /* another 500 ms (results in faster booting) */
303 if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
309 if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
310 phydev->duplex = DUPLEX_FULL;
312 phydev->duplex = DUPLEX_HALF;
314 speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
317 case MIIM_RTL8211x_PHYSTAT_GBIT:
318 phydev->speed = SPEED_1000;
320 case MIIM_RTL8211x_PHYSTAT_100:
321 phydev->speed = SPEED_100;
324 phydev->speed = SPEED_10;
330 static int rtl8211f_parse_status(struct phy_device *phydev)
333 unsigned int mii_reg;
336 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43);
337 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS);
340 while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) {
341 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
342 puts(" TIMEOUT !\n");
347 if ((i++ % 1000) == 0)
350 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
351 MIIM_RTL8211F_PHY_STATUS);
354 if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX)
355 phydev->duplex = DUPLEX_FULL;
357 phydev->duplex = DUPLEX_HALF;
359 speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED);
362 case MIIM_RTL8211F_PHYSTAT_GBIT:
363 phydev->speed = SPEED_1000;
365 case MIIM_RTL8211F_PHYSTAT_100:
366 phydev->speed = SPEED_100;
369 phydev->speed = SPEED_10;
375 static int rtl8211x_startup(struct phy_device *phydev)
379 /* Read the Status (2x to make sure link is right) */
380 ret = genphy_update_link(phydev);
384 return rtl8211x_parse_status(phydev);
387 static int rtl8211e_startup(struct phy_device *phydev)
391 ret = genphy_update_link(phydev);
395 return genphy_parse_link(phydev);
398 static int rtl8211f_startup(struct phy_device *phydev)
402 /* Read the Status (2x to make sure link is right) */
403 ret = genphy_update_link(phydev);
406 /* Read the Status (2x to make sure link is right) */
408 return rtl8211f_parse_status(phydev);
411 /* Support for RTL8211B PHY */
412 static struct phy_driver RTL8211B_driver = {
413 .name = "RealTek RTL8211B",
416 .features = PHY_GBIT_FEATURES,
417 .probe = &rtl8211b_probe,
418 .config = &rtl8211x_config,
419 .startup = &rtl8211x_startup,
420 .shutdown = &genphy_shutdown,
423 /* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
424 static struct phy_driver RTL8211E_driver = {
425 .name = "RealTek RTL8211E",
428 .features = PHY_GBIT_FEATURES,
429 .probe = &rtl8211e_probe,
430 .config = &rtl8211e_config,
431 .startup = &rtl8211e_startup,
432 .shutdown = &genphy_shutdown,
435 /* Support for RTL8211DN PHY */
436 static struct phy_driver RTL8211DN_driver = {
437 .name = "RealTek RTL8211DN",
440 .features = PHY_GBIT_FEATURES,
441 .config = &rtl8211x_config,
442 .startup = &rtl8211x_startup,
443 .shutdown = &genphy_shutdown,
446 /* Support for RTL8211F PHY */
447 static struct phy_driver RTL8211F_driver = {
448 .name = "RealTek RTL8211F",
451 .features = PHY_GBIT_FEATURES,
452 .probe = &rtl8211f_probe,
453 .config = &rtl8211f_config,
454 .startup = &rtl8211f_startup,
455 .shutdown = &genphy_shutdown,
456 .readext = &rtl8211f_phy_extread,
457 .writeext = &rtl8211f_phy_extwrite,
460 /* Support for RTL8201F PHY */
461 static struct phy_driver RTL8201F_driver = {
462 .name = "RealTek RTL8201F 10/100Mbps Ethernet",
465 .features = PHY_BASIC_FEATURES,
466 .probe = &rtl8210f_probe,
467 .config = &rtl8201f_config,
468 .startup = &rtl8211e_startup,
469 .shutdown = &genphy_shutdown,
472 int phy_realtek_init(void)
474 phy_register(&RTL8211B_driver);
475 phy_register(&RTL8211E_driver);
476 phy_register(&RTL8211F_driver);
477 phy_register(&RTL8211DN_driver);
478 phy_register(&RTL8201F_driver);