1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2021 Maxlinear Corporation
3 * Copyright (C) 2020 Intel Corporation
5 * Drivers for Maxlinear Ethernet GPY
9 #include <linux/module.h>
10 #include <linux/bitfield.h>
11 #include <linux/hwmon.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/polynomial.h>
15 #include <linux/property.h>
16 #include <linux/netdevice.h>
19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC
20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9
21 #define PHY_ID_GPY2xx 0x67C9DC00
22 #define PHY_ID_GPY115B 0x67C9DF00
23 #define PHY_ID_GPY115C 0x67C9DF10
24 #define PHY_ID_GPY211B 0x67C9DE08
25 #define PHY_ID_GPY211C 0x67C9DE10
26 #define PHY_ID_GPY212B 0x67C9DE09
27 #define PHY_ID_GPY212C 0x67C9DE20
28 #define PHY_ID_GPY215B 0x67C9DF04
29 #define PHY_ID_GPY215C 0x67C9DF20
30 #define PHY_ID_GPY241B 0x67C9DE40
31 #define PHY_ID_GPY241BM 0x67C9DE80
32 #define PHY_ID_GPY245B 0x67C9DEC0
35 #define PHY_CTL1_MDICD BIT(3)
36 #define PHY_CTL1_MDIAB BIT(2)
37 #define PHY_CTL1_AMDIX BIT(0)
38 #define PHY_MIISTAT 0x18 /* MII state */
39 #define PHY_IMASK 0x19 /* interrupt mask */
40 #define PHY_ISTAT 0x1A /* interrupt status */
41 #define PHY_FWV 0x1E /* firmware version */
43 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
44 #define PHY_MIISTAT_DPX BIT(3)
45 #define PHY_MIISTAT_LS BIT(10)
47 #define PHY_MIISTAT_SPD_10 0
48 #define PHY_MIISTAT_SPD_100 1
49 #define PHY_MIISTAT_SPD_1000 2
50 #define PHY_MIISTAT_SPD_2500 4
52 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
53 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
54 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
55 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */
56 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */
57 #define PHY_IMASK_LSTC BIT(0) /* Link state change */
58 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \
64 #define PHY_FWV_REL_MASK BIT(15)
65 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8)
66 #define PHY_FWV_MINOR_MASK GENMASK(7, 0)
68 #define PHY_PMA_MGBT_POLARITY 0x82
69 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0)
70 #define PHY_MDI_MDI_X_NORMAL 0x3
71 #define PHY_MDI_MDI_X_AB 0x2
72 #define PHY_MDI_MDI_X_CD 0x1
73 #define PHY_MDI_MDI_X_CROSS 0x0
76 #define VSPEC1_SGMII_CTRL 0x08
77 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
78 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
79 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
80 VSPEC1_SGMII_CTRL_ANRS)
82 /* Temperature sensor */
83 #define VSPEC1_TEMP_STA 0x0E
84 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0)
87 #define VSPEC1_MBOX_DATA 0x5
88 #define VSPEC1_MBOX_ADDRLO 0x6
89 #define VSPEC1_MBOX_CMD 0x7
90 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)
91 #define VSPEC1_MBOX_CMD_RD (0 << 8)
92 #define VSPEC1_MBOX_CMD_READY BIT(15)
95 #define VPSPEC2_WOL_CTL 0x0E06
96 #define VPSPEC2_WOL_AD01 0x0E08
97 #define VPSPEC2_WOL_AD23 0x0E09
98 #define VPSPEC2_WOL_AD45 0x0E0A
101 /* Internal registers, access via mbox */
102 #define REG_GPIO0_OUT 0xd3ce00
105 /* serialize mailbox acesses */
106 struct mutex mbox_lock;
111 /* It takes 3 seconds to fully switch out of loopback mode before
112 * it can safely re-enter loopback mode. Record the time when
113 * loopback is disabled. Check and wait if necessary before loopback
119 static const struct {
122 } ver_need_sgmii_reaneg[] = {
128 #if IS_ENABLED(CONFIG_HWMON)
129 /* The original translation formulae of the temperature (in degrees of Celsius)
132 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
133 * 3.0762e-1*(N^1) + -5.2156e1
135 * where [-52.156, 137.961]C and N = [0, 1023].
137 * They must be accordingly altered to be suitable for the integer arithmetics.
138 * The technique is called 'factor redistribution', which just makes sure the
139 * multiplications and divisions are made so to have a result of the operations
140 * within the integer numbers limit. In addition we need to translate the
141 * formulae to accept millidegrees of Celsius. Here what it looks like after
144 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
145 * 307620e-3*(N^1) + -52156
147 * where T = [-52156, 137961]mC and N = [0, 1023].
149 static const struct polynomial poly_N_to_temp = {
151 {4, -25761, 1000, 1},
153 {2, -191650, 1000, 1},
154 {1, 307620, 1000, 1},
159 static int gpy_hwmon_read(struct device *dev,
160 enum hwmon_sensor_types type,
161 u32 attr, int channel, long *value)
163 struct phy_device *phydev = dev_get_drvdata(dev);
166 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
172 *value = polynomial_calc(&poly_N_to_temp,
173 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret));
178 static umode_t gpy_hwmon_is_visible(const void *data,
179 enum hwmon_sensor_types type,
180 u32 attr, int channel)
185 static const struct hwmon_channel_info * const gpy_hwmon_info[] = {
186 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
190 static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
191 .is_visible = gpy_hwmon_is_visible,
192 .read = gpy_hwmon_read,
195 static const struct hwmon_chip_info gpy_hwmon_chip_info = {
196 .ops = &gpy_hwmon_hwmon_ops,
197 .info = gpy_hwmon_info,
200 static int gpy_hwmon_register(struct phy_device *phydev)
202 struct device *dev = &phydev->mdio.dev;
203 struct device *hwmon_dev;
206 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
207 if (IS_ERR(hwmon_name))
208 return PTR_ERR(hwmon_name);
210 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
212 &gpy_hwmon_chip_info,
215 return PTR_ERR_OR_ZERO(hwmon_dev);
218 static int gpy_hwmon_register(struct phy_device *phydev)
224 static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
226 struct gpy_priv *priv = phydev->priv;
230 mutex_lock(&priv->mbox_lock);
232 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
237 cmd = VSPEC1_MBOX_CMD_RD;
238 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16);
240 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
244 /* The mbox read is used in the interrupt workaround. It was observed
245 * that a read might take up to 2.5ms. This is also the time for which
246 * the interrupt line is stuck low. To be on the safe side, poll the
247 * ready bit for 10ms.
249 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
250 VSPEC1_MBOX_CMD, val,
251 (val & VSPEC1_MBOX_CMD_READY),
256 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
259 mutex_unlock(&priv->mbox_lock);
263 static int gpy_config_init(struct phy_device *phydev)
267 /* Mask all interrupts */
268 ret = phy_write(phydev, PHY_IMASK, 0);
272 /* Clear all pending interrupts */
273 ret = phy_read(phydev, PHY_ISTAT);
274 return ret < 0 ? ret : 0;
277 static bool gpy_has_broken_mdint(struct phy_device *phydev)
279 /* At least these PHYs are known to have broken interrupt handling */
280 return phydev->drv->phy_id == PHY_ID_GPY215B ||
281 phydev->drv->phy_id == PHY_ID_GPY215C;
284 static int gpy_probe(struct phy_device *phydev)
286 struct device *dev = &phydev->mdio.dev;
287 struct gpy_priv *priv;
291 if (!phydev->is_c45) {
292 ret = phy_get_c45_ids(phydev);
297 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
301 mutex_init(&priv->mbox_lock);
303 if (gpy_has_broken_mdint(phydev) &&
304 !device_property_present(dev, "maxlinear,use-broken-interrupts"))
305 phydev->dev_flags |= PHY_F_NO_IRQ;
307 fw_version = phy_read(phydev, PHY_FWV);
310 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version);
311 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
313 ret = gpy_hwmon_register(phydev);
317 /* Show GPY PHY FW version in dmesg */
318 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
319 priv->fw_major, priv->fw_minor, fw_version,
320 fw_version & PHY_FWV_REL_MASK ? "" : " test version");
325 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
327 struct gpy_priv *priv = phydev->priv;
330 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
331 if (priv->fw_major != ver_need_sgmii_reaneg[i].major)
333 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
341 static bool gpy_2500basex_chk(struct phy_device *phydev)
345 ret = phy_read(phydev, PHY_MIISTAT);
347 phydev_err(phydev, "Error: MDIO register access failed: %d\n",
352 if (!(ret & PHY_MIISTAT_LS) ||
353 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
356 phydev->speed = SPEED_2500;
357 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
358 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
359 VSPEC1_SGMII_CTRL_ANEN, 0);
363 static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
367 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
369 phydev_err(phydev, "Error: MMD register access failed: %d\n",
374 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
377 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl)
383 case ETH_TP_MDI_AUTO:
384 val = PHY_CTL1_AMDIX;
387 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD);
396 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB |
397 PHY_CTL1_MDICD, val);
401 return genphy_c45_restart_aneg(phydev);
404 static int gpy_config_aneg(struct phy_device *phydev)
406 bool changed = false;
410 if (phydev->autoneg == AUTONEG_DISABLE) {
411 /* Configure half duplex with genphy_setup_forced,
412 * because genphy_c45_pma_setup_forced does not support.
414 return phydev->duplex != DUPLEX_FULL
415 ? genphy_setup_forced(phydev)
416 : genphy_c45_pma_setup_forced(phydev);
419 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl);
423 ret = genphy_c45_an_config_aneg(phydev);
429 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
430 ret = phy_modify_changed(phydev, MII_CTRL1000,
431 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
438 ret = genphy_c45_check_and_restart_aneg(phydev, changed);
442 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
443 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
446 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
449 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
450 !gpy_sgmii_aneg_en(phydev))
453 /* There is a design constraint in GPY2xx device where SGMII AN is
454 * only triggered when there is change of speed. If, PHY link
455 * partner`s speed is still same even after PHY TPI is down and up
456 * again, SGMII AN is not triggered and hence no new in-band message
457 * from GPY to MAC side SGMII.
458 * This could cause an issue during power up, when PHY is up prior to
459 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
460 * wouldn`t receive new in-band message from GPY with correct link
461 * status, speed and duplex info.
463 * 1) If PHY is already up and TPI link status is still down (such as
464 * hard reboot), TPI link status is polled for 4 seconds before
465 * retriggerring SGMII AN.
466 * 2) If PHY is already up and TPI link status is also up (such as soft
467 * reboot), polling of TPI link status is not needed and SGMII AN is
468 * immediately retriggered.
469 * 3) Other conditions such as PHY is down, speed change etc, skip
470 * retriggering SGMII AN. Note: in case of speed change, GPY FW will
474 if (phydev->state != PHY_UP)
477 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
478 20000, 4000000, false);
479 if (ret == -ETIMEDOUT)
484 /* Trigger SGMII AN. */
485 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
486 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
489 static int gpy_update_mdix(struct phy_device *phydev)
493 ret = phy_read(phydev, PHY_CTL1);
497 if (ret & PHY_CTL1_AMDIX)
498 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
500 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB)
501 phydev->mdix_ctrl = ETH_TP_MDI_X;
503 phydev->mdix_ctrl = ETH_TP_MDI;
505 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY);
509 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL)
510 phydev->mdix = ETH_TP_MDI_X;
512 phydev->mdix = ETH_TP_MDI;
517 static int gpy_update_interface(struct phy_device *phydev)
521 /* Interface mode is fixed for USXGMII and integrated PHY */
522 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
523 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
526 /* Automatically switch SERDES interface between SGMII and 2500-BaseX
527 * according to speed. Disable ANEG in 2500-BaseX mode.
529 switch (phydev->speed) {
531 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
532 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
533 VSPEC1_SGMII_CTRL_ANEN, 0);
536 "Error: Disable of SGMII ANEG failed: %d\n",
544 phydev->interface = PHY_INTERFACE_MODE_SGMII;
545 if (gpy_sgmii_aneg_en(phydev))
547 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
548 * if ANEG is disabled (in 2500-BaseX mode).
550 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
551 VSPEC1_SGMII_ANEN_ANRS,
552 VSPEC1_SGMII_ANEN_ANRS);
555 "Error: Enable of SGMII ANEG failed: %d\n",
562 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) {
563 ret = genphy_read_master_slave(phydev);
568 return gpy_update_mdix(phydev);
571 static int gpy_read_status(struct phy_device *phydev)
575 ret = genphy_update_link(phydev);
579 phydev->speed = SPEED_UNKNOWN;
580 phydev->duplex = DUPLEX_UNKNOWN;
582 phydev->asym_pause = 0;
584 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
585 ret = genphy_c45_read_lpa(phydev);
589 /* Read the link partner's 1G advertisement */
590 ret = phy_read(phydev, MII_STAT1000);
593 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
594 } else if (phydev->autoneg == AUTONEG_DISABLE) {
595 linkmode_zero(phydev->lp_advertising);
598 ret = phy_read(phydev, PHY_MIISTAT);
602 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
603 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
604 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
605 case PHY_MIISTAT_SPD_10:
606 phydev->speed = SPEED_10;
608 case PHY_MIISTAT_SPD_100:
609 phydev->speed = SPEED_100;
611 case PHY_MIISTAT_SPD_1000:
612 phydev->speed = SPEED_1000;
614 case PHY_MIISTAT_SPD_2500:
615 phydev->speed = SPEED_2500;
620 ret = gpy_update_interface(phydev);
628 static int gpy_config_intr(struct phy_device *phydev)
632 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
633 mask = PHY_IMASK_MASK;
635 return phy_write(phydev, PHY_IMASK, mask);
638 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
642 reg = phy_read(phydev, PHY_ISTAT);
648 if (!(reg & PHY_IMASK_MASK))
651 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT
652 * is read. To avoid interrupt storms, delay the interrupt handling as
653 * long as the PHY drives the interrupt line. An internal bus read will
654 * stall as long as the interrupt line is asserted, thus just read a
655 * random register here.
656 * Because we cannot access the internal bus at all while the interrupt
657 * is driven by the PHY, there is no way to make the interrupt line
658 * unstuck (e.g. by changing the pinmux to GPIO input) during that time
659 * frame. Therefore, polling is the best we can do and won't do any more
661 * It was observed that this bug happens on link state and link speed
662 * changes on a GPY215B and GYP215C independent of the firmware version
663 * (which doesn't mean that this list is exhaustive).
665 if (gpy_has_broken_mdint(phydev) &&
666 (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC))) {
667 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
674 phy_trigger_machine(phydev);
679 static int gpy_set_wol(struct phy_device *phydev,
680 struct ethtool_wolinfo *wol)
682 struct net_device *attach_dev = phydev->attached_dev;
685 if (wol->wolopts & WAKE_MAGIC) {
686 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
687 * VPSPEC2_WOL_AD45 = Byte0:Byte1
688 * VPSPEC2_WOL_AD23 = Byte2:Byte3
689 * VPSPEC2_WOL_AD01 = Byte4:Byte5
691 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
693 ((attach_dev->dev_addr[0] << 8) |
694 attach_dev->dev_addr[1]));
698 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
700 ((attach_dev->dev_addr[2] << 8) |
701 attach_dev->dev_addr[3]));
705 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
707 ((attach_dev->dev_addr[4] << 8) |
708 attach_dev->dev_addr[5]));
712 /* Enable the WOL interrupt */
713 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
717 /* Enable magic packet matching */
718 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
724 /* Clear the interrupt status register.
725 * Only WoL is enabled so clear all.
727 ret = phy_read(phydev, PHY_ISTAT);
731 /* Disable magic packet matching */
732 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
739 if (wol->wolopts & WAKE_PHY) {
740 /* Enable the link state change interrupt */
741 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
745 /* Clear the interrupt status register */
746 ret = phy_read(phydev, PHY_ISTAT);
750 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
751 phy_trigger_machine(phydev);
756 /* Disable the link state change interrupt */
757 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
760 static void gpy_get_wol(struct phy_device *phydev,
761 struct ethtool_wolinfo *wol)
765 wol->supported = WAKE_MAGIC | WAKE_PHY;
768 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL);
770 wol->wolopts |= WAKE_MAGIC;
772 ret = phy_read(phydev, PHY_IMASK);
773 if (ret & PHY_IMASK_LSTC)
774 wol->wolopts |= WAKE_PHY;
777 static int gpy_loopback(struct phy_device *phydev, bool enable)
779 struct gpy_priv *priv = phydev->priv;
784 u64 now = get_jiffies_64();
786 /* wait until 3 seconds from last disable */
787 if (time_before64(now, priv->lb_dis_to))
788 msleep(jiffies64_to_msecs(priv->lb_dis_to - now));
793 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set);
798 /* It takes some time for PHY device to switch into
803 priv->lb_dis_to = get_jiffies_64() + HZ * 3;
809 static int gpy115_loopback(struct phy_device *phydev, bool enable)
811 struct gpy_priv *priv = phydev->priv;
814 return gpy_loopback(phydev, enable);
816 if (priv->fw_minor > 0x76)
817 return gpy_loopback(phydev, 0);
819 return genphy_soft_reset(phydev);
822 static struct phy_driver gpy_drivers[] = {
824 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
825 .name = "Maxlinear Ethernet GPY2xx",
826 .get_features = genphy_c45_pma_read_abilities,
827 .config_init = gpy_config_init,
829 .suspend = genphy_suspend,
830 .resume = genphy_resume,
831 .config_aneg = gpy_config_aneg,
832 .aneg_done = genphy_c45_aneg_done,
833 .read_status = gpy_read_status,
834 .config_intr = gpy_config_intr,
835 .handle_interrupt = gpy_handle_interrupt,
836 .set_wol = gpy_set_wol,
837 .get_wol = gpy_get_wol,
838 .set_loopback = gpy_loopback,
841 .phy_id = PHY_ID_GPY115B,
842 .phy_id_mask = PHY_ID_GPYx15B_MASK,
843 .name = "Maxlinear Ethernet GPY115B",
844 .get_features = genphy_c45_pma_read_abilities,
845 .config_init = gpy_config_init,
847 .suspend = genphy_suspend,
848 .resume = genphy_resume,
849 .config_aneg = gpy_config_aneg,
850 .aneg_done = genphy_c45_aneg_done,
851 .read_status = gpy_read_status,
852 .config_intr = gpy_config_intr,
853 .handle_interrupt = gpy_handle_interrupt,
854 .set_wol = gpy_set_wol,
855 .get_wol = gpy_get_wol,
856 .set_loopback = gpy115_loopback,
859 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
860 .name = "Maxlinear Ethernet GPY115C",
861 .get_features = genphy_c45_pma_read_abilities,
862 .config_init = gpy_config_init,
864 .suspend = genphy_suspend,
865 .resume = genphy_resume,
866 .config_aneg = gpy_config_aneg,
867 .aneg_done = genphy_c45_aneg_done,
868 .read_status = gpy_read_status,
869 .config_intr = gpy_config_intr,
870 .handle_interrupt = gpy_handle_interrupt,
871 .set_wol = gpy_set_wol,
872 .get_wol = gpy_get_wol,
873 .set_loopback = gpy115_loopback,
876 .phy_id = PHY_ID_GPY211B,
877 .phy_id_mask = PHY_ID_GPY21xB_MASK,
878 .name = "Maxlinear Ethernet GPY211B",
879 .get_features = genphy_c45_pma_read_abilities,
880 .config_init = gpy_config_init,
882 .suspend = genphy_suspend,
883 .resume = genphy_resume,
884 .config_aneg = gpy_config_aneg,
885 .aneg_done = genphy_c45_aneg_done,
886 .read_status = gpy_read_status,
887 .config_intr = gpy_config_intr,
888 .handle_interrupt = gpy_handle_interrupt,
889 .set_wol = gpy_set_wol,
890 .get_wol = gpy_get_wol,
891 .set_loopback = gpy_loopback,
894 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
895 .name = "Maxlinear Ethernet GPY211C",
896 .get_features = genphy_c45_pma_read_abilities,
897 .config_init = gpy_config_init,
899 .suspend = genphy_suspend,
900 .resume = genphy_resume,
901 .config_aneg = gpy_config_aneg,
902 .aneg_done = genphy_c45_aneg_done,
903 .read_status = gpy_read_status,
904 .config_intr = gpy_config_intr,
905 .handle_interrupt = gpy_handle_interrupt,
906 .set_wol = gpy_set_wol,
907 .get_wol = gpy_get_wol,
908 .set_loopback = gpy_loopback,
911 .phy_id = PHY_ID_GPY212B,
912 .phy_id_mask = PHY_ID_GPY21xB_MASK,
913 .name = "Maxlinear Ethernet GPY212B",
914 .get_features = genphy_c45_pma_read_abilities,
915 .config_init = gpy_config_init,
917 .suspend = genphy_suspend,
918 .resume = genphy_resume,
919 .config_aneg = gpy_config_aneg,
920 .aneg_done = genphy_c45_aneg_done,
921 .read_status = gpy_read_status,
922 .config_intr = gpy_config_intr,
923 .handle_interrupt = gpy_handle_interrupt,
924 .set_wol = gpy_set_wol,
925 .get_wol = gpy_get_wol,
926 .set_loopback = gpy_loopback,
929 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
930 .name = "Maxlinear Ethernet GPY212C",
931 .get_features = genphy_c45_pma_read_abilities,
932 .config_init = gpy_config_init,
934 .suspend = genphy_suspend,
935 .resume = genphy_resume,
936 .config_aneg = gpy_config_aneg,
937 .aneg_done = genphy_c45_aneg_done,
938 .read_status = gpy_read_status,
939 .config_intr = gpy_config_intr,
940 .handle_interrupt = gpy_handle_interrupt,
941 .set_wol = gpy_set_wol,
942 .get_wol = gpy_get_wol,
943 .set_loopback = gpy_loopback,
946 .phy_id = PHY_ID_GPY215B,
947 .phy_id_mask = PHY_ID_GPYx15B_MASK,
948 .name = "Maxlinear Ethernet GPY215B",
949 .get_features = genphy_c45_pma_read_abilities,
950 .config_init = gpy_config_init,
952 .suspend = genphy_suspend,
953 .resume = genphy_resume,
954 .config_aneg = gpy_config_aneg,
955 .aneg_done = genphy_c45_aneg_done,
956 .read_status = gpy_read_status,
957 .config_intr = gpy_config_intr,
958 .handle_interrupt = gpy_handle_interrupt,
959 .set_wol = gpy_set_wol,
960 .get_wol = gpy_get_wol,
961 .set_loopback = gpy_loopback,
964 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
965 .name = "Maxlinear Ethernet GPY215C",
966 .get_features = genphy_c45_pma_read_abilities,
967 .config_init = gpy_config_init,
969 .suspend = genphy_suspend,
970 .resume = genphy_resume,
971 .config_aneg = gpy_config_aneg,
972 .aneg_done = genphy_c45_aneg_done,
973 .read_status = gpy_read_status,
974 .config_intr = gpy_config_intr,
975 .handle_interrupt = gpy_handle_interrupt,
976 .set_wol = gpy_set_wol,
977 .get_wol = gpy_get_wol,
978 .set_loopback = gpy_loopback,
981 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
982 .name = "Maxlinear Ethernet GPY241B",
983 .get_features = genphy_c45_pma_read_abilities,
984 .config_init = gpy_config_init,
986 .suspend = genphy_suspend,
987 .resume = genphy_resume,
988 .config_aneg = gpy_config_aneg,
989 .aneg_done = genphy_c45_aneg_done,
990 .read_status = gpy_read_status,
991 .config_intr = gpy_config_intr,
992 .handle_interrupt = gpy_handle_interrupt,
993 .set_wol = gpy_set_wol,
994 .get_wol = gpy_get_wol,
995 .set_loopback = gpy_loopback,
998 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
999 .name = "Maxlinear Ethernet GPY241BM",
1000 .get_features = genphy_c45_pma_read_abilities,
1001 .config_init = gpy_config_init,
1003 .suspend = genphy_suspend,
1004 .resume = genphy_resume,
1005 .config_aneg = gpy_config_aneg,
1006 .aneg_done = genphy_c45_aneg_done,
1007 .read_status = gpy_read_status,
1008 .config_intr = gpy_config_intr,
1009 .handle_interrupt = gpy_handle_interrupt,
1010 .set_wol = gpy_set_wol,
1011 .get_wol = gpy_get_wol,
1012 .set_loopback = gpy_loopback,
1015 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
1016 .name = "Maxlinear Ethernet GPY245B",
1017 .get_features = genphy_c45_pma_read_abilities,
1018 .config_init = gpy_config_init,
1020 .suspend = genphy_suspend,
1021 .resume = genphy_resume,
1022 .config_aneg = gpy_config_aneg,
1023 .aneg_done = genphy_c45_aneg_done,
1024 .read_status = gpy_read_status,
1025 .config_intr = gpy_config_intr,
1026 .handle_interrupt = gpy_handle_interrupt,
1027 .set_wol = gpy_set_wol,
1028 .get_wol = gpy_get_wol,
1029 .set_loopback = gpy_loopback,
1032 module_phy_driver(gpy_drivers);
1034 static struct mdio_device_id __maybe_unused gpy_tbl[] = {
1035 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
1036 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
1037 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
1038 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
1039 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
1040 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
1041 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
1042 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
1043 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
1044 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
1045 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
1046 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
1049 MODULE_DEVICE_TABLE(mdio, gpy_tbl);
1051 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
1052 MODULE_AUTHOR("Xu Liang");
1053 MODULE_LICENSE("GPL");