1 // SPDX-License-Identifier: GPL-2.0+
4 * Elecsys Corporation <www.elecsyscorp.com>
5 * Kevin Smith <kevin.smith@elecsyscorp.com>
9 * Marvell Semiconductor <www.marvell.com>
10 * Prafulla Wadaskar <prafulla@marvell.com>
14 * PHY driver for mv88e61xx ethernet switches.
16 * This driver configures the mv88e61xx for basic use as a PHY. The switch
17 * supports a VLAN configuration that determines how traffic will be routed
18 * between the ports. This driver uses a simple configuration that routes
19 * traffic from each PHY port only to the CPU port, and from the CPU port to
22 * The configuration determines which PHY ports to activate using the
23 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
24 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
25 * connected to unless it is connected over a PHY interface (not MII).
27 * This driver was written for and tested on the mv88e6176 with an SGMII
28 * connection. Other configurations should be supported, but some additions or
29 * changes may be required.
40 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
42 #define PORT_MASK(port_count) ((1 << (port_count)) - 1)
44 /* Device addresses */
45 #define DEVADDR_PHY(p) (p)
46 #define DEVADDR_SERDES 0x0F
48 /* SMI indirection registers for multichip addressing mode */
49 #define SMI_CMD_REG 0x00
50 #define SMI_DATA_REG 0x01
52 /* Global registers */
53 #define GLOBAL1_STATUS 0x00
54 #define GLOBAL1_CTRL 0x04
55 #define GLOBAL1_MON_CTRL 0x1A
57 /* Global 2 registers */
58 #define GLOBAL2_REG_PHY_CMD 0x18
59 #define GLOBAL2_REG_PHY_DATA 0x19
62 #define PORT_REG_STATUS 0x00
63 #define PORT_REG_PHYS_CTRL 0x01
64 #define PORT_REG_SWITCH_ID 0x03
65 #define PORT_REG_CTRL 0x04
66 #define PORT_REG_VLAN_MAP 0x06
67 #define PORT_REG_VLAN_ID 0x07
70 #define PHY_REG_CTRL1 0x10
71 #define PHY_REG_STATUS1 0x11
72 #define PHY_REG_PAGE 0x16
74 /* Serdes registers */
75 #define SERDES_REG_CTRL_1 0x10
77 /* Phy page numbers */
78 #define PHY_PAGE_COPPER 0
79 #define PHY_PAGE_SERDES 1
82 #define GLOBAL1_CTRL_SWRESET BIT(15)
84 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
85 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
87 #define PORT_REG_STATUS_SPEED_SHIFT 8
88 #define PORT_REG_STATUS_SPEED_10 0
89 #define PORT_REG_STATUS_SPEED_100 1
90 #define PORT_REG_STATUS_SPEED_1000 2
92 #define PORT_REG_STATUS_CMODE_MASK 0xF
93 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8
94 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
95 #define PORT_REG_STATUS_CMODE_SGMII 0xa
97 #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
98 #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
99 #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
100 #define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
101 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
102 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
103 #define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
104 #define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
105 #define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
106 #define PORT_REG_PHYS_CTRL_SPD100 BIT(0)
107 #define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
109 #define PORT_REG_CTRL_PSTATE_SHIFT 0
110 #define PORT_REG_CTRL_PSTATE_WIDTH 2
112 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
113 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
115 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
116 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
118 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
121 #define PORT_REG_CTRL_PSTATE_DISABLED 0
122 #define PORT_REG_CTRL_PSTATE_FORWARD 3
124 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0
125 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE 1
126 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
127 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
129 /* PHY Status Register */
130 #define PHY_REG_STATUS1_SPEED 0xc000
131 #define PHY_REG_STATUS1_GBIT 0x8000
132 #define PHY_REG_STATUS1_100 0x4000
133 #define PHY_REG_STATUS1_DUPLEX 0x2000
134 #define PHY_REG_STATUS1_SPDDONE 0x0800
135 #define PHY_REG_STATUS1_LINK 0x0400
136 #define PHY_REG_STATUS1_ENERGY 0x0010
139 * Macros for building commands for indirect addressing modes. These are valid
140 * for both the indirect multichip addressing mode and the PHY indirection
141 * required for the writes to any PHY register.
143 #define SMI_BUSY BIT(15)
144 #define SMI_CMD_CLAUSE_22 BIT(12)
145 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
146 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
148 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
149 SMI_CMD_CLAUSE_22_OP_READ)
150 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
151 SMI_CMD_CLAUSE_22_OP_WRITE)
153 #define SMI_CMD_ADDR_SHIFT 5
154 #define SMI_CMD_ADDR_WIDTH 5
155 #define SMI_CMD_REG_SHIFT 0
156 #define SMI_CMD_REG_WIDTH 5
158 /* Check for required macros */
159 #ifndef CONFIG_MV88E61XX_PHY_PORTS
160 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
163 #ifndef CONFIG_MV88E61XX_CPU_PORT
164 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
168 * These are ports without PHYs that may be wired directly
169 * to other serdes interfaces
171 #ifndef CONFIG_MV88E61XX_FIXED_PORTS
172 #define CONFIG_MV88E61XX_FIXED_PORTS 0
175 /* ID register values for different switch models */
176 #define PORT_SWITCH_ID_6020 0x0200
177 #define PORT_SWITCH_ID_6070 0x0700
178 #define PORT_SWITCH_ID_6071 0x0710
179 #define PORT_SWITCH_ID_6096 0x0980
180 #define PORT_SWITCH_ID_6097 0x0990
181 #define PORT_SWITCH_ID_6172 0x1720
182 #define PORT_SWITCH_ID_6176 0x1760
183 #define PORT_SWITCH_ID_6220 0x2200
184 #define PORT_SWITCH_ID_6240 0x2400
185 #define PORT_SWITCH_ID_6250 0x2500
186 #define PORT_SWITCH_ID_6352 0x3520
188 struct mv88e61xx_phy_priv {
189 struct mii_dev *mdio_bus;
192 int port_count; /* Number of switch ports */
193 int port_reg_base; /* Base of the switch port registers */
194 u16 port_stat_link_mask;/* Bitmask for port link status bits */
195 u16 port_stat_dup_mask; /* Bitmask for port duplex status bits */
196 u8 port_stat_speed_width;/* Width of speed status bitfield */
197 u8 global1; /* Offset of Switch Global 1 registers */
198 u8 global2; /* Offset of Switch Global 2 registers */
199 u8 phy_ctrl1_en_det_shift; /* 'EDet' bit field offset */
200 u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */
201 u8 phy_ctrl1_en_det_ctrl; /* 'EDet' control value */
204 static inline int smi_cmd(int cmd, int addr, int reg)
206 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
208 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
212 static inline int smi_cmd_read(int addr, int reg)
214 return smi_cmd(SMI_CMD_READ, addr, reg);
217 static inline int smi_cmd_write(int addr, int reg)
219 return smi_cmd(SMI_CMD_WRITE, addr, reg);
222 __weak int mv88e61xx_hw_reset(struct phy_device *phydev)
227 /* Wait for the current SMI indirect command to complete */
228 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
234 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
235 if (val >= 0 && (val & SMI_BUSY) == 0)
241 puts("SMI busy timeout\n");
246 * The mv88e61xx has three types of addresses: the smi bus address, the device
247 * address, and the register address. The smi bus address distinguishes it on
248 * the smi bus from other PHYs or switches. The device address determines
249 * which on-chip register set you are reading/writing (the various PHYs, their
250 * associated ports, or global configuration registers). The register address
251 * is the offset of the register you are reading/writing.
253 * When the mv88e61xx is hardware configured to have address zero, it behaves in
254 * single-chip addressing mode, where it responds to all SMI addresses, using
255 * the smi address as its device address. This obviously only works when this
256 * is the only chip on the SMI bus. This allows the driver to access device
257 * registers without using indirection. When the chip is configured to a
258 * non-zero address, it only responds to that SMI address and requires indirect
259 * writes to access the different device addresses.
261 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
263 struct mv88e61xx_phy_priv *priv = phydev->priv;
264 struct mii_dev *mdio_bus = priv->mdio_bus;
265 int smi_addr = priv->smi_addr;
268 /* In single-chip mode, the device can be addressed directly */
270 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
272 /* Wait for the bus to become free */
273 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
277 /* Issue the read command */
278 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
279 smi_cmd_read(dev, reg));
283 /* Wait for the read command to complete */
284 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
289 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
293 return bitfield_extract(res, 0, 16);
296 /* See the comment above mv88e61xx_reg_read */
297 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
300 struct mv88e61xx_phy_priv *priv = phydev->priv;
301 struct mii_dev *mdio_bus = priv->mdio_bus;
302 int smi_addr = priv->smi_addr;
305 /* In single-chip mode, the device can be addressed directly */
307 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
311 /* Wait for the bus to become free */
312 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
316 /* Set the data to write */
317 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
322 /* Issue the write command */
323 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
324 smi_cmd_write(dev, reg));
328 /* Wait for the write command to complete */
329 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
336 static int mv88e61xx_phy_wait(struct phy_device *phydev)
338 struct mv88e61xx_phy_priv *priv = phydev->priv;
343 val = mv88e61xx_reg_read(phydev, priv->global2,
344 GLOBAL2_REG_PHY_CMD);
345 if (val >= 0 && (val & SMI_BUSY) == 0)
354 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
357 struct mv88e61xx_phy_priv *priv;
358 struct phy_device *phydev;
361 phydev = (struct phy_device *)smi_wrapper->priv;
364 /* Issue command to read */
365 res = mv88e61xx_reg_write(phydev, priv->global2,
367 smi_cmd_read(dev, reg));
369 /* Wait for data to be read */
370 res = mv88e61xx_phy_wait(phydev);
374 /* Read retrieved data */
375 return mv88e61xx_reg_read(phydev, priv->global2,
376 GLOBAL2_REG_PHY_DATA);
379 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
380 int devad, int reg, u16 data)
382 struct mv88e61xx_phy_priv *priv;
383 struct phy_device *phydev;
386 phydev = (struct phy_device *)smi_wrapper->priv;
389 /* Set the data to write */
390 res = mv88e61xx_reg_write(phydev, priv->global2,
391 GLOBAL2_REG_PHY_DATA, data);
394 /* Issue the write command */
395 res = mv88e61xx_reg_write(phydev, priv->global2,
397 smi_cmd_write(dev, reg));
401 /* Wait for command to complete */
402 return mv88e61xx_phy_wait(phydev);
405 /* Wrapper function to make calls to phy_read_indirect simpler */
406 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
408 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
409 MDIO_DEVAD_NONE, reg);
412 /* Wrapper function to make calls to phy_read_indirect simpler */
413 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
416 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
417 MDIO_DEVAD_NONE, reg, val);
420 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
422 struct mv88e61xx_phy_priv *priv = phydev->priv;
424 return mv88e61xx_reg_read(phydev, priv->port_reg_base + port, reg);
427 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
430 struct mv88e61xx_phy_priv *priv = phydev->priv;
432 return mv88e61xx_reg_write(phydev, priv->port_reg_base + port,
436 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
438 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
441 static int mv88e61xx_get_switch_id(struct phy_device *phydev)
445 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
451 static bool mv88e61xx_6352_family(struct phy_device *phydev)
453 struct mv88e61xx_phy_priv *priv = phydev->priv;
456 case PORT_SWITCH_ID_6172:
457 case PORT_SWITCH_ID_6176:
458 case PORT_SWITCH_ID_6240:
459 case PORT_SWITCH_ID_6352:
465 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
469 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
472 return res & PORT_REG_STATUS_CMODE_MASK;
475 static int mv88e61xx_parse_status(struct phy_device *phydev)
478 unsigned int mii_reg;
480 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
482 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
483 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
486 puts("Waiting for PHY realtime link");
487 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
488 /* Timeout reached ? */
489 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
490 puts(" TIMEOUT !\n");
495 if ((i++ % 1000) == 0)
498 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
502 udelay(500000); /* another 500 ms (results in faster booting) */
504 if (mii_reg & PHY_REG_STATUS1_LINK)
510 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
511 phydev->duplex = DUPLEX_FULL;
513 phydev->duplex = DUPLEX_HALF;
515 speed = mii_reg & PHY_REG_STATUS1_SPEED;
518 case PHY_REG_STATUS1_GBIT:
519 phydev->speed = SPEED_1000;
521 case PHY_REG_STATUS1_100:
522 phydev->speed = SPEED_100;
525 phydev->speed = SPEED_10;
532 static int mv88e61xx_switch_reset(struct phy_device *phydev)
534 struct mv88e61xx_phy_priv *priv = phydev->priv;
539 /* Disable all ports */
540 for (port = 0; port < priv->port_count; port++) {
541 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
544 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
545 PORT_REG_CTRL_PSTATE_WIDTH,
546 PORT_REG_CTRL_PSTATE_DISABLED);
547 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
552 /* Wait 2 ms for queues to drain */
556 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_CTRL);
559 val |= GLOBAL1_CTRL_SWRESET;
560 val = mv88e61xx_reg_write(phydev, priv->global1,
565 /* Wait up to 1 second for switch reset complete */
566 for (time = 1000; time; time--) {
567 val = mv88e61xx_reg_read(phydev, priv->global1,
569 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
579 static int mv88e61xx_serdes_init(struct phy_device *phydev)
583 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
587 /* Power up serdes module */
588 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
591 val &= ~(BMCR_PDOWN);
592 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
599 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
603 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
606 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
607 PORT_REG_CTRL_PSTATE_WIDTH,
608 PORT_REG_CTRL_PSTATE_FORWARD);
609 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
616 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
621 /* Set VID to port number plus one */
622 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
625 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
626 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
628 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
633 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
636 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
637 PORT_REG_VLAN_MAP_TABLE_WIDTH,
639 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
646 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
648 struct mv88e61xx_phy_priv *priv = phydev->priv;
653 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
656 if (!(val & priv->port_stat_link_mask)) {
657 /* Temporarily force link to read port configuration */
661 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
664 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
665 PORT_REG_PHYS_CTRL_LINK_VALUE);
666 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
671 /* Wait for status register to reflect forced link */
673 val = mv88e61xx_port_read(phydev, port,
679 if (val & priv->port_stat_link_mask)
689 if (val & priv->port_stat_dup_mask)
690 phydev->duplex = DUPLEX_FULL;
692 phydev->duplex = DUPLEX_HALF;
694 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
695 priv->port_stat_speed_width);
697 case PORT_REG_STATUS_SPEED_1000:
698 phydev->speed = SPEED_1000;
700 case PORT_REG_STATUS_SPEED_100:
701 phydev->speed = SPEED_100;
704 phydev->speed = SPEED_10;
712 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
715 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
716 PORT_REG_PHYS_CTRL_LINK_VALUE);
717 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
726 static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
728 struct mv88e61xx_phy_priv *priv = phydev->priv;
731 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
735 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
736 PORT_REG_PHYS_CTRL_FC_VALUE |
737 PORT_REG_PHYS_CTRL_FC_FORCE);
738 val |= PORT_REG_PHYS_CTRL_FC_FORCE |
739 PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
740 PORT_REG_PHYS_CTRL_DUPLEX_FORCE;
742 if (priv->id == PORT_SWITCH_ID_6071) {
743 val |= PORT_REG_PHYS_CTRL_SPD100;
745 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
746 PORT_REG_PHYS_CTRL_PCS_AN_RST |
747 PORT_REG_PHYS_CTRL_SPD1000;
750 if (port == CONFIG_MV88E61XX_CPU_PORT)
751 val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
752 PORT_REG_PHYS_CTRL_LINK_FORCE;
754 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
758 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
760 struct mv88e61xx_phy_priv *priv = phydev->priv;
764 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_MON_CTRL);
767 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
768 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
769 CONFIG_MV88E61XX_CPU_PORT);
770 val = mv88e61xx_reg_write(phydev, priv->global1,
771 GLOBAL1_MON_CTRL, val);
775 /* Allow CPU to route to any port */
776 val = PORT_MASK(priv->port_count) & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
777 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
781 /* Enable CPU port */
782 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
786 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
790 /* If CPU is connected to serdes, initialize serdes */
791 if (mv88e61xx_6352_family(phydev)) {
792 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
795 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
796 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
797 val == PORT_REG_STATUS_CMODE_SGMII) {
798 val = mv88e61xx_serdes_init(phydev);
803 val = mv88e61xx_fixed_port_setup(phydev,
804 CONFIG_MV88E61XX_CPU_PORT);
812 static int mv88e61xx_switch_init(struct phy_device *phydev)
820 res = mv88e61xx_switch_reset(phydev);
824 res = mv88e61xx_set_cpu_port(phydev);
833 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
837 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
840 val &= ~(BMCR_PDOWN);
841 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
848 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
850 struct mv88e61xx_phy_priv *priv = phydev->priv;
854 * Enable energy-detect sensing on PHY, used to determine when a PHY
855 * port is physically connected
857 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
860 val = bitfield_replace(val, priv->phy_ctrl1_en_det_shift,
861 priv->phy_ctrl1_en_det_width,
862 priv->phy_ctrl1_en_det_ctrl);
863 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
870 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
874 val = mv88e61xx_port_enable(phydev, phy);
878 val = mv88e61xx_port_set_vlan(phydev, phy,
879 1 << CONFIG_MV88E61XX_CPU_PORT);
887 * This function is used to pre-configure the required register
888 * offsets, so that the indirect register access to the PHY registers
889 * is possible. This is necessary to be able to read the PHY ID
890 * while driver probing or in get_phy_id(). The globalN register
891 * offsets must be initialized correctly for a detected switch,
892 * otherwise detection of the PHY ID won't work!
894 static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev)
896 struct mv88e61xx_phy_priv *priv = phydev->priv;
899 * Initial 'port_reg_base' value must be an offset of existing
900 * port register, then reading the ID should succeed. First, try
901 * to read via port registers with device address 0x10 (88E6096
902 * and compatible switches).
904 priv->port_reg_base = 0x10;
905 priv->id = mv88e61xx_get_switch_id(phydev);
906 if (priv->id != 0xfff0) {
907 priv->global1 = 0x1B;
908 priv->global2 = 0x1C;
913 * Now try via port registers with device address 0x08
914 * (88E6020 and compatible switches).
916 priv->port_reg_base = 0x08;
917 priv->id = mv88e61xx_get_switch_id(phydev);
918 if (priv->id != 0xfff0) {
919 priv->global1 = 0x0F;
920 priv->global2 = 0x07;
924 debug("%s Unknown ID 0x%x\n", __func__, priv->id);
928 static int mv88e61xx_probe(struct phy_device *phydev)
930 struct mii_dev *smi_wrapper;
931 struct mv88e61xx_phy_priv *priv;
934 res = mv88e61xx_hw_reset(phydev);
938 priv = malloc(sizeof(*priv));
942 memset(priv, 0, sizeof(*priv));
945 * This device requires indirect reads/writes to the PHY registers
946 * which the generic PHY code can't handle. Make a wrapper MII device
947 * to handle reads/writes
949 smi_wrapper = mdio_alloc();
956 * Store the mdio bus in the private data, as we are going to replace
957 * the bus with the wrapper bus
959 priv->mdio_bus = phydev->bus;
962 * Store the smi bus address in private data. This lets us use the
963 * phydev addr field for device address instead, as the genphy code
966 priv->smi_addr = phydev->addr;
969 * Store the phy_device in the wrapper mii device. This lets us get it
970 * back when genphy functions call phy_read/phy_write.
972 smi_wrapper->priv = phydev;
973 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
974 smi_wrapper->read = mv88e61xx_phy_read_indirect;
975 smi_wrapper->write = mv88e61xx_phy_write_indirect;
977 /* Replace the bus with the wrapper device */
978 phydev->bus = smi_wrapper;
982 res = mv88e61xx_priv_reg_offs_pre_init(phydev);
986 debug("%s ID 0x%x\n", __func__, priv->id);
989 case PORT_SWITCH_ID_6096:
990 case PORT_SWITCH_ID_6097:
991 case PORT_SWITCH_ID_6172:
992 case PORT_SWITCH_ID_6176:
993 case PORT_SWITCH_ID_6240:
994 case PORT_SWITCH_ID_6352:
995 priv->port_count = 11;
996 priv->port_stat_link_mask = BIT(11);
997 priv->port_stat_dup_mask = BIT(10);
998 priv->port_stat_speed_width = 2;
999 priv->phy_ctrl1_en_det_shift = 8;
1000 priv->phy_ctrl1_en_det_width = 2;
1001 priv->phy_ctrl1_en_det_ctrl =
1002 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT;
1004 case PORT_SWITCH_ID_6020:
1005 case PORT_SWITCH_ID_6070:
1006 case PORT_SWITCH_ID_6071:
1007 case PORT_SWITCH_ID_6220:
1008 case PORT_SWITCH_ID_6250:
1009 priv->port_count = 7;
1010 priv->port_stat_link_mask = BIT(12);
1011 priv->port_stat_dup_mask = BIT(9);
1012 priv->port_stat_speed_width = 1;
1013 priv->phy_ctrl1_en_det_shift = 14;
1014 priv->phy_ctrl1_en_det_width = 1;
1015 priv->phy_ctrl1_en_det_ctrl =
1016 PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE;
1023 res = mdio_register(smi_wrapper);
1025 printf("Failed to register SMI bus\n");
1030 static int mv88e61xx_phy_config(struct phy_device *phydev)
1032 struct mv88e61xx_phy_priv *priv = phydev->priv;
1037 res = mv88e61xx_switch_init(phydev);
1041 for (i = 0; i < priv->port_count; i++) {
1042 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1045 res = mv88e61xx_phy_enable(phydev, i);
1047 printf("Error enabling PHY %i\n", i);
1050 res = mv88e61xx_phy_setup(phydev, i);
1052 printf("Error setting up PHY %i\n", i);
1055 res = mv88e61xx_phy_config_port(phydev, i);
1057 printf("Error configuring PHY %i\n", i);
1061 res = phy_reset(phydev);
1063 printf("Error resetting PHY %i\n", i);
1066 res = genphy_config_aneg(phydev);
1068 printf("Error setting PHY %i autoneg\n", i);
1072 /* Return success if any PHY succeeds */
1074 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
1075 res = mv88e61xx_fixed_port_setup(phydev, i);
1077 printf("Error configuring port %i\n", i);
1086 static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
1090 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
1095 * After reset, the energy detect signal remains high for a few seconds
1096 * regardless of whether a cable is connected. This function will
1097 * return false positives during this time.
1099 return (val & PHY_REG_STATUS1_ENERGY) == 0;
1102 static int mv88e61xx_phy_startup(struct phy_device *phydev)
1104 struct mv88e61xx_phy_priv *priv = phydev->priv;
1108 int speed = phydev->speed;
1109 int duplex = phydev->duplex;
1111 for (i = 0; i < priv->port_count; i++) {
1112 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1114 if (!mv88e61xx_phy_is_connected(phydev))
1116 res = genphy_update_link(phydev);
1119 res = mv88e61xx_parse_status(phydev);
1122 link = (link || phydev->link);
1125 phydev->link = link;
1127 /* Restore CPU interface speed and duplex after it was changed for
1129 phydev->speed = speed;
1130 phydev->duplex = duplex;
1135 static struct phy_driver mv88e61xx_driver = {
1136 .name = "Marvell MV88E61xx",
1139 .features = PHY_GBIT_FEATURES,
1140 .probe = mv88e61xx_probe,
1141 .config = mv88e61xx_phy_config,
1142 .startup = mv88e61xx_phy_startup,
1143 .shutdown = &genphy_shutdown,
1146 static struct phy_driver mv88e609x_driver = {
1147 .name = "Marvell MV88E609x",
1150 .features = PHY_GBIT_FEATURES,
1151 .probe = mv88e61xx_probe,
1152 .config = mv88e61xx_phy_config,
1153 .startup = mv88e61xx_phy_startup,
1154 .shutdown = &genphy_shutdown,
1157 static struct phy_driver mv88e6071_driver = {
1158 .name = "Marvell MV88E6071",
1161 .features = PHY_BASIC_FEATURES | SUPPORTED_MII,
1162 .probe = mv88e61xx_probe,
1163 .config = mv88e61xx_phy_config,
1164 .startup = mv88e61xx_phy_startup,
1165 .shutdown = &genphy_shutdown,
1168 int phy_mv88e61xx_init(void)
1170 phy_register(&mv88e61xx_driver);
1171 phy_register(&mv88e609x_driver);
1172 phy_register(&mv88e6071_driver);
1178 * Overload weak get_phy_id definition since we need non-standard functions
1179 * to read PHY registers
1181 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1183 struct phy_device temp_phy;
1184 struct mv88e61xx_phy_priv temp_priv;
1185 struct mii_dev temp_mii;
1189 * Buid temporary data structures that the chip reading code needs to
1192 temp_priv.mdio_bus = bus;
1193 temp_priv.smi_addr = smi_addr;
1194 temp_phy.priv = &temp_priv;
1195 temp_mii.priv = &temp_phy;
1198 * get_phy_id() can be called by framework before mv88e61xx driver
1199 * probing, in this case the global register offsets are not
1200 * initialized yet. Do this initialization here before indirect
1201 * PHY register access.
1203 val = mv88e61xx_priv_reg_offs_pre_init(&temp_phy);
1207 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1211 *phy_id = val << 16;
1213 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1217 *phy_id |= (val & 0xffff);