1 // SPDX-License-Identifier: GPL-2.0+
4 * Elecsys Corporation <www.elecsyscorp.com>
5 * Kevin Smith <kevin.smith@elecsyscorp.com>
9 * Marvell Semiconductor <www.marvell.com>
10 * Prafulla Wadaskar <prafulla@marvell.com>
14 * PHY driver for mv88e61xx ethernet switches.
16 * This driver configures the mv88e61xx for basic use as a PHY. The switch
17 * supports a VLAN configuration that determines how traffic will be routed
18 * between the ports. This driver uses a simple configuration that routes
19 * traffic from each PHY port only to the CPU port, and from the CPU port to
22 * The configuration determines which PHY ports to activate using the
23 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
24 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
25 * connected to unless it is connected over a PHY interface (not MII).
27 * This driver was written for and tested on the mv88e6176 with an SGMII
28 * connection. Other configurations should be supported, but some additions or
29 * changes may be required.
40 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
42 #define PORT_MASK(port_count) ((1 << (port_count)) - 1)
44 /* Device addresses */
45 #define DEVADDR_PHY(p) (p)
46 #define DEVADDR_SERDES 0x0F
48 /* SMI indirection registers for multichip addressing mode */
49 #define SMI_CMD_REG 0x00
50 #define SMI_DATA_REG 0x01
52 /* Global registers */
53 #define GLOBAL1_STATUS 0x00
54 #define GLOBAL1_CTRL 0x04
55 #define GLOBAL1_MON_CTRL 0x1A
57 /* Global 2 registers */
58 #define GLOBAL2_REG_PHY_CMD 0x18
59 #define GLOBAL2_REG_PHY_DATA 0x19
62 #define PORT_REG_STATUS 0x00
63 #define PORT_REG_PHYS_CTRL 0x01
64 #define PORT_REG_SWITCH_ID 0x03
65 #define PORT_REG_CTRL 0x04
66 #define PORT_REG_VLAN_MAP 0x06
67 #define PORT_REG_VLAN_ID 0x07
70 #define PHY_REG_CTRL1 0x10
71 #define PHY_REG_STATUS1 0x11
72 #define PHY_REG_PAGE 0x16
74 /* Serdes registers */
75 #define SERDES_REG_CTRL_1 0x10
77 /* Phy page numbers */
78 #define PHY_PAGE_COPPER 0
79 #define PHY_PAGE_SERDES 1
82 #define GLOBAL1_CTRL_SWRESET BIT(15)
84 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
85 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
87 #define PORT_REG_STATUS_SPEED_SHIFT 8
88 #define PORT_REG_STATUS_SPEED_10 0
89 #define PORT_REG_STATUS_SPEED_100 1
90 #define PORT_REG_STATUS_SPEED_1000 2
92 #define PORT_REG_STATUS_CMODE_MASK 0xF
93 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8
94 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
95 #define PORT_REG_STATUS_CMODE_SGMII 0xa
97 #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
98 #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
99 #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
100 #define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
101 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
102 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
103 #define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
104 #define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
105 #define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
106 #define PORT_REG_PHYS_CTRL_SPD100 BIT(0)
107 #define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
109 #define PORT_REG_CTRL_PSTATE_SHIFT 0
110 #define PORT_REG_CTRL_PSTATE_WIDTH 2
112 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
113 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
115 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
116 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
118 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
120 #define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
121 #define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
124 #define PORT_REG_CTRL_PSTATE_DISABLED 0
125 #define PORT_REG_CTRL_PSTATE_FORWARD 3
127 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0
128 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
129 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
131 /* PHY Status Register */
132 #define PHY_REG_STATUS1_SPEED 0xc000
133 #define PHY_REG_STATUS1_GBIT 0x8000
134 #define PHY_REG_STATUS1_100 0x4000
135 #define PHY_REG_STATUS1_DUPLEX 0x2000
136 #define PHY_REG_STATUS1_SPDDONE 0x0800
137 #define PHY_REG_STATUS1_LINK 0x0400
138 #define PHY_REG_STATUS1_ENERGY 0x0010
141 * Macros for building commands for indirect addressing modes. These are valid
142 * for both the indirect multichip addressing mode and the PHY indirection
143 * required for the writes to any PHY register.
145 #define SMI_BUSY BIT(15)
146 #define SMI_CMD_CLAUSE_22 BIT(12)
147 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
148 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
150 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
151 SMI_CMD_CLAUSE_22_OP_READ)
152 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
153 SMI_CMD_CLAUSE_22_OP_WRITE)
155 #define SMI_CMD_ADDR_SHIFT 5
156 #define SMI_CMD_ADDR_WIDTH 5
157 #define SMI_CMD_REG_SHIFT 0
158 #define SMI_CMD_REG_WIDTH 5
160 /* Check for required macros */
161 #ifndef CONFIG_MV88E61XX_PHY_PORTS
162 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
165 #ifndef CONFIG_MV88E61XX_CPU_PORT
166 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
170 * These are ports without PHYs that may be wired directly
171 * to other serdes interfaces
173 #ifndef CONFIG_MV88E61XX_FIXED_PORTS
174 #define CONFIG_MV88E61XX_FIXED_PORTS 0
177 /* ID register values for different switch models */
178 #define PORT_SWITCH_ID_6020 0x0200
179 #define PORT_SWITCH_ID_6070 0x0700
180 #define PORT_SWITCH_ID_6071 0x0710
181 #define PORT_SWITCH_ID_6096 0x0980
182 #define PORT_SWITCH_ID_6097 0x0990
183 #define PORT_SWITCH_ID_6172 0x1720
184 #define PORT_SWITCH_ID_6176 0x1760
185 #define PORT_SWITCH_ID_6220 0x2200
186 #define PORT_SWITCH_ID_6240 0x2400
187 #define PORT_SWITCH_ID_6250 0x2500
188 #define PORT_SWITCH_ID_6352 0x3520
190 struct mv88e61xx_phy_priv {
191 struct mii_dev *mdio_bus;
194 int port_count; /* Number of switch ports */
195 int port_reg_base; /* Base of the switch port registers */
196 u16 port_stat_link_mask;/* Bitmask for port link status bits */
197 u16 port_stat_dup_mask; /* Bitmask for port duplex status bits */
198 u8 port_stat_speed_width;/* Width of speed status bitfield */
199 u8 global1; /* Offset of Switch Global 1 registers */
200 u8 global2; /* Offset of Switch Global 2 registers */
203 static inline int smi_cmd(int cmd, int addr, int reg)
205 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
207 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
211 static inline int smi_cmd_read(int addr, int reg)
213 return smi_cmd(SMI_CMD_READ, addr, reg);
216 static inline int smi_cmd_write(int addr, int reg)
218 return smi_cmd(SMI_CMD_WRITE, addr, reg);
221 __weak int mv88e61xx_hw_reset(struct phy_device *phydev)
226 /* Wait for the current SMI indirect command to complete */
227 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
233 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
234 if (val >= 0 && (val & SMI_BUSY) == 0)
240 puts("SMI busy timeout\n");
245 * The mv88e61xx has three types of addresses: the smi bus address, the device
246 * address, and the register address. The smi bus address distinguishes it on
247 * the smi bus from other PHYs or switches. The device address determines
248 * which on-chip register set you are reading/writing (the various PHYs, their
249 * associated ports, or global configuration registers). The register address
250 * is the offset of the register you are reading/writing.
252 * When the mv88e61xx is hardware configured to have address zero, it behaves in
253 * single-chip addressing mode, where it responds to all SMI addresses, using
254 * the smi address as its device address. This obviously only works when this
255 * is the only chip on the SMI bus. This allows the driver to access device
256 * registers without using indirection. When the chip is configured to a
257 * non-zero address, it only responds to that SMI address and requires indirect
258 * writes to access the different device addresses.
260 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
262 struct mv88e61xx_phy_priv *priv = phydev->priv;
263 struct mii_dev *mdio_bus = priv->mdio_bus;
264 int smi_addr = priv->smi_addr;
267 /* In single-chip mode, the device can be addressed directly */
269 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
271 /* Wait for the bus to become free */
272 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
276 /* Issue the read command */
277 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
278 smi_cmd_read(dev, reg));
282 /* Wait for the read command to complete */
283 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
288 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
292 return bitfield_extract(res, 0, 16);
295 /* See the comment above mv88e61xx_reg_read */
296 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
299 struct mv88e61xx_phy_priv *priv = phydev->priv;
300 struct mii_dev *mdio_bus = priv->mdio_bus;
301 int smi_addr = priv->smi_addr;
304 /* In single-chip mode, the device can be addressed directly */
306 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
310 /* Wait for the bus to become free */
311 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
315 /* Set the data to write */
316 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
321 /* Issue the write command */
322 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
323 smi_cmd_write(dev, reg));
327 /* Wait for the write command to complete */
328 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
335 static int mv88e61xx_phy_wait(struct phy_device *phydev)
337 struct mv88e61xx_phy_priv *priv = phydev->priv;
342 val = mv88e61xx_reg_read(phydev, priv->global2,
343 GLOBAL2_REG_PHY_CMD);
344 if (val >= 0 && (val & SMI_BUSY) == 0)
353 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
356 struct mv88e61xx_phy_priv *priv;
357 struct phy_device *phydev;
360 phydev = (struct phy_device *)smi_wrapper->priv;
363 /* Issue command to read */
364 res = mv88e61xx_reg_write(phydev, priv->global2,
366 smi_cmd_read(dev, reg));
368 /* Wait for data to be read */
369 res = mv88e61xx_phy_wait(phydev);
373 /* Read retrieved data */
374 return mv88e61xx_reg_read(phydev, priv->global2,
375 GLOBAL2_REG_PHY_DATA);
378 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
379 int devad, int reg, u16 data)
381 struct mv88e61xx_phy_priv *priv;
382 struct phy_device *phydev;
385 phydev = (struct phy_device *)smi_wrapper->priv;
388 /* Set the data to write */
389 res = mv88e61xx_reg_write(phydev, priv->global2,
390 GLOBAL2_REG_PHY_DATA, data);
393 /* Issue the write command */
394 res = mv88e61xx_reg_write(phydev, priv->global2,
396 smi_cmd_write(dev, reg));
400 /* Wait for command to complete */
401 return mv88e61xx_phy_wait(phydev);
404 /* Wrapper function to make calls to phy_read_indirect simpler */
405 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
407 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
408 MDIO_DEVAD_NONE, reg);
411 /* Wrapper function to make calls to phy_read_indirect simpler */
412 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
415 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
416 MDIO_DEVAD_NONE, reg, val);
419 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
421 struct mv88e61xx_phy_priv *priv = phydev->priv;
423 return mv88e61xx_reg_read(phydev, priv->port_reg_base + port, reg);
426 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
429 struct mv88e61xx_phy_priv *priv = phydev->priv;
431 return mv88e61xx_reg_write(phydev, priv->port_reg_base + port,
435 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
437 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
440 static int mv88e61xx_get_switch_id(struct phy_device *phydev)
444 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
450 static bool mv88e61xx_6352_family(struct phy_device *phydev)
452 struct mv88e61xx_phy_priv *priv = phydev->priv;
455 case PORT_SWITCH_ID_6172:
456 case PORT_SWITCH_ID_6176:
457 case PORT_SWITCH_ID_6240:
458 case PORT_SWITCH_ID_6352:
464 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
468 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
471 return res & PORT_REG_STATUS_CMODE_MASK;
474 static int mv88e61xx_parse_status(struct phy_device *phydev)
477 unsigned int mii_reg;
479 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
481 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
482 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
485 puts("Waiting for PHY realtime link");
486 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
487 /* Timeout reached ? */
488 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
489 puts(" TIMEOUT !\n");
494 if ((i++ % 1000) == 0)
497 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
501 udelay(500000); /* another 500 ms (results in faster booting) */
503 if (mii_reg & PHY_REG_STATUS1_LINK)
509 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
510 phydev->duplex = DUPLEX_FULL;
512 phydev->duplex = DUPLEX_HALF;
514 speed = mii_reg & PHY_REG_STATUS1_SPEED;
517 case PHY_REG_STATUS1_GBIT:
518 phydev->speed = SPEED_1000;
520 case PHY_REG_STATUS1_100:
521 phydev->speed = SPEED_100;
524 phydev->speed = SPEED_10;
531 static int mv88e61xx_switch_reset(struct phy_device *phydev)
533 struct mv88e61xx_phy_priv *priv = phydev->priv;
538 /* Disable all ports */
539 for (port = 0; port < priv->port_count; port++) {
540 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
543 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
544 PORT_REG_CTRL_PSTATE_WIDTH,
545 PORT_REG_CTRL_PSTATE_DISABLED);
546 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
551 /* Wait 2 ms for queues to drain */
555 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_CTRL);
558 val |= GLOBAL1_CTRL_SWRESET;
559 val = mv88e61xx_reg_write(phydev, priv->global1,
564 /* Wait up to 1 second for switch reset complete */
565 for (time = 1000; time; time--) {
566 val = mv88e61xx_reg_read(phydev, priv->global1,
568 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
578 static int mv88e61xx_serdes_init(struct phy_device *phydev)
582 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
586 /* Power up serdes module */
587 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
590 val &= ~(BMCR_PDOWN);
591 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
598 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
602 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
605 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
606 PORT_REG_CTRL_PSTATE_WIDTH,
607 PORT_REG_CTRL_PSTATE_FORWARD);
608 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
615 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
620 /* Set VID to port number plus one */
621 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
624 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
625 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
627 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
632 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
635 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
636 PORT_REG_VLAN_MAP_TABLE_WIDTH,
638 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
645 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
647 struct mv88e61xx_phy_priv *priv = phydev->priv;
652 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
655 if (!(val & priv->port_stat_link_mask)) {
656 /* Temporarily force link to read port configuration */
660 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
663 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
664 PORT_REG_PHYS_CTRL_LINK_VALUE);
665 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
670 /* Wait for status register to reflect forced link */
672 val = mv88e61xx_port_read(phydev, port,
678 if (val & priv->port_stat_link_mask)
688 if (val & priv->port_stat_dup_mask)
689 phydev->duplex = DUPLEX_FULL;
691 phydev->duplex = DUPLEX_HALF;
693 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
694 priv->port_stat_speed_width);
696 case PORT_REG_STATUS_SPEED_1000:
697 phydev->speed = SPEED_1000;
699 case PORT_REG_STATUS_SPEED_100:
700 phydev->speed = SPEED_100;
703 phydev->speed = SPEED_10;
711 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
714 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
715 PORT_REG_PHYS_CTRL_LINK_VALUE);
716 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
725 static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
727 struct mv88e61xx_phy_priv *priv = phydev->priv;
730 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
734 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
735 PORT_REG_PHYS_CTRL_FC_VALUE |
736 PORT_REG_PHYS_CTRL_FC_FORCE);
737 val |= PORT_REG_PHYS_CTRL_FC_FORCE |
738 PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
739 PORT_REG_PHYS_CTRL_DUPLEX_FORCE;
741 if (priv->id == PORT_SWITCH_ID_6071) {
742 val |= PORT_REG_PHYS_CTRL_SPD100;
744 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
745 PORT_REG_PHYS_CTRL_PCS_AN_RST |
746 PORT_REG_PHYS_CTRL_SPD1000;
749 if (port == CONFIG_MV88E61XX_CPU_PORT)
750 val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
751 PORT_REG_PHYS_CTRL_LINK_FORCE;
753 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
757 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
759 struct mv88e61xx_phy_priv *priv = phydev->priv;
763 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_MON_CTRL);
766 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
767 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
768 CONFIG_MV88E61XX_CPU_PORT);
769 val = mv88e61xx_reg_write(phydev, priv->global1,
770 GLOBAL1_MON_CTRL, val);
774 /* Allow CPU to route to any port */
775 val = PORT_MASK(priv->port_count) & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
776 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
780 /* Enable CPU port */
781 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
785 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
789 /* If CPU is connected to serdes, initialize serdes */
790 if (mv88e61xx_6352_family(phydev)) {
791 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
794 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
795 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
796 val == PORT_REG_STATUS_CMODE_SGMII) {
797 val = mv88e61xx_serdes_init(phydev);
802 val = mv88e61xx_fixed_port_setup(phydev,
803 CONFIG_MV88E61XX_CPU_PORT);
811 static int mv88e61xx_switch_init(struct phy_device *phydev)
819 res = mv88e61xx_switch_reset(phydev);
823 res = mv88e61xx_set_cpu_port(phydev);
832 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
836 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
839 val &= ~(BMCR_PDOWN);
840 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
847 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
852 * Enable energy-detect sensing on PHY, used to determine when a PHY
853 * port is physically connected
855 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
858 val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
859 PHY_REG_CTRL1_ENERGY_DET_WIDTH,
860 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
861 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
868 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
872 val = mv88e61xx_port_enable(phydev, phy);
876 val = mv88e61xx_port_set_vlan(phydev, phy,
877 1 << CONFIG_MV88E61XX_CPU_PORT);
885 * This function is used to pre-configure the required register
886 * offsets, so that the indirect register access to the PHY registers
887 * is possible. This is necessary to be able to read the PHY ID
888 * while driver probing or in get_phy_id(). The globalN register
889 * offsets must be initialized correctly for a detected switch,
890 * otherwise detection of the PHY ID won't work!
892 static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev)
894 struct mv88e61xx_phy_priv *priv = phydev->priv;
897 * Initial 'port_reg_base' value must be an offset of existing
898 * port register, then reading the ID should succeed. First, try
899 * to read via port registers with device address 0x10 (88E6096
900 * and compatible switches).
902 priv->port_reg_base = 0x10;
903 priv->id = mv88e61xx_get_switch_id(phydev);
904 if (priv->id != 0xfff0) {
905 priv->global1 = 0x1B;
906 priv->global2 = 0x1C;
911 * Now try via port registers with device address 0x08
912 * (88E6020 and compatible switches).
914 priv->port_reg_base = 0x08;
915 priv->id = mv88e61xx_get_switch_id(phydev);
916 if (priv->id != 0xfff0) {
917 priv->global1 = 0x0F;
918 priv->global2 = 0x07;
922 debug("%s Unknown ID 0x%x\n", __func__, priv->id);
926 static int mv88e61xx_probe(struct phy_device *phydev)
928 struct mii_dev *smi_wrapper;
929 struct mv88e61xx_phy_priv *priv;
932 res = mv88e61xx_hw_reset(phydev);
936 priv = malloc(sizeof(*priv));
940 memset(priv, 0, sizeof(*priv));
943 * This device requires indirect reads/writes to the PHY registers
944 * which the generic PHY code can't handle. Make a wrapper MII device
945 * to handle reads/writes
947 smi_wrapper = mdio_alloc();
954 * Store the mdio bus in the private data, as we are going to replace
955 * the bus with the wrapper bus
957 priv->mdio_bus = phydev->bus;
960 * Store the smi bus address in private data. This lets us use the
961 * phydev addr field for device address instead, as the genphy code
964 priv->smi_addr = phydev->addr;
967 * Store the phy_device in the wrapper mii device. This lets us get it
968 * back when genphy functions call phy_read/phy_write.
970 smi_wrapper->priv = phydev;
971 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
972 smi_wrapper->read = mv88e61xx_phy_read_indirect;
973 smi_wrapper->write = mv88e61xx_phy_write_indirect;
975 /* Replace the bus with the wrapper device */
976 phydev->bus = smi_wrapper;
980 res = mv88e61xx_priv_reg_offs_pre_init(phydev);
984 debug("%s ID 0x%x\n", __func__, priv->id);
987 case PORT_SWITCH_ID_6096:
988 case PORT_SWITCH_ID_6097:
989 case PORT_SWITCH_ID_6172:
990 case PORT_SWITCH_ID_6176:
991 case PORT_SWITCH_ID_6240:
992 case PORT_SWITCH_ID_6352:
993 priv->port_count = 11;
994 priv->port_stat_link_mask = BIT(11);
995 priv->port_stat_dup_mask = BIT(10);
996 priv->port_stat_speed_width = 2;
998 case PORT_SWITCH_ID_6020:
999 case PORT_SWITCH_ID_6070:
1000 case PORT_SWITCH_ID_6071:
1001 case PORT_SWITCH_ID_6220:
1002 case PORT_SWITCH_ID_6250:
1003 priv->port_count = 7;
1004 priv->port_stat_link_mask = BIT(12);
1005 priv->port_stat_dup_mask = BIT(9);
1006 priv->port_stat_speed_width = 1;
1013 res = mdio_register(smi_wrapper);
1015 printf("Failed to register SMI bus\n");
1020 static int mv88e61xx_phy_config(struct phy_device *phydev)
1022 struct mv88e61xx_phy_priv *priv = phydev->priv;
1027 res = mv88e61xx_switch_init(phydev);
1031 for (i = 0; i < priv->port_count; i++) {
1032 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1035 res = mv88e61xx_phy_enable(phydev, i);
1037 printf("Error enabling PHY %i\n", i);
1040 res = mv88e61xx_phy_setup(phydev, i);
1042 printf("Error setting up PHY %i\n", i);
1045 res = mv88e61xx_phy_config_port(phydev, i);
1047 printf("Error configuring PHY %i\n", i);
1051 res = phy_reset(phydev);
1053 printf("Error resetting PHY %i\n", i);
1056 res = genphy_config_aneg(phydev);
1058 printf("Error setting PHY %i autoneg\n", i);
1062 /* Return success if any PHY succeeds */
1064 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
1065 res = mv88e61xx_fixed_port_setup(phydev, i);
1067 printf("Error configuring port %i\n", i);
1076 static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
1080 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
1085 * After reset, the energy detect signal remains high for a few seconds
1086 * regardless of whether a cable is connected. This function will
1087 * return false positives during this time.
1089 return (val & PHY_REG_STATUS1_ENERGY) == 0;
1092 static int mv88e61xx_phy_startup(struct phy_device *phydev)
1094 struct mv88e61xx_phy_priv *priv = phydev->priv;
1098 int speed = phydev->speed;
1099 int duplex = phydev->duplex;
1101 for (i = 0; i < priv->port_count; i++) {
1102 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1104 if (!mv88e61xx_phy_is_connected(phydev))
1106 res = genphy_update_link(phydev);
1109 res = mv88e61xx_parse_status(phydev);
1112 link = (link || phydev->link);
1115 phydev->link = link;
1117 /* Restore CPU interface speed and duplex after it was changed for
1119 phydev->speed = speed;
1120 phydev->duplex = duplex;
1125 static struct phy_driver mv88e61xx_driver = {
1126 .name = "Marvell MV88E61xx",
1129 .features = PHY_GBIT_FEATURES,
1130 .probe = mv88e61xx_probe,
1131 .config = mv88e61xx_phy_config,
1132 .startup = mv88e61xx_phy_startup,
1133 .shutdown = &genphy_shutdown,
1136 static struct phy_driver mv88e609x_driver = {
1137 .name = "Marvell MV88E609x",
1140 .features = PHY_GBIT_FEATURES,
1141 .probe = mv88e61xx_probe,
1142 .config = mv88e61xx_phy_config,
1143 .startup = mv88e61xx_phy_startup,
1144 .shutdown = &genphy_shutdown,
1147 int phy_mv88e61xx_init(void)
1149 phy_register(&mv88e61xx_driver);
1150 phy_register(&mv88e609x_driver);
1156 * Overload weak get_phy_id definition since we need non-standard functions
1157 * to read PHY registers
1159 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1161 struct phy_device temp_phy;
1162 struct mv88e61xx_phy_priv temp_priv;
1163 struct mii_dev temp_mii;
1167 * Buid temporary data structures that the chip reading code needs to
1170 temp_priv.mdio_bus = bus;
1171 temp_priv.smi_addr = smi_addr;
1172 temp_phy.priv = &temp_priv;
1173 temp_mii.priv = &temp_phy;
1176 * get_phy_id() can be called by framework before mv88e61xx driver
1177 * probing, in this case the global register offsets are not
1178 * initialized yet. Do this initialization here before indirect
1179 * PHY register access.
1181 val = mv88e61xx_priv_reg_offs_pre_init(&temp_phy);
1185 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1189 *phy_id = val << 16;
1191 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1195 *phy_id |= (val & 0xffff);