drivers/net/phy/mscc/mscc_macsec.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Driver for Microsemi VSC85xx PHYs - MACsec support
   4  *
   5  * Author: Antoine Tenart
   6  * License: Dual MIT/GPL
   7  * Copyright (c) 2020 Microsemi Corporation
   8  */
   9
  10 #include <linux/phy.h>
  11 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  12
  13 #include <crypto/skcipher.h>
  14
  15 #include <net/macsec.h>
  16
  17 #include "mscc.h"
  18 #include "mscc_mac.h"
  19 #include "mscc_macsec.h"
  20 #include "mscc_fc_buffer.h"
  21
  22 static u32 vsc8584_macsec_phy_read(struct phy_device *phydev,
  23                                    enum macsec_bank bank, u32 reg)
  24 {
  25         u32 val, val_l = 0, val_h = 0;
  26         unsigned long deadline;
  27         int rc;
  28
  29         rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
  30         if (rc < 0)
  31                 goto failed;
  32
  33         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
  34                     MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
  35
  36         if (bank >> 2 == 0x1)
  37                 /* non-MACsec access */
  38                 bank &= 0x3;
  39         else
  40                 bank = 0;
  41
  42         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
  43                     MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_READ |
  44                     MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
  45                     MSCC_PHY_MACSEC_19_TARGET(bank));
  46
  47         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
  48         do {
  49                 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
  50         } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
  51
  52         val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17);
  53         val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18);
  54
  55 failed:
  56         phy_restore_page(phydev, rc, rc);
  57
  58         return (val_h << 16) | val_l;
  59 }
  60
  61 static void vsc8584_macsec_phy_write(struct phy_device *phydev,
  62                                      enum macsec_bank bank, u32 reg, u32 val)
  63 {
  64         unsigned long deadline;
  65         int rc;
  66
  67         rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
  68         if (rc < 0)
  69                 goto failed;
  70
  71         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
  72                     MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
  73
  74         if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3))
  75                 bank &= 0x3;
  76         else
  77                 /* MACsec access */
  78                 bank = 0;
  79
  80         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val);
  81         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16));
  82
  83         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
  84                     MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
  85                     MSCC_PHY_MACSEC_19_TARGET(bank));
  86
  87         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
  88         do {
  89                 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
  90         } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
  91
  92 failed:
  93         phy_restore_page(phydev, rc, rc);
  94 }
  95
  96 static void vsc8584_macsec_classification(struct phy_device *phydev,
  97                                           enum macsec_bank bank)
  98 {
  99         /* enable VLAN tag parsing */
 100         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,
 101                                  MSCC_MS_SAM_CP_TAG_PARSE_STAG |
 102                                  MSCC_MS_SAM_CP_TAG_PARSE_QTAG |
 103                                  MSCC_MS_SAM_CP_TAG_PARSE_QINQ);
 104 }
 105
 106 static void vsc8584_macsec_flow_default_action(struct phy_device *phydev,
 107                                                enum macsec_bank bank,
 108                                                bool block)
 109 {
 110         u32 port = (bank == MACSEC_INGR) ?
 111                     MSCC_MS_PORT_UNCONTROLLED : MSCC_MS_PORT_COMMON;
 112         u32 action = MSCC_MS_FLOW_BYPASS;
 113
 114         if (block)
 115                 action = MSCC_MS_FLOW_DROP;
 116
 117         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,
 118                                  /* MACsec untagged */
 119                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
 120                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 121                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(port) |
 122                                  /* MACsec tagged */
 123                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
 124                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 125                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(port) |
 126                                  /* Bad tag */
 127                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
 128                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 129                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(port) |
 130                                  /* Kay tag */
 131                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
 132                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 133                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(port));
 134         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,
 135                                  /* MACsec untagged */
 136                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
 137                                  MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 138                                  MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(port) |
 139                                  /* MACsec tagged */
 140                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
 141                                  MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 142                                  MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(port) |
 143                                  /* Bad tag */
 144                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
 145                                  MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 146                                  MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(port) |
 147                                  /* Kay tag */
 148                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
 149                                  MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 150                                  MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(port));
 151 }
 152
 153 static void vsc8584_macsec_integrity_checks(struct phy_device *phydev,
 154                                             enum macsec_bank bank)
 155 {
 156         u32 val;
 157
 158         if (bank != MACSEC_INGR)
 159                 return;
 160
 161         /* Set default rules to pass unmatched frames */
 162         val = vsc8584_macsec_phy_read(phydev, bank,
 163                                       MSCC_MS_PARAMS2_IG_CC_CONTROL);
 164         val |= MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT |
 165                MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT;
 166         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,
 167                                  val);
 168
 169         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,
 170                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG |
 171                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG |
 172                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ);
 173 }
 174
 175 static void vsc8584_macsec_block_init(struct phy_device *phydev,
 176                                       enum macsec_bank bank)
 177 {
 178         u32 val;
 179         int i;
 180
 181         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 182                                  MSCC_MS_ENA_CFG_SW_RST |
 183                                  MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA);
 184
 185         /* Set the MACsec block out of s/w reset and enable clocks */
 186         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 187                                  MSCC_MS_ENA_CFG_CLK_ENA);
 188
 189         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,
 190                                  bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218);
 191         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,
 192                                  MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) |
 193                                  MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2));
 194
 195         /* Clear the counters */
 196         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
 197         val |= MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET;
 198         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
 199
 200         /* Enable octet increment mode */
 201         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,
 202                                  MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE);
 203
 204         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);
 205
 206         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
 207         val |= MSCC_MS_COUNT_CONTROL_RESET_ALL;
 208         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
 209
 210         /* Set the MTU */
 211         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,
 212                                  MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(32761) |
 213                                  MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP);
 214
 215         for (i = 0; i < 8; i++)
 216                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),
 217                                          MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(32761) |
 218                                          MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP);
 219
 220         if (bank == MACSEC_EGR) {
 221                 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);
 222                 val &= ~MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M;
 223                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);
 224
 225                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,
 226                                          MSCC_MS_FC_CFG_FCBUF_ENA |
 227                                          MSCC_MS_FC_CFG_LOW_THRESH(0x1) |
 228                                          MSCC_MS_FC_CFG_HIGH_THRESH(0x4) |
 229                                          MSCC_MS_FC_CFG_LOW_BYTES_VAL(0x4) |
 230                                          MSCC_MS_FC_CFG_HIGH_BYTES_VAL(0x6));
 231         }
 232
 233         vsc8584_macsec_classification(phydev, bank);
 234         vsc8584_macsec_flow_default_action(phydev, bank, false);
 235         vsc8584_macsec_integrity_checks(phydev, bank);
 236
 237         /* Enable the MACsec block */
 238         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 239                                  MSCC_MS_ENA_CFG_CLK_ENA |
 240                                  MSCC_MS_ENA_CFG_MACSEC_ENA |
 241                                  MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(0x5));
 242 }
 243
 244 static void vsc8584_macsec_mac_init(struct phy_device *phydev,
 245                                     enum macsec_bank bank)
 246 {
 247         u32 val;
 248         int i;
 249
 250         /* Clear host & line stats */
 251         for (i = 0; i < 36; i++)
 252                 vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);
 253
 254         val = vsc8584_macsec_phy_read(phydev, bank,
 255                                       MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL);
 256         val &= ~MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M;
 257         val |= MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(2) |
 258                MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(0xffff);
 259         vsc8584_macsec_phy_write(phydev, bank,
 260                                  MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL, val);
 261
 262         val = vsc8584_macsec_phy_read(phydev, bank,
 263                                       MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2);
 264         val |= 0xffff;
 265         vsc8584_macsec_phy_write(phydev, bank,
 266                                  MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2, val);
 267
 268         val = vsc8584_macsec_phy_read(phydev, bank,
 269                                       MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL);
 270         if (bank == HOST_MAC)
 271                 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA |
 272                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA;
 273         else
 274                 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA |
 275                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA |
 276                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE |
 277                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA;
 278         vsc8584_macsec_phy_write(phydev, bank,
 279                                  MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL, val);
 280
 281         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,
 282                                  MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA |
 283                                  MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA |
 284                                  MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA |
 285                                  MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA |
 286                                  MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA |
 287                                  (bank == HOST_MAC ?
 288                                   MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0) |
 289                                  (IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING) ?
 290                                   MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(0x8) : 0));
 291
 292         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
 293         val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC;
 294         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);
 295
 296         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);
 297         val &= ~MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M;
 298         val |= MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(10240);
 299         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);
 300
 301         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,
 302                                  MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA |
 303                                  MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA |
 304                                  MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA |
 305                                  MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA);
 306
 307         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);
 308         val &= ~MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA;
 309         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);
 310
 311         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,
 312                                  MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA |
 313                                  MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA |
 314                                  MSCC_MAC_CFG_ENA_CFG_RX_ENA |
 315                                  MSCC_MAC_CFG_ENA_CFG_TX_ENA);
 316 }
 317
 318 /* Must be called with mdio_lock taken */
 319 static int __vsc8584_macsec_init(struct phy_device *phydev)
 320 {
 321         struct vsc8531_private *priv = phydev->priv;
 322         enum macsec_bank proc_bank;
 323         u32 val;
 324
 325         vsc8584_macsec_block_init(phydev, MACSEC_INGR);
 326         vsc8584_macsec_block_init(phydev, MACSEC_EGR);
 327         vsc8584_macsec_mac_init(phydev, HOST_MAC);
 328         vsc8584_macsec_mac_init(phydev, LINE_MAC);
 329
 330         vsc8584_macsec_phy_write(phydev, FC_BUFFER,
 331                                  MSCC_FCBUF_FC_READ_THRESH_CFG,
 332                                  MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(4) |
 333                                  MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(5));
 334
 335         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG);
 336         val |= MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA |
 337                MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA |
 338                MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA;
 339         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val);
 340
 341         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG,
 342                                  MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(8) |
 343                                  MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(9));
 344
 345         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER,
 346                                       MSCC_FCBUF_TX_DATA_QUEUE_CFG);
 347         val &= ~(MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M |
 348                  MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M);
 349         val |= MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(0) |
 350                 MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(5119);
 351         vsc8584_macsec_phy_write(phydev, FC_BUFFER,
 352                                  MSCC_FCBUF_TX_DATA_QUEUE_CFG, val);
 353
 354         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG);
 355         val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
 356         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
 357
 358         proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2;
 359
 360         val = vsc8584_macsec_phy_read(phydev, proc_bank,
 361                                       MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL);
 362         val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
 363         val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
 364         vsc8584_macsec_phy_write(phydev, proc_bank,
 365                                  MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
 366
 367         return 0;
 368 }
 369
 370 static void vsc8584_macsec_flow(struct phy_device *phydev,
 371                                 struct macsec_flow *flow)
 372 {
 373         struct vsc8531_private *priv = phydev->priv;
 374         enum macsec_bank bank = flow->bank;
 375         u32 val, match = 0, mask = 0, action = 0, idx = flow->index;
 376
 377         if (flow->match.tagged)
 378                 match |= MSCC_MS_SAM_MISC_MATCH_TAGGED;
 379         if (flow->match.untagged)
 380                 match |= MSCC_MS_SAM_MISC_MATCH_UNTAGGED;
 381
 382         if (bank == MACSEC_INGR && flow->assoc_num >= 0) {
 383                 match |= MSCC_MS_SAM_MISC_MATCH_AN(flow->assoc_num);
 384                 mask |= MSCC_MS_SAM_MASK_AN_MASK(0x3);
 385         }
 386
 387         if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {
 388                 u64 sci = (__force u64)flow->rx_sa->sc->sci;
 389
 390                 match |= MSCC_MS_SAM_MISC_MATCH_TCI(BIT(3));
 391                 mask |= MSCC_MS_SAM_MASK_TCI_MASK(BIT(3)) |
 392                         MSCC_MS_SAM_MASK_SCI_MASK;
 393
 394                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
 395                                          lower_32_bits(sci));
 396                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
 397                                          upper_32_bits(sci));
 398         }
 399
 400         if (flow->match.etype) {
 401                 mask |= MSCC_MS_SAM_MASK_MAC_ETYPE_MASK;
 402
 403                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
 404                                          MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE((__force u32)htons(flow->etype)));
 405         }
 406
 407         match |= MSCC_MS_SAM_MISC_MATCH_PRIORITY(flow->priority);
 408
 409         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);
 410         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);
 411
 412         /* Action for matching packets */
 413         if (flow->action.drop)
 414                 action = MSCC_MS_FLOW_DROP;
 415         else if (flow->action.bypass || flow->port == MSCC_MS_PORT_UNCONTROLLED)
 416                 action = MSCC_MS_FLOW_BYPASS;
 417         else
 418                 action = (bank == MACSEC_INGR) ?
 419                          MSCC_MS_FLOW_INGRESS : MSCC_MS_FLOW_EGRESS;
 420
 421         val = MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(action) |
 422               MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 423               MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(flow->port);
 424
 425         if (action == MSCC_MS_FLOW_BYPASS)
 426                 goto write_ctrl;
 427
 428         if (bank == MACSEC_INGR) {
 429                 if (priv->secy->replay_protect)
 430                         val |= MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT;
 431                 if (priv->secy->validate_frames == MACSEC_VALIDATE_STRICT)
 432                         val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_STRICT);
 433                 else if (priv->secy->validate_frames == MACSEC_VALIDATE_CHECK)
 434                         val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_CHECK);
 435         } else if (bank == MACSEC_EGR) {
 436                 if (priv->secy->protect_frames)
 437                         val |= MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME;
 438                 if (priv->secy->tx_sc.encrypt)
 439                         val |= MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT;
 440                 if (priv->secy->tx_sc.send_sci)
 441                         val |= MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI;
 442         }
 443
 444 write_ctrl:
 445         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 446 }
 447
 448 static struct macsec_flow *vsc8584_macsec_find_flow(struct macsec_context *ctx,
 449                                                     enum macsec_bank bank)
 450 {
 451         struct vsc8531_private *priv = ctx->phydev->priv;
 452         struct macsec_flow *pos, *tmp;
 453
 454         list_for_each_entry_safe(pos, tmp, &priv->macsec_flows, list)
 455                 if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank)
 456                         return pos;
 457
 458         return ERR_PTR(-ENOENT);
 459 }
 460
 461 static void vsc8584_macsec_flow_enable(struct phy_device *phydev,
 462                                        struct macsec_flow *flow)
 463 {
 464         enum macsec_bank bank = flow->bank;
 465         u32 val, idx = flow->index;
 466
 467         if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) ||
 468             (flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active))
 469                 return;
 470
 471         /* Enable */
 472         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));
 473
 474         /* Set in-use */
 475         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
 476         val |= MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
 477         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 478 }
 479
 480 static void vsc8584_macsec_flow_disable(struct phy_device *phydev,
 481                                         struct macsec_flow *flow)
 482 {
 483         enum macsec_bank bank = flow->bank;
 484         u32 val, idx = flow->index;
 485
 486         /* Disable */
 487         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));
 488
 489         /* Clear in-use */
 490         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
 491         val &= ~MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
 492         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 493 }
 494
 495 static u32 vsc8584_macsec_flow_context_id(struct macsec_flow *flow)
 496 {
 497         if (flow->bank == MACSEC_INGR)
 498                 return flow->index + MSCC_MS_MAX_FLOWS;
 499
 500         return flow->index;
 501 }
 502
 503 /* Derive the AES key to get a key for the hash autentication */
 504 static int vsc8584_macsec_derive_key(const u8 key[MACSEC_KEYID_LEN],
 505                                      u16 key_len, u8 hkey[16])
 506 {
 507         struct crypto_skcipher *tfm = crypto_alloc_skcipher("ecb(aes)", 0, 0);
 508         struct skcipher_request *req = NULL;
 509         struct scatterlist src, dst;
 510         DECLARE_CRYPTO_WAIT(wait);
 511         u32 input[4] = {0};
 512         int ret;
 513
 514         if (IS_ERR(tfm))
 515                 return PTR_ERR(tfm);
 516
 517         req = skcipher_request_alloc(tfm, GFP_KERNEL);
 518         if (!req) {
 519                 ret = -ENOMEM;
 520                 goto out;
 521         }
 522
 523         skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG |
 524                                       CRYPTO_TFM_REQ_MAY_SLEEP, crypto_req_done,
 525                                       &wait);
 526         ret = crypto_skcipher_setkey(tfm, key, key_len);
 527         if (ret < 0)
 528                 goto out;
 529
 530         sg_init_one(&src, input, 16);
 531         sg_init_one(&dst, hkey, 16);
 532         skcipher_request_set_crypt(req, &src, &dst, 16, NULL);
 533
 534         ret = crypto_wait_req(crypto_skcipher_encrypt(req), &wait);
 535
 536 out:
 537         skcipher_request_free(req);
 538         crypto_free_skcipher(tfm);
 539         return ret;
 540 }
 541
 542 static int vsc8584_macsec_transformation(struct phy_device *phydev,
 543                                          struct macsec_flow *flow)
 544 {
 545         struct vsc8531_private *priv = phydev->priv;
 546         enum macsec_bank bank = flow->bank;
 547         int i, ret, index = flow->index;
 548         u32 rec = 0, control = 0;
 549         u8 hkey[16];
 550         u64 sci;
 551
 552         ret = vsc8584_macsec_derive_key(flow->key, priv->secy->key_len, hkey);
 553         if (ret)
 554                 return ret;
 555
 556         switch (priv->secy->key_len) {
 557         case 16:
 558                 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_128);
 559                 break;
 560         case 32:
 561                 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_256);
 562                 break;
 563         default:
 564                 return -EINVAL;
 565         }
 566
 567         control |= (bank == MACSEC_EGR) ?
 568                    (CONTROL_TYPE_EGRESS | CONTROL_AN(priv->secy->tx_sc.encoding_sa)) :
 569                    (CONTROL_TYPE_INGRESS | CONTROL_SEQ_MASK);
 570
 571         control |= CONTROL_UPDATE_SEQ | CONTROL_ENCRYPT_AUTH | CONTROL_KEY_IN_CTX |
 572                    CONTROL_IV0 | CONTROL_IV1 | CONTROL_IV_IN_SEQ |
 573                    CONTROL_DIGEST_TYPE(0x2) | CONTROL_SEQ_TYPE(0x1) |
 574                    CONTROL_AUTH_ALG(AUTH_ALG_AES_GHAS) | CONTROL_CONTEXT_ID;
 575
 576         /* Set the control word */
 577         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 578                                  control);
 579
 580         /* Set the context ID. Must be unique. */
 581         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 582                                  vsc8584_macsec_flow_context_id(flow));
 583
 584         /* Set the encryption/decryption key */
 585         for (i = 0; i < priv->secy->key_len / sizeof(u32); i++)
 586                 vsc8584_macsec_phy_write(phydev, bank,
 587                                          MSCC_MS_XFORM_REC(index, rec++),
 588                                          ((u32 *)flow->key)[i]);
 589
 590         /* Set the authentication key */
 591         for (i = 0; i < 4; i++)
 592                 vsc8584_macsec_phy_write(phydev, bank,
 593                                          MSCC_MS_XFORM_REC(index, rec++),
 594                                          ((u32 *)hkey)[i]);
 595
 596         /* Initial sequence number */
 597         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 598                                  bank == MACSEC_INGR ?
 599                                  flow->rx_sa->next_pn : flow->tx_sa->next_pn);
 600
 601         if (bank == MACSEC_INGR)
 602                 /* Set the mask (replay window size) */
 603                 vsc8584_macsec_phy_write(phydev, bank,
 604                                          MSCC_MS_XFORM_REC(index, rec++),
 605                                          priv->secy->replay_window);
 606
 607         /* Set the input vectors */
 608         sci = (__force u64)(bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci);
 609         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 610                                  lower_32_bits(sci));
 611         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 612                                  upper_32_bits(sci));
 613
 614         while (rec < 20)
 615                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 616                                          0);
 617
 618         flow->has_transformation = true;
 619         return 0;
 620 }
 621
 622 static struct macsec_flow *vsc8584_macsec_alloc_flow(struct vsc8531_private *priv,
 623                                                      enum macsec_bank bank)
 624 {
 625         unsigned long *bitmap = bank == MACSEC_INGR ?
 626                                 &priv->ingr_flows : &priv->egr_flows;
 627         struct macsec_flow *flow;
 628         int index;
 629
 630         index = find_first_zero_bit(bitmap, MSCC_MS_MAX_FLOWS);
 631
 632         if (index == MSCC_MS_MAX_FLOWS)
 633                 return ERR_PTR(-ENOMEM);
 634
 635         flow = kzalloc(sizeof(*flow), GFP_KERNEL);
 636         if (!flow)
 637                 return ERR_PTR(-ENOMEM);
 638
 639         set_bit(index, bitmap);
 640         flow->index = index;
 641         flow->bank = bank;
 642         flow->priority = 8;
 643         flow->assoc_num = -1;
 644
 645         list_add_tail(&flow->list, &priv->macsec_flows);
 646         return flow;
 647 }
 648
 649 static void vsc8584_macsec_free_flow(struct vsc8531_private *priv,
 650                                      struct macsec_flow *flow)
 651 {
 652         unsigned long *bitmap = flow->bank == MACSEC_INGR ?
 653                                 &priv->ingr_flows : &priv->egr_flows;
 654
 655         list_del(&flow->list);
 656         clear_bit(flow->index, bitmap);
 657         kfree(flow);
 658 }
 659
 660 static int vsc8584_macsec_add_flow(struct phy_device *phydev,
 661                                    struct macsec_flow *flow, bool update)
 662 {
 663         int ret;
 664
 665         flow->port = MSCC_MS_PORT_CONTROLLED;
 666         vsc8584_macsec_flow(phydev, flow);
 667
 668         if (update)
 669                 return 0;
 670
 671         ret = vsc8584_macsec_transformation(phydev, flow);
 672         if (ret) {
 673                 vsc8584_macsec_free_flow(phydev->priv, flow);
 674                 return ret;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int vsc8584_macsec_default_flows(struct phy_device *phydev)
 681 {
 682         struct macsec_flow *flow;
 683
 684         /* Add a rule to let the MKA traffic go through, ingress */
 685         flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_INGR);
 686         if (IS_ERR(flow))
 687                 return PTR_ERR(flow);
 688
 689         flow->priority = 15;
 690         flow->port = MSCC_MS_PORT_UNCONTROLLED;
 691         flow->match.tagged = 1;
 692         flow->match.untagged = 1;
 693         flow->match.etype = 1;
 694         flow->etype = ETH_P_PAE;
 695         flow->action.bypass = 1;
 696
 697         vsc8584_macsec_flow(phydev, flow);
 698         vsc8584_macsec_flow_enable(phydev, flow);
 699
 700         /* Add a rule to let the MKA traffic go through, egress */
 701         flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_EGR);
 702         if (IS_ERR(flow))
 703                 return PTR_ERR(flow);
 704
 705         flow->priority = 15;
 706         flow->port = MSCC_MS_PORT_COMMON;
 707         flow->match.untagged = 1;
 708         flow->match.etype = 1;
 709         flow->etype = ETH_P_PAE;
 710         flow->action.bypass = 1;
 711
 712         vsc8584_macsec_flow(phydev, flow);
 713         vsc8584_macsec_flow_enable(phydev, flow);
 714
 715         return 0;
 716 }
 717
 718 static void vsc8584_macsec_del_flow(struct phy_device *phydev,
 719                                     struct macsec_flow *flow)
 720 {
 721         vsc8584_macsec_flow_disable(phydev, flow);
 722         vsc8584_macsec_free_flow(phydev->priv, flow);
 723 }
 724
 725 static int __vsc8584_macsec_add_rxsa(struct macsec_context *ctx,
 726                                      struct macsec_flow *flow, bool update)
 727 {
 728         struct phy_device *phydev = ctx->phydev;
 729         struct vsc8531_private *priv = phydev->priv;
 730
 731         if (!flow) {
 732                 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_INGR);
 733                 if (IS_ERR(flow))
 734                         return PTR_ERR(flow);
 735
 736                 memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
 737         }
 738
 739         flow->assoc_num = ctx->sa.assoc_num;
 740         flow->rx_sa = ctx->sa.rx_sa;
 741
 742         /* Always match tagged packets on ingress */
 743         flow->match.tagged = 1;
 744         flow->match.sci = 1;
 745
 746         if (priv->secy->validate_frames != MACSEC_VALIDATE_DISABLED)
 747                 flow->match.untagged = 1;
 748
 749         return vsc8584_macsec_add_flow(phydev, flow, update);
 750 }
 751
 752 static int __vsc8584_macsec_add_txsa(struct macsec_context *ctx,
 753                                      struct macsec_flow *flow, bool update)
 754 {
 755         struct phy_device *phydev = ctx->phydev;
 756         struct vsc8531_private *priv = phydev->priv;
 757
 758         if (!flow) {
 759                 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_EGR);
 760                 if (IS_ERR(flow))
 761                         return PTR_ERR(flow);
 762
 763                 memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
 764         }
 765
 766         flow->assoc_num = ctx->sa.assoc_num;
 767         flow->tx_sa = ctx->sa.tx_sa;
 768
 769         /* Always match untagged packets on egress */
 770         flow->match.untagged = 1;
 771
 772         return vsc8584_macsec_add_flow(phydev, flow, update);
 773 }
 774
 775 static int vsc8584_macsec_dev_open(struct macsec_context *ctx)
 776 {
 777         struct vsc8531_private *priv = ctx->phydev->priv;
 778         struct macsec_flow *flow, *tmp;
 779
 780         /* No operation to perform before the commit step */
 781         if (ctx->prepare)
 782                 return 0;
 783
 784         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 785                 vsc8584_macsec_flow_enable(ctx->phydev, flow);
 786
 787         return 0;
 788 }
 789
 790 static int vsc8584_macsec_dev_stop(struct macsec_context *ctx)
 791 {
 792         struct vsc8531_private *priv = ctx->phydev->priv;
 793         struct macsec_flow *flow, *tmp;
 794
 795         /* No operation to perform before the commit step */
 796         if (ctx->prepare)
 797                 return 0;
 798
 799         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 800                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 801
 802         return 0;
 803 }
 804
 805 static int vsc8584_macsec_add_secy(struct macsec_context *ctx)
 806 {
 807         struct vsc8531_private *priv = ctx->phydev->priv;
 808         struct macsec_secy *secy = ctx->secy;
 809
 810         if (ctx->prepare) {
 811                 if (priv->secy)
 812                         return -EEXIST;
 813
 814                 return 0;
 815         }
 816
 817         priv->secy = secy;
 818
 819         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR,
 820                                            secy->validate_frames != MACSEC_VALIDATE_DISABLED);
 821         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR,
 822                                            secy->validate_frames != MACSEC_VALIDATE_DISABLED);
 823
 824         return vsc8584_macsec_default_flows(ctx->phydev);
 825 }
 826
 827 static int vsc8584_macsec_del_secy(struct macsec_context *ctx)
 828 {
 829         struct vsc8531_private *priv = ctx->phydev->priv;
 830         struct macsec_flow *flow, *tmp;
 831
 832         /* No operation to perform before the commit step */
 833         if (ctx->prepare)
 834                 return 0;
 835
 836         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 837                 vsc8584_macsec_del_flow(ctx->phydev, flow);
 838
 839         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR, false);
 840         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR, false);
 841
 842         priv->secy = NULL;
 843         return 0;
 844 }
 845
 846 static int vsc8584_macsec_upd_secy(struct macsec_context *ctx)
 847 {
 848         /* No operation to perform before the commit step */
 849         if (ctx->prepare)
 850                 return 0;
 851
 852         vsc8584_macsec_del_secy(ctx);
 853         return vsc8584_macsec_add_secy(ctx);
 854 }
 855
 856 static int vsc8584_macsec_add_rxsc(struct macsec_context *ctx)
 857 {
 858         /* Nothing to do */
 859         return 0;
 860 }
 861
 862 static int vsc8584_macsec_upd_rxsc(struct macsec_context *ctx)
 863 {
 864         return -EOPNOTSUPP;
 865 }
 866
 867 static int vsc8584_macsec_del_rxsc(struct macsec_context *ctx)
 868 {
 869         struct vsc8531_private *priv = ctx->phydev->priv;
 870         struct macsec_flow *flow, *tmp;
 871
 872         /* No operation to perform before the commit step */
 873         if (ctx->prepare)
 874                 return 0;
 875
 876         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
 877                 if (flow->bank == MACSEC_INGR && flow->rx_sa &&
 878                     flow->rx_sa->sc->sci == ctx->rx_sc->sci)
 879                         vsc8584_macsec_del_flow(ctx->phydev, flow);
 880         }
 881
 882         return 0;
 883 }
 884
 885 static int vsc8584_macsec_add_rxsa(struct macsec_context *ctx)
 886 {
 887         struct macsec_flow *flow = NULL;
 888
 889         if (ctx->prepare)
 890                 return __vsc8584_macsec_add_rxsa(ctx, flow, false);
 891
 892         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 893         if (IS_ERR(flow))
 894                 return PTR_ERR(flow);
 895
 896         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 897         return 0;
 898 }
 899
 900 static int vsc8584_macsec_upd_rxsa(struct macsec_context *ctx)
 901 {
 902         struct macsec_flow *flow;
 903
 904         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 905         if (IS_ERR(flow))
 906                 return PTR_ERR(flow);
 907
 908         if (ctx->prepare) {
 909                 /* Make sure the flow is disabled before updating it */
 910                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 911
 912                 return __vsc8584_macsec_add_rxsa(ctx, flow, true);
 913         }
 914
 915         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 916         return 0;
 917 }
 918
 919 static int vsc8584_macsec_del_rxsa(struct macsec_context *ctx)
 920 {
 921         struct macsec_flow *flow;
 922
 923         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 924
 925         if (IS_ERR(flow))
 926                 return PTR_ERR(flow);
 927         if (ctx->prepare)
 928                 return 0;
 929
 930         vsc8584_macsec_del_flow(ctx->phydev, flow);
 931         return 0;
 932 }
 933
 934 static int vsc8584_macsec_add_txsa(struct macsec_context *ctx)
 935 {
 936         struct macsec_flow *flow = NULL;
 937
 938         if (ctx->prepare)
 939                 return __vsc8584_macsec_add_txsa(ctx, flow, false);
 940
 941         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 942         if (IS_ERR(flow))
 943                 return PTR_ERR(flow);
 944
 945         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 946         return 0;
 947 }
 948
 949 static int vsc8584_macsec_upd_txsa(struct macsec_context *ctx)
 950 {
 951         struct macsec_flow *flow;
 952
 953         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 954         if (IS_ERR(flow))
 955                 return PTR_ERR(flow);
 956
 957         if (ctx->prepare) {
 958                 /* Make sure the flow is disabled before updating it */
 959                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 960
 961                 return __vsc8584_macsec_add_txsa(ctx, flow, true);
 962         }
 963
 964         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 965         return 0;
 966 }
 967
 968 static int vsc8584_macsec_del_txsa(struct macsec_context *ctx)
 969 {
 970         struct macsec_flow *flow;
 971
 972         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 973
 974         if (IS_ERR(flow))
 975                 return PTR_ERR(flow);
 976         if (ctx->prepare)
 977                 return 0;
 978
 979         vsc8584_macsec_del_flow(ctx->phydev, flow);
 980         return 0;
 981 }
 982
 983 static struct macsec_ops vsc8584_macsec_ops = {
 984         .mdo_dev_open = vsc8584_macsec_dev_open,
 985         .mdo_dev_stop = vsc8584_macsec_dev_stop,
 986         .mdo_add_secy = vsc8584_macsec_add_secy,
 987         .mdo_upd_secy = vsc8584_macsec_upd_secy,
 988         .mdo_del_secy = vsc8584_macsec_del_secy,
 989         .mdo_add_rxsc = vsc8584_macsec_add_rxsc,
 990         .mdo_upd_rxsc = vsc8584_macsec_upd_rxsc,
 991         .mdo_del_rxsc = vsc8584_macsec_del_rxsc,
 992         .mdo_add_rxsa = vsc8584_macsec_add_rxsa,
 993         .mdo_upd_rxsa = vsc8584_macsec_upd_rxsa,
 994         .mdo_del_rxsa = vsc8584_macsec_del_rxsa,
 995         .mdo_add_txsa = vsc8584_macsec_add_txsa,
 996         .mdo_upd_txsa = vsc8584_macsec_upd_txsa,
 997         .mdo_del_txsa = vsc8584_macsec_del_txsa,
 998 };
 999
1000 int vsc8584_macsec_init(struct phy_device *phydev)
1001 {
1002         struct vsc8531_private *vsc8531 = phydev->priv;
1003
1004         switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1005         case PHY_ID_VSC856X:
1006         case PHY_ID_VSC8575:
1007         case PHY_ID_VSC8582:
1008         case PHY_ID_VSC8584:
1009                 INIT_LIST_HEAD(&vsc8531->macsec_flows);
1010                 vsc8531->secy = NULL;
1011
1012                 phydev->macsec_ops = &vsc8584_macsec_ops;
1013
1014                 return __vsc8584_macsec_init(phydev);
1015         }
1016
1017         return 0;
1018 }
1019
1020 void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
1021 {
1022         struct vsc8531_private *priv = phydev->priv;
1023         struct macsec_flow *flow, *tmp;
1024         u32 cause, rec;
1025
1026         /* Check MACsec PN rollover */
1027         cause = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1028                                         MSCC_MS_INTR_CTRL_STATUS);
1029         cause &= MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M;
1030         if (!(cause & MACSEC_INTR_CTRL_STATUS_ROLLOVER))
1031                 return;
1032
1033         rec = 6 + priv->secy->key_len / sizeof(u32);
1034         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
1035                 u32 val;
1036
1037                 if (flow->bank != MACSEC_EGR || !flow->has_transformation)
1038                         continue;
1039
1040                 val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1041                                               MSCC_MS_XFORM_REC(flow->index, rec));
1042                 if (val == 0xffffffff) {
1043                         vsc8584_macsec_flow_disable(phydev, flow);
1044                         macsec_pn_wrapped(priv->secy, flow->tx_sa);
1045                         return;
1046                 }
1047         }
1048 }
1049
1050 void vsc8584_config_macsec_intr(struct phy_device *phydev)
1051 {
1052         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1053         phy_write(phydev, MSCC_PHY_EXTENDED_INT, MSCC_PHY_EXTENDED_INT_MS_EGR);
1054         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1055
1056         vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_AIC_CTRL, 0xf);
1057         vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_INTR_CTRL_STATUS,
1058                                  MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(MACSEC_INTR_CTRL_STATUS_ROLLOVER));
1059 }