drivers/net/phy/mscc/mscc_macsec.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Driver for Microsemi VSC85xx PHYs - MACsec support
   4  *
   5  * Author: Antoine Tenart
   6  * License: Dual MIT/GPL
   7  * Copyright (c) 2020 Microsemi Corporation
   8  */
   9
  10 #include <linux/phy.h>
  11 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  12
  13 #include <crypto/skcipher.h>
  14
  15 #include <net/macsec.h>
  16
  17 #include "mscc.h"
  18 #include "mscc_mac.h"
  19 #include "mscc_macsec.h"
  20 #include "mscc_fc_buffer.h"
  21
  22 static u32 vsc8584_macsec_phy_read(struct phy_device *phydev,
  23                                    enum macsec_bank bank, u32 reg)
  24 {
  25         u32 val, val_l = 0, val_h = 0;
  26         unsigned long deadline;
  27         int rc;
  28
  29         rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
  30         if (rc < 0)
  31                 goto failed;
  32
  33         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
  34                     MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
  35
  36         if (bank >> 2 == 0x1)
  37                 /* non-MACsec access */
  38                 bank &= 0x3;
  39         else
  40                 bank = 0;
  41
  42         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
  43                     MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_READ |
  44                     MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
  45                     MSCC_PHY_MACSEC_19_TARGET(bank));
  46
  47         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
  48         do {
  49                 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
  50         } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
  51
  52         val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17);
  53         val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18);
  54
  55 failed:
  56         phy_restore_page(phydev, rc, rc);
  57
  58         return (val_h << 16) | val_l;
  59 }
  60
  61 static void vsc8584_macsec_phy_write(struct phy_device *phydev,
  62                                      enum macsec_bank bank, u32 reg, u32 val)
  63 {
  64         unsigned long deadline;
  65         int rc;
  66
  67         rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC);
  68         if (rc < 0)
  69                 goto failed;
  70
  71         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20,
  72                     MSCC_PHY_MACSEC_20_TARGET(bank >> 2));
  73
  74         if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3))
  75                 bank &= 0x3;
  76         else
  77                 /* MACsec access */
  78                 bank = 0;
  79
  80         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val);
  81         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16));
  82
  83         __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19,
  84                     MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_REG_ADDR(reg) |
  85                     MSCC_PHY_MACSEC_19_TARGET(bank));
  86
  87         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
  88         do {
  89                 val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19);
  90         } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD));
  91
  92 failed:
  93         phy_restore_page(phydev, rc, rc);
  94 }
  95
  96 static void vsc8584_macsec_classification(struct phy_device *phydev,
  97                                           enum macsec_bank bank)
  98 {
  99         /* enable VLAN tag parsing */
 100         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG,
 101                                  MSCC_MS_SAM_CP_TAG_PARSE_STAG |
 102                                  MSCC_MS_SAM_CP_TAG_PARSE_QTAG |
 103                                  MSCC_MS_SAM_CP_TAG_PARSE_QINQ);
 104 }
 105
 106 static void vsc8584_macsec_flow_default_action(struct phy_device *phydev,
 107                                                enum macsec_bank bank,
 108                                                bool block)
 109 {
 110         u32 port = (bank == MACSEC_INGR) ?
 111                     MSCC_MS_PORT_UNCONTROLLED : MSCC_MS_PORT_COMMON;
 112         u32 action = MSCC_MS_FLOW_BYPASS;
 113
 114         if (block)
 115                 action = MSCC_MS_FLOW_DROP;
 116
 117         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP,
 118                                  /* MACsec untagged */
 119                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
 120                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 121                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(port) |
 122                                  /* MACsec tagged */
 123                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
 124                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 125                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(port) |
 126                                  /* Bad tag */
 127                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
 128                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 129                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(port) |
 130                                  /* Kay tag */
 131                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
 132                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 133                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(port));
 134         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP,
 135                                  /* MACsec untagged */
 136                                  MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) |
 137                                  MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 138                                  MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(port) |
 139                                  /* MACsec tagged */
 140                                  MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) |
 141                                  MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 142                                  MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(port) |
 143                                  /* Bad tag */
 144                                  MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) |
 145                                  MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 146                                  MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(port) |
 147                                  /* Kay tag */
 148                                  MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) |
 149                                  MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 150                                  MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(port));
 151 }
 152
 153 static void vsc8584_macsec_integrity_checks(struct phy_device *phydev,
 154                                             enum macsec_bank bank)
 155 {
 156         u32 val;
 157
 158         if (bank != MACSEC_INGR)
 159                 return;
 160
 161         /* Set default rules to pass unmatched frames */
 162         val = vsc8584_macsec_phy_read(phydev, bank,
 163                                       MSCC_MS_PARAMS2_IG_CC_CONTROL);
 164         val |= MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT |
 165                MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT;
 166         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL,
 167                                  val);
 168
 169         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG,
 170                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG |
 171                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG |
 172                                  MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ);
 173 }
 174
 175 static void vsc8584_macsec_block_init(struct phy_device *phydev,
 176                                       enum macsec_bank bank)
 177 {
 178         u32 val;
 179         int i;
 180
 181         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 182                                  MSCC_MS_ENA_CFG_SW_RST |
 183                                  MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA);
 184
 185         /* Set the MACsec block out of s/w reset and enable clocks */
 186         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 187                                  MSCC_MS_ENA_CFG_CLK_ENA);
 188
 189         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL,
 190                                  bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218);
 191         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL,
 192                                  MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) |
 193                                  MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2));
 194
 195         /* Clear the counters */
 196         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
 197         val |= MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET;
 198         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
 199
 200         /* Enable octet increment mode */
 201         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL,
 202                                  MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE);
 203
 204         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3);
 205
 206         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL);
 207         val |= MSCC_MS_COUNT_CONTROL_RESET_ALL;
 208         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val);
 209
 210         /* Set the MTU */
 211         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK,
 212                                  MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(32761) |
 213                                  MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP);
 214
 215         for (i = 0; i < 8; i++)
 216                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i),
 217                                          MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(32761) |
 218                                          MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP);
 219
 220         if (bank == MACSEC_EGR) {
 221                 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS);
 222                 val &= ~MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M;
 223                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val);
 224
 225                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG,
 226                                          MSCC_MS_FC_CFG_FCBUF_ENA |
 227                                          MSCC_MS_FC_CFG_LOW_THRESH(0x1) |
 228                                          MSCC_MS_FC_CFG_HIGH_THRESH(0x4) |
 229                                          MSCC_MS_FC_CFG_LOW_BYTES_VAL(0x4) |
 230                                          MSCC_MS_FC_CFG_HIGH_BYTES_VAL(0x6));
 231         }
 232
 233         vsc8584_macsec_classification(phydev, bank);
 234         vsc8584_macsec_flow_default_action(phydev, bank, false);
 235         vsc8584_macsec_integrity_checks(phydev, bank);
 236
 237         /* Enable the MACsec block */
 238         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG,
 239                                  MSCC_MS_ENA_CFG_CLK_ENA |
 240                                  MSCC_MS_ENA_CFG_MACSEC_ENA |
 241                                  MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(0x5));
 242 }
 243
 244 static void vsc8584_macsec_mac_init(struct phy_device *phydev,
 245                                     enum macsec_bank bank)
 246 {
 247         u32 val;
 248         int i;
 249
 250         /* Clear host & line stats */
 251         for (i = 0; i < 36; i++)
 252                 vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0);
 253
 254         val = vsc8584_macsec_phy_read(phydev, bank,
 255                                       MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL);
 256         val &= ~MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M;
 257         val |= MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(2) |
 258                MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(0xffff);
 259         vsc8584_macsec_phy_write(phydev, bank,
 260                                  MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL, val);
 261
 262         val = vsc8584_macsec_phy_read(phydev, bank,
 263                                       MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2);
 264         val |= 0xffff;
 265         vsc8584_macsec_phy_write(phydev, bank,
 266                                  MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2, val);
 267
 268         val = vsc8584_macsec_phy_read(phydev, bank,
 269                                       MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL);
 270         if (bank == HOST_MAC)
 271                 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA |
 272                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA;
 273         else
 274                 val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA |
 275                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA |
 276                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE |
 277                        MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA;
 278         vsc8584_macsec_phy_write(phydev, bank,
 279                                  MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL, val);
 280
 281         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG,
 282                                  MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA |
 283                                  MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA |
 284                                  MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA |
 285                                  MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA |
 286                                  MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA |
 287                                  (bank == HOST_MAC ?
 288                                   MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0) |
 289                                  (IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING) ?
 290                                   MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(0x8) : 0));
 291
 292         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
 293         val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC;
 294         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val);
 295
 296         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG);
 297         val &= ~MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M;
 298         val |= MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(10240);
 299         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val);
 300
 301         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG,
 302                                  MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA |
 303                                  MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA |
 304                                  MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA |
 305                                  MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA);
 306
 307         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG);
 308         val &= ~MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA;
 309         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val);
 310
 311         vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG,
 312                                  MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA |
 313                                  MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA |
 314                                  MSCC_MAC_CFG_ENA_CFG_RX_ENA |
 315                                  MSCC_MAC_CFG_ENA_CFG_TX_ENA);
 316 }
 317
 318 /* Must be called with mdio_lock taken */
 319 static int __vsc8584_macsec_init(struct phy_device *phydev)
 320 {
 321         struct vsc8531_private *priv = phydev->priv;
 322         enum macsec_bank proc_bank;
 323         u32 val;
 324
 325         vsc8584_macsec_block_init(phydev, MACSEC_INGR);
 326         vsc8584_macsec_block_init(phydev, MACSEC_EGR);
 327         vsc8584_macsec_mac_init(phydev, HOST_MAC);
 328         vsc8584_macsec_mac_init(phydev, LINE_MAC);
 329
 330         vsc8584_macsec_phy_write(phydev, FC_BUFFER,
 331                                  MSCC_FCBUF_FC_READ_THRESH_CFG,
 332                                  MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(4) |
 333                                  MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(5));
 334
 335         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG);
 336         val |= MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA |
 337                MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA |
 338                MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA;
 339         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val);
 340
 341         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG,
 342                                  MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(8) |
 343                                  MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(9));
 344
 345         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER,
 346                                       MSCC_FCBUF_TX_DATA_QUEUE_CFG);
 347         val &= ~(MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M |
 348                  MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M);
 349         val |= MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(0) |
 350                 MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(5119);
 351         vsc8584_macsec_phy_write(phydev, FC_BUFFER,
 352                                  MSCC_FCBUF_TX_DATA_QUEUE_CFG, val);
 353
 354         val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG);
 355         val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
 356         vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
 357
 358         proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2;
 359
 360         val = vsc8584_macsec_phy_read(phydev, proc_bank,
 361                                       MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL);
 362         val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
 363         val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
 364         vsc8584_macsec_phy_write(phydev, proc_bank,
 365                                  MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
 366
 367         return 0;
 368 }
 369
 370 static void vsc8584_macsec_flow(struct phy_device *phydev,
 371                                 struct macsec_flow *flow)
 372 {
 373         struct vsc8531_private *priv = phydev->priv;
 374         enum macsec_bank bank = flow->bank;
 375         u32 val, match = 0, mask = 0, action = 0, idx = flow->index;
 376
 377         if (flow->match.tagged)
 378                 match |= MSCC_MS_SAM_MISC_MATCH_TAGGED;
 379         if (flow->match.untagged)
 380                 match |= MSCC_MS_SAM_MISC_MATCH_UNTAGGED;
 381
 382         if (bank == MACSEC_INGR && flow->assoc_num >= 0) {
 383                 match |= MSCC_MS_SAM_MISC_MATCH_AN(flow->assoc_num);
 384                 mask |= MSCC_MS_SAM_MASK_AN_MASK(0x3);
 385         }
 386
 387         if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {
 388                 match |= MSCC_MS_SAM_MISC_MATCH_TCI(BIT(3));
 389                 mask |= MSCC_MS_SAM_MASK_TCI_MASK(BIT(3)) |
 390                         MSCC_MS_SAM_MASK_SCI_MASK;
 391
 392                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
 393                                          lower_32_bits(flow->rx_sa->sc->sci));
 394                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
 395                                          upper_32_bits(flow->rx_sa->sc->sci));
 396         }
 397
 398         if (flow->match.etype) {
 399                 mask |= MSCC_MS_SAM_MASK_MAC_ETYPE_MASK;
 400
 401                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
 402                                          MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(htons(flow->etype)));
 403         }
 404
 405         match |= MSCC_MS_SAM_MISC_MATCH_PRIORITY(flow->priority);
 406
 407         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match);
 408         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask);
 409
 410         /* Action for matching packets */
 411         if (flow->action.drop)
 412                 action = MSCC_MS_FLOW_DROP;
 413         else if (flow->action.bypass || flow->port == MSCC_MS_PORT_UNCONTROLLED)
 414                 action = MSCC_MS_FLOW_BYPASS;
 415         else
 416                 action = (bank == MACSEC_INGR) ?
 417                          MSCC_MS_FLOW_INGRESS : MSCC_MS_FLOW_EGRESS;
 418
 419         val = MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(action) |
 420               MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(MSCC_MS_ACTION_DROP) |
 421               MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(flow->port);
 422
 423         if (action == MSCC_MS_FLOW_BYPASS)
 424                 goto write_ctrl;
 425
 426         if (bank == MACSEC_INGR) {
 427                 if (priv->secy->replay_protect)
 428                         val |= MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT;
 429                 if (priv->secy->validate_frames == MACSEC_VALIDATE_STRICT)
 430                         val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_STRICT);
 431                 else if (priv->secy->validate_frames == MACSEC_VALIDATE_CHECK)
 432                         val |= MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(MSCC_MS_VALIDATE_CHECK);
 433         } else if (bank == MACSEC_EGR) {
 434                 if (priv->secy->protect_frames)
 435                         val |= MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME;
 436                 if (priv->secy->tx_sc.encrypt)
 437                         val |= MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT;
 438                 if (priv->secy->tx_sc.send_sci)
 439                         val |= MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI;
 440         }
 441
 442 write_ctrl:
 443         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 444 }
 445
 446 static struct macsec_flow *vsc8584_macsec_find_flow(struct macsec_context *ctx,
 447                                                     enum macsec_bank bank)
 448 {
 449         struct vsc8531_private *priv = ctx->phydev->priv;
 450         struct macsec_flow *pos, *tmp;
 451
 452         list_for_each_entry_safe(pos, tmp, &priv->macsec_flows, list)
 453                 if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank)
 454                         return pos;
 455
 456         return ERR_PTR(-ENOENT);
 457 }
 458
 459 static void vsc8584_macsec_flow_enable(struct phy_device *phydev,
 460                                        struct macsec_flow *flow)
 461 {
 462         enum macsec_bank bank = flow->bank;
 463         u32 val, idx = flow->index;
 464
 465         if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) ||
 466             (flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active))
 467                 return;
 468
 469         /* Enable */
 470         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx));
 471
 472         /* Set in-use */
 473         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
 474         val |= MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
 475         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 476 }
 477
 478 static void vsc8584_macsec_flow_disable(struct phy_device *phydev,
 479                                         struct macsec_flow *flow)
 480 {
 481         enum macsec_bank bank = flow->bank;
 482         u32 val, idx = flow->index;
 483
 484         /* Disable */
 485         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx));
 486
 487         /* Clear in-use */
 488         val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx));
 489         val &= ~MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE;
 490         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val);
 491 }
 492
 493 static u32 vsc8584_macsec_flow_context_id(struct macsec_flow *flow)
 494 {
 495         if (flow->bank == MACSEC_INGR)
 496                 return flow->index + MSCC_MS_MAX_FLOWS;
 497
 498         return flow->index;
 499 }
 500
 501 /* Derive the AES key to get a key for the hash autentication */
 502 static int vsc8584_macsec_derive_key(const u8 key[MACSEC_KEYID_LEN],
 503                                      u16 key_len, u8 hkey[16])
 504 {
 505         struct crypto_skcipher *tfm = crypto_alloc_skcipher("ecb(aes)", 0, 0);
 506         struct skcipher_request *req = NULL;
 507         struct scatterlist src, dst;
 508         DECLARE_CRYPTO_WAIT(wait);
 509         u32 input[4] = {0};
 510         int ret;
 511
 512         if (IS_ERR(tfm))
 513                 return PTR_ERR(tfm);
 514
 515         req = skcipher_request_alloc(tfm, GFP_KERNEL);
 516         if (!req) {
 517                 ret = -ENOMEM;
 518                 goto out;
 519         }
 520
 521         skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG |
 522                                       CRYPTO_TFM_REQ_MAY_SLEEP, crypto_req_done,
 523                                       &wait);
 524         ret = crypto_skcipher_setkey(tfm, key, key_len);
 525         if (ret < 0)
 526                 goto out;
 527
 528         sg_init_one(&src, input, 16);
 529         sg_init_one(&dst, hkey, 16);
 530         skcipher_request_set_crypt(req, &src, &dst, 16, NULL);
 531
 532         ret = crypto_wait_req(crypto_skcipher_encrypt(req), &wait);
 533
 534 out:
 535         skcipher_request_free(req);
 536         crypto_free_skcipher(tfm);
 537         return ret;
 538 }
 539
 540 static int vsc8584_macsec_transformation(struct phy_device *phydev,
 541                                          struct macsec_flow *flow)
 542 {
 543         struct vsc8531_private *priv = phydev->priv;
 544         enum macsec_bank bank = flow->bank;
 545         int i, ret, index = flow->index;
 546         u32 rec = 0, control = 0;
 547         u8 hkey[16];
 548         sci_t sci;
 549
 550         ret = vsc8584_macsec_derive_key(flow->key, priv->secy->key_len, hkey);
 551         if (ret)
 552                 return ret;
 553
 554         switch (priv->secy->key_len) {
 555         case 16:
 556                 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_128);
 557                 break;
 558         case 32:
 559                 control |= CONTROL_CRYPTO_ALG(CTRYPTO_ALG_AES_CTR_256);
 560                 break;
 561         default:
 562                 return -EINVAL;
 563         }
 564
 565         control |= (bank == MACSEC_EGR) ?
 566                    (CONTROL_TYPE_EGRESS | CONTROL_AN(priv->secy->tx_sc.encoding_sa)) :
 567                    (CONTROL_TYPE_INGRESS | CONTROL_SEQ_MASK);
 568
 569         control |= CONTROL_UPDATE_SEQ | CONTROL_ENCRYPT_AUTH | CONTROL_KEY_IN_CTX |
 570                    CONTROL_IV0 | CONTROL_IV1 | CONTROL_IV_IN_SEQ |
 571                    CONTROL_DIGEST_TYPE(0x2) | CONTROL_SEQ_TYPE(0x1) |
 572                    CONTROL_AUTH_ALG(AUTH_ALG_AES_GHAS) | CONTROL_CONTEXT_ID;
 573
 574         /* Set the control word */
 575         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 576                                  control);
 577
 578         /* Set the context ID. Must be unique. */
 579         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 580                                  vsc8584_macsec_flow_context_id(flow));
 581
 582         /* Set the encryption/decryption key */
 583         for (i = 0; i < priv->secy->key_len / sizeof(u32); i++)
 584                 vsc8584_macsec_phy_write(phydev, bank,
 585                                          MSCC_MS_XFORM_REC(index, rec++),
 586                                          ((u32 *)flow->key)[i]);
 587
 588         /* Set the authentication key */
 589         for (i = 0; i < 4; i++)
 590                 vsc8584_macsec_phy_write(phydev, bank,
 591                                          MSCC_MS_XFORM_REC(index, rec++),
 592                                          ((u32 *)hkey)[i]);
 593
 594         /* Initial sequence number */
 595         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 596                                  bank == MACSEC_INGR ?
 597                                  flow->rx_sa->next_pn : flow->tx_sa->next_pn);
 598
 599         if (bank == MACSEC_INGR)
 600                 /* Set the mask (replay window size) */
 601                 vsc8584_macsec_phy_write(phydev, bank,
 602                                          MSCC_MS_XFORM_REC(index, rec++),
 603                                          priv->secy->replay_window);
 604
 605         /* Set the input vectors */
 606         sci = bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci;
 607         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 608                                  lower_32_bits(sci));
 609         vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 610                                  upper_32_bits(sci));
 611
 612         while (rec < 20)
 613                 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
 614                                          0);
 615
 616         flow->has_transformation = true;
 617         return 0;
 618 }
 619
 620 static struct macsec_flow *vsc8584_macsec_alloc_flow(struct vsc8531_private *priv,
 621                                                      enum macsec_bank bank)
 622 {
 623         unsigned long *bitmap = bank == MACSEC_INGR ?
 624                                 &priv->ingr_flows : &priv->egr_flows;
 625         struct macsec_flow *flow;
 626         int index;
 627
 628         index = find_first_zero_bit(bitmap, MSCC_MS_MAX_FLOWS);
 629
 630         if (index == MSCC_MS_MAX_FLOWS)
 631                 return ERR_PTR(-ENOMEM);
 632
 633         flow = kzalloc(sizeof(*flow), GFP_KERNEL);
 634         if (!flow)
 635                 return ERR_PTR(-ENOMEM);
 636
 637         set_bit(index, bitmap);
 638         flow->index = index;
 639         flow->bank = bank;
 640         flow->priority = 8;
 641         flow->assoc_num = -1;
 642
 643         list_add_tail(&flow->list, &priv->macsec_flows);
 644         return flow;
 645 }
 646
 647 static void vsc8584_macsec_free_flow(struct vsc8531_private *priv,
 648                                      struct macsec_flow *flow)
 649 {
 650         unsigned long *bitmap = flow->bank == MACSEC_INGR ?
 651                                 &priv->ingr_flows : &priv->egr_flows;
 652
 653         list_del(&flow->list);
 654         clear_bit(flow->index, bitmap);
 655         kfree(flow);
 656 }
 657
 658 static int vsc8584_macsec_add_flow(struct phy_device *phydev,
 659                                    struct macsec_flow *flow, bool update)
 660 {
 661         int ret;
 662
 663         flow->port = MSCC_MS_PORT_CONTROLLED;
 664         vsc8584_macsec_flow(phydev, flow);
 665
 666         if (update)
 667                 return 0;
 668
 669         ret = vsc8584_macsec_transformation(phydev, flow);
 670         if (ret) {
 671                 vsc8584_macsec_free_flow(phydev->priv, flow);
 672                 return ret;
 673         }
 674
 675         return 0;
 676 }
 677
 678 static int vsc8584_macsec_default_flows(struct phy_device *phydev)
 679 {
 680         struct macsec_flow *flow;
 681
 682         /* Add a rule to let the MKA traffic go through, ingress */
 683         flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_INGR);
 684         if (IS_ERR(flow))
 685                 return PTR_ERR(flow);
 686
 687         flow->priority = 15;
 688         flow->port = MSCC_MS_PORT_UNCONTROLLED;
 689         flow->match.tagged = 1;
 690         flow->match.untagged = 1;
 691         flow->match.etype = 1;
 692         flow->etype = ETH_P_PAE;
 693         flow->action.bypass = 1;
 694
 695         vsc8584_macsec_flow(phydev, flow);
 696         vsc8584_macsec_flow_enable(phydev, flow);
 697
 698         /* Add a rule to let the MKA traffic go through, egress */
 699         flow = vsc8584_macsec_alloc_flow(phydev->priv, MACSEC_EGR);
 700         if (IS_ERR(flow))
 701                 return PTR_ERR(flow);
 702
 703         flow->priority = 15;
 704         flow->port = MSCC_MS_PORT_COMMON;
 705         flow->match.untagged = 1;
 706         flow->match.etype = 1;
 707         flow->etype = ETH_P_PAE;
 708         flow->action.bypass = 1;
 709
 710         vsc8584_macsec_flow(phydev, flow);
 711         vsc8584_macsec_flow_enable(phydev, flow);
 712
 713         return 0;
 714 }
 715
 716 static void vsc8584_macsec_del_flow(struct phy_device *phydev,
 717                                     struct macsec_flow *flow)
 718 {
 719         vsc8584_macsec_flow_disable(phydev, flow);
 720         vsc8584_macsec_free_flow(phydev->priv, flow);
 721 }
 722
 723 static int __vsc8584_macsec_add_rxsa(struct macsec_context *ctx,
 724                                      struct macsec_flow *flow, bool update)
 725 {
 726         struct phy_device *phydev = ctx->phydev;
 727         struct vsc8531_private *priv = phydev->priv;
 728
 729         if (!flow) {
 730                 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_INGR);
 731                 if (IS_ERR(flow))
 732                         return PTR_ERR(flow);
 733
 734                 memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
 735         }
 736
 737         flow->assoc_num = ctx->sa.assoc_num;
 738         flow->rx_sa = ctx->sa.rx_sa;
 739
 740         /* Always match tagged packets on ingress */
 741         flow->match.tagged = 1;
 742         flow->match.sci = 1;
 743
 744         if (priv->secy->validate_frames != MACSEC_VALIDATE_DISABLED)
 745                 flow->match.untagged = 1;
 746
 747         return vsc8584_macsec_add_flow(phydev, flow, update);
 748 }
 749
 750 static int __vsc8584_macsec_add_txsa(struct macsec_context *ctx,
 751                                      struct macsec_flow *flow, bool update)
 752 {
 753         struct phy_device *phydev = ctx->phydev;
 754         struct vsc8531_private *priv = phydev->priv;
 755
 756         if (!flow) {
 757                 flow = vsc8584_macsec_alloc_flow(priv, MACSEC_EGR);
 758                 if (IS_ERR(flow))
 759                         return PTR_ERR(flow);
 760
 761                 memcpy(flow->key, ctx->sa.key, priv->secy->key_len);
 762         }
 763
 764         flow->assoc_num = ctx->sa.assoc_num;
 765         flow->tx_sa = ctx->sa.tx_sa;
 766
 767         /* Always match untagged packets on egress */
 768         flow->match.untagged = 1;
 769
 770         return vsc8584_macsec_add_flow(phydev, flow, update);
 771 }
 772
 773 static int vsc8584_macsec_dev_open(struct macsec_context *ctx)
 774 {
 775         struct vsc8531_private *priv = ctx->phydev->priv;
 776         struct macsec_flow *flow, *tmp;
 777
 778         /* No operation to perform before the commit step */
 779         if (ctx->prepare)
 780                 return 0;
 781
 782         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 783                 vsc8584_macsec_flow_enable(ctx->phydev, flow);
 784
 785         return 0;
 786 }
 787
 788 static int vsc8584_macsec_dev_stop(struct macsec_context *ctx)
 789 {
 790         struct vsc8531_private *priv = ctx->phydev->priv;
 791         struct macsec_flow *flow, *tmp;
 792
 793         /* No operation to perform before the commit step */
 794         if (ctx->prepare)
 795                 return 0;
 796
 797         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 798                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 799
 800         return 0;
 801 }
 802
 803 static int vsc8584_macsec_add_secy(struct macsec_context *ctx)
 804 {
 805         struct vsc8531_private *priv = ctx->phydev->priv;
 806         struct macsec_secy *secy = ctx->secy;
 807
 808         if (ctx->prepare) {
 809                 if (priv->secy)
 810                         return -EEXIST;
 811
 812                 return 0;
 813         }
 814
 815         priv->secy = secy;
 816
 817         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR,
 818                                            secy->validate_frames != MACSEC_VALIDATE_DISABLED);
 819         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR,
 820                                            secy->validate_frames != MACSEC_VALIDATE_DISABLED);
 821
 822         return vsc8584_macsec_default_flows(ctx->phydev);
 823 }
 824
 825 static int vsc8584_macsec_del_secy(struct macsec_context *ctx)
 826 {
 827         struct vsc8531_private *priv = ctx->phydev->priv;
 828         struct macsec_flow *flow, *tmp;
 829
 830         /* No operation to perform before the commit step */
 831         if (ctx->prepare)
 832                 return 0;
 833
 834         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list)
 835                 vsc8584_macsec_del_flow(ctx->phydev, flow);
 836
 837         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_EGR, false);
 838         vsc8584_macsec_flow_default_action(ctx->phydev, MACSEC_INGR, false);
 839
 840         priv->secy = NULL;
 841         return 0;
 842 }
 843
 844 static int vsc8584_macsec_upd_secy(struct macsec_context *ctx)
 845 {
 846         /* No operation to perform before the commit step */
 847         if (ctx->prepare)
 848                 return 0;
 849
 850         vsc8584_macsec_del_secy(ctx);
 851         return vsc8584_macsec_add_secy(ctx);
 852 }
 853
 854 static int vsc8584_macsec_add_rxsc(struct macsec_context *ctx)
 855 {
 856         /* Nothing to do */
 857         return 0;
 858 }
 859
 860 static int vsc8584_macsec_upd_rxsc(struct macsec_context *ctx)
 861 {
 862         return -EOPNOTSUPP;
 863 }
 864
 865 static int vsc8584_macsec_del_rxsc(struct macsec_context *ctx)
 866 {
 867         struct vsc8531_private *priv = ctx->phydev->priv;
 868         struct macsec_flow *flow, *tmp;
 869
 870         /* No operation to perform before the commit step */
 871         if (ctx->prepare)
 872                 return 0;
 873
 874         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
 875                 if (flow->bank == MACSEC_INGR && flow->rx_sa &&
 876                     flow->rx_sa->sc->sci == ctx->rx_sc->sci)
 877                         vsc8584_macsec_del_flow(ctx->phydev, flow);
 878         }
 879
 880         return 0;
 881 }
 882
 883 static int vsc8584_macsec_add_rxsa(struct macsec_context *ctx)
 884 {
 885         struct macsec_flow *flow = NULL;
 886
 887         if (ctx->prepare)
 888                 return __vsc8584_macsec_add_rxsa(ctx, flow, false);
 889
 890         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 891         if (IS_ERR(flow))
 892                 return PTR_ERR(flow);
 893
 894         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 895         return 0;
 896 }
 897
 898 static int vsc8584_macsec_upd_rxsa(struct macsec_context *ctx)
 899 {
 900         struct macsec_flow *flow;
 901
 902         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 903         if (IS_ERR(flow))
 904                 return PTR_ERR(flow);
 905
 906         if (ctx->prepare) {
 907                 /* Make sure the flow is disabled before updating it */
 908                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 909
 910                 return __vsc8584_macsec_add_rxsa(ctx, flow, true);
 911         }
 912
 913         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 914         return 0;
 915 }
 916
 917 static int vsc8584_macsec_del_rxsa(struct macsec_context *ctx)
 918 {
 919         struct macsec_flow *flow;
 920
 921         flow = vsc8584_macsec_find_flow(ctx, MACSEC_INGR);
 922
 923         if (IS_ERR(flow))
 924                 return PTR_ERR(flow);
 925         if (ctx->prepare)
 926                 return 0;
 927
 928         vsc8584_macsec_del_flow(ctx->phydev, flow);
 929         return 0;
 930 }
 931
 932 static int vsc8584_macsec_add_txsa(struct macsec_context *ctx)
 933 {
 934         struct macsec_flow *flow = NULL;
 935
 936         if (ctx->prepare)
 937                 return __vsc8584_macsec_add_txsa(ctx, flow, false);
 938
 939         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 940         if (IS_ERR(flow))
 941                 return PTR_ERR(flow);
 942
 943         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 944         return 0;
 945 }
 946
 947 static int vsc8584_macsec_upd_txsa(struct macsec_context *ctx)
 948 {
 949         struct macsec_flow *flow;
 950
 951         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 952         if (IS_ERR(flow))
 953                 return PTR_ERR(flow);
 954
 955         if (ctx->prepare) {
 956                 /* Make sure the flow is disabled before updating it */
 957                 vsc8584_macsec_flow_disable(ctx->phydev, flow);
 958
 959                 return __vsc8584_macsec_add_txsa(ctx, flow, true);
 960         }
 961
 962         vsc8584_macsec_flow_enable(ctx->phydev, flow);
 963         return 0;
 964 }
 965
 966 static int vsc8584_macsec_del_txsa(struct macsec_context *ctx)
 967 {
 968         struct macsec_flow *flow;
 969
 970         flow = vsc8584_macsec_find_flow(ctx, MACSEC_EGR);
 971
 972         if (IS_ERR(flow))
 973                 return PTR_ERR(flow);
 974         if (ctx->prepare)
 975                 return 0;
 976
 977         vsc8584_macsec_del_flow(ctx->phydev, flow);
 978         return 0;
 979 }
 980
 981 static struct macsec_ops vsc8584_macsec_ops = {
 982         .mdo_dev_open = vsc8584_macsec_dev_open,
 983         .mdo_dev_stop = vsc8584_macsec_dev_stop,
 984         .mdo_add_secy = vsc8584_macsec_add_secy,
 985         .mdo_upd_secy = vsc8584_macsec_upd_secy,
 986         .mdo_del_secy = vsc8584_macsec_del_secy,
 987         .mdo_add_rxsc = vsc8584_macsec_add_rxsc,
 988         .mdo_upd_rxsc = vsc8584_macsec_upd_rxsc,
 989         .mdo_del_rxsc = vsc8584_macsec_del_rxsc,
 990         .mdo_add_rxsa = vsc8584_macsec_add_rxsa,
 991         .mdo_upd_rxsa = vsc8584_macsec_upd_rxsa,
 992         .mdo_del_rxsa = vsc8584_macsec_del_rxsa,
 993         .mdo_add_txsa = vsc8584_macsec_add_txsa,
 994         .mdo_upd_txsa = vsc8584_macsec_upd_txsa,
 995         .mdo_del_txsa = vsc8584_macsec_del_txsa,
 996 };
 997
 998 int vsc8584_macsec_init(struct phy_device *phydev)
 999 {
1000         struct vsc8531_private *vsc8531 = phydev->priv;
1001
1002         switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1003         case PHY_ID_VSC856X:
1004         case PHY_ID_VSC8575:
1005         case PHY_ID_VSC8582:
1006         case PHY_ID_VSC8584:
1007                 INIT_LIST_HEAD(&vsc8531->macsec_flows);
1008                 vsc8531->secy = NULL;
1009
1010                 phydev->macsec_ops = &vsc8584_macsec_ops;
1011
1012                 return __vsc8584_macsec_init(phydev);
1013         }
1014
1015         return 0;
1016 }
1017
1018 void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
1019 {
1020         struct vsc8531_private *priv = phydev->priv;
1021         struct macsec_flow *flow, *tmp;
1022         u32 cause, rec;
1023
1024         /* Check MACsec PN rollover */
1025         cause = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1026                                         MSCC_MS_INTR_CTRL_STATUS);
1027         cause &= MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M;
1028         if (!(cause & MACSEC_INTR_CTRL_STATUS_ROLLOVER))
1029                 return;
1030
1031         rec = 6 + priv->secy->key_len / sizeof(u32);
1032         list_for_each_entry_safe(flow, tmp, &priv->macsec_flows, list) {
1033                 u32 val;
1034
1035                 if (flow->bank != MACSEC_EGR || !flow->has_transformation)
1036                         continue;
1037
1038                 val = vsc8584_macsec_phy_read(phydev, MACSEC_EGR,
1039                                               MSCC_MS_XFORM_REC(flow->index, rec));
1040                 if (val == 0xffffffff) {
1041                         vsc8584_macsec_flow_disable(phydev, flow);
1042                         macsec_pn_wrapped(priv->secy, flow->tx_sa);
1043                         return;
1044                 }
1045         }
1046 }
1047
1048 void vsc8584_config_macsec_intr(struct phy_device *phydev)
1049 {
1050         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1051         phy_write(phydev, MSCC_PHY_EXTENDED_INT, MSCC_PHY_EXTENDED_INT_MS_EGR);
1052         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1053
1054         vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_AIC_CTRL, 0xf);
1055         vsc8584_macsec_phy_write(phydev, MACSEC_EGR, MSCC_MS_INTR_CTRL_STATUS,
1056                                  MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(MACSEC_INTR_CTRL_STATUS_ROLLOVER));
1057 }