1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Driver for Microsemi VSC85xx PHYs
5 * Copyright (c) 2016 Microsemi Corporation
11 #if IS_ENABLED(CONFIG_MACSEC)
12 #include "mscc_macsec.h"
15 enum rgmii_rx_clock_delay {
16 RGMII_RX_CLK_DELAY_0_2_NS = 0,
17 RGMII_RX_CLK_DELAY_0_8_NS = 1,
18 RGMII_RX_CLK_DELAY_1_1_NS = 2,
19 RGMII_RX_CLK_DELAY_1_7_NS = 3,
20 RGMII_RX_CLK_DELAY_2_0_NS = 4,
21 RGMII_RX_CLK_DELAY_2_3_NS = 5,
22 RGMII_RX_CLK_DELAY_2_6_NS = 6,
23 RGMII_RX_CLK_DELAY_3_4_NS = 7
26 /* Microsemi VSC85xx PHY registers */
27 /* IEEE 802. Std Registers */
28 #define MSCC_PHY_BYPASS_CONTROL 18
29 #define DISABLE_HP_AUTO_MDIX_MASK 0x0080
30 #define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
31 #define DISABLE_POLARITY_CORR_MASK 0x0010
32 #define PARALLEL_DET_IGNORE_ADVERTISED 0x0008
34 #define MSCC_PHY_EXT_CNTL_STATUS 22
35 #define SMI_BROADCAST_WR_EN 0x0001
37 #define MSCC_PHY_ERR_RX_CNT 19
38 #define MSCC_PHY_ERR_FALSE_CARRIER_CNT 20
39 #define MSCC_PHY_ERR_LINK_DISCONNECT_CNT 21
40 #define ERR_CNT_MASK GENMASK(7, 0)
42 #define MSCC_PHY_EXT_PHY_CNTL_1 23
43 #define MAC_IF_SELECTION_MASK 0x1800
44 #define MAC_IF_SELECTION_GMII 0
45 #define MAC_IF_SELECTION_RMII 1
46 #define MAC_IF_SELECTION_RGMII 2
47 #define MAC_IF_SELECTION_POS 11
48 #define VSC8584_MAC_IF_SELECTION_MASK 0x1000
49 #define VSC8584_MAC_IF_SELECTION_SGMII 0
50 #define VSC8584_MAC_IF_SELECTION_1000BASEX 1
51 #define VSC8584_MAC_IF_SELECTION_POS 12
52 #define FAR_END_LOOPBACK_MODE_MASK 0x0008
53 #define MEDIA_OP_MODE_MASK 0x0700
54 #define MEDIA_OP_MODE_COPPER 0
55 #define MEDIA_OP_MODE_SERDES 1
56 #define MEDIA_OP_MODE_1000BASEX 2
57 #define MEDIA_OP_MODE_100BASEFX 3
58 #define MEDIA_OP_MODE_AMS_COPPER_SERDES 5
59 #define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6
60 #define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7
61 #define MEDIA_OP_MODE_POS 8
63 #define MSCC_PHY_EXT_PHY_CNTL_2 24
65 #define MII_VSC85XX_INT_MASK 25
66 #define MII_VSC85XX_INT_MASK_MDINT BIT(15)
67 #define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13)
68 #define MII_VSC85XX_INT_MASK_WOL BIT(6)
69 #define MII_VSC85XX_INT_MASK_EXT BIT(5)
70 #define MII_VSC85XX_INT_STATUS 26
72 #define MII_VSC85XX_INT_MASK_MASK (MII_VSC85XX_INT_MASK_MDINT | \
73 MII_VSC85XX_INT_MASK_LINK_CHG | \
74 MII_VSC85XX_INT_MASK_EXT)
76 #define MSCC_PHY_WOL_MAC_CONTROL 27
77 #define EDGE_RATE_CNTL_POS 5
78 #define EDGE_RATE_CNTL_MASK 0x00E0
80 #define MSCC_PHY_DEV_AUX_CNTL 28
81 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
83 #define MSCC_PHY_LED_MODE_SEL 29
84 #define LED_MODE_SEL_POS(x) ((x) * 4)
85 #define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
86 #define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
88 #define MSCC_EXT_PAGE_CSR_CNTL_17 17
89 #define MSCC_EXT_PAGE_CSR_CNTL_18 18
91 #define MSCC_EXT_PAGE_CSR_CNTL_19 19
92 #define MSCC_PHY_CSR_CNTL_19_REG_ADDR(x) (x)
93 #define MSCC_PHY_CSR_CNTL_19_TARGET(x) ((x) << 12)
94 #define MSCC_PHY_CSR_CNTL_19_READ BIT(14)
95 #define MSCC_PHY_CSR_CNTL_19_CMD BIT(15)
97 #define MSCC_EXT_PAGE_CSR_CNTL_20 20
98 #define MSCC_PHY_CSR_CNTL_20_TARGET(x) (x)
100 #define PHY_MCB_TARGET 0x07
101 #define PHY_MCB_S6G_WRITE BIT(31)
102 #define PHY_MCB_S6G_READ BIT(30)
104 #define PHY_S6G_PLL5G_CFG0 0x06
105 #define PHY_S6G_LCPLL_CFG 0x11
106 #define PHY_S6G_PLL_CFG 0x2b
107 #define PHY_S6G_COMMON_CFG 0x2c
108 #define PHY_S6G_GPC_CFG 0x2e
109 #define PHY_S6G_MISC_CFG 0x3b
110 #define PHY_MCB_S6G_CFG 0x3f
111 #define PHY_S6G_DFT_CFG2 0x3e
112 #define PHY_S6G_PLL_STATUS 0x31
113 #define PHY_S6G_IB_STATUS0 0x2f
115 #define PHY_S6G_SYS_RST_POS 31
116 #define PHY_S6G_ENA_LANE_POS 18
117 #define PHY_S6G_ENA_LOOP_POS 8
118 #define PHY_S6G_QRATE_POS 6
119 #define PHY_S6G_IF_MODE_POS 4
120 #define PHY_S6G_PLL_ENA_OFFS_POS 21
121 #define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8
122 #define PHY_S6G_PLL_FSM_ENA_POS 7
124 #define MSCC_EXT_PAGE_ACCESS 31
125 #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
126 #define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
127 #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
128 #define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */
129 #define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */
130 #define MSCC_PHY_PAGE_CSR_CNTL MSCC_PHY_PAGE_EXTENDED_4
131 #define MSCC_PHY_PAGE_MACSEC MSCC_PHY_PAGE_EXTENDED_4
132 /* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs
133 * in the same package.
135 #define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
136 #define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
137 #define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
139 /* Extended Page 1 Registers */
140 #define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT 18
141 #define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)
143 #define MSCC_PHY_EXT_MODE_CNTL 19
144 #define FORCE_MDI_CROSSOVER_MASK 0x000C
145 #define FORCE_MDI_CROSSOVER_MDIX 0x000C
146 #define FORCE_MDI_CROSSOVER_MDI 0x0008
148 #define MSCC_PHY_ACTIPHY_CNTL 20
149 #define PHY_ADDR_REVERSED 0x0200
150 #define DOWNSHIFT_CNTL_MASK 0x001C
151 #define DOWNSHIFT_EN 0x0010
152 #define DOWNSHIFT_CNTL_POS 2
154 #define MSCC_PHY_EXT_PHY_CNTL_4 23
155 #define PHY_CNTL_4_ADDR_POS 11
157 #define MSCC_PHY_VERIPHY_CNTL_2 25
159 #define MSCC_PHY_VERIPHY_CNTL_3 26
161 /* Extended Page 2 Registers */
162 #define MSCC_PHY_CU_PMD_TX_CNTL 16
164 #define MSCC_PHY_RGMII_CNTL 20
165 #define RGMII_RX_CLK_DELAY_MASK 0x0070
166 #define RGMII_RX_CLK_DELAY_POS 4
168 #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
169 #define MSCC_PHY_WOL_MID_MAC_ADDR 22
170 #define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
171 #define MSCC_PHY_WOL_LOWER_PASSWD 24
172 #define MSCC_PHY_WOL_MID_PASSWD 25
173 #define MSCC_PHY_WOL_UPPER_PASSWD 26
175 #define MSCC_PHY_WOL_MAC_CONTROL 27
176 #define SECURE_ON_ENABLE 0x8000
177 #define SECURE_ON_PASSWD_LEN_4 0x4000
179 #define MSCC_PHY_EXTENDED_INT 28
180 #define MSCC_PHY_EXTENDED_INT_MS_EGR BIT(9)
182 /* Extended Page 3 Registers */
183 #define MSCC_PHY_SERDES_TX_VALID_CNT 21
184 #define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22
185 #define MSCC_PHY_SERDES_RX_VALID_CNT 28
186 #define MSCC_PHY_SERDES_RX_CRC_ERR_CNT 29
188 /* Extended page GPIO Registers */
189 #define MSCC_DW8051_CNTL_STATUS 0
190 #define MICRO_NSOFT_RESET 0x8000
191 #define RUN_FROM_INT_ROM 0x4000
192 #define AUTOINC_ADDR 0x2000
193 #define PATCH_RAM_CLK 0x1000
194 #define MICRO_PATCH_EN 0x0080
195 #define DW8051_CLK_EN 0x0010
196 #define MICRO_CLK_EN 0x0008
197 #define MICRO_CLK_DIVIDE(x) ((x) >> 1)
198 #define MSCC_DW8051_VLD_MASK 0xf1ff
200 /* x Address in range 1-4 */
201 #define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1)
202 #define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2)
203 #define MSCC_INT_MEM_ADDR 11
205 #define MSCC_INT_MEM_CNTL 12
206 #define READ_SFR 0x6000
207 #define READ_PRAM 0x4000
208 #define READ_ROM 0x2000
209 #define READ_RAM 0x0000
210 #define INT_MEM_WRITE_EN 0x1000
211 #define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1))
212 #define INT_MEM_DATA_M 0x00ff
213 #define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))
215 #define MSCC_PHY_PROC_CMD 18
216 #define PROC_CMD_NCOMPLETED 0x8000
217 #define PROC_CMD_FAILED 0x4000
218 #define PROC_CMD_SGMII_PORT(x) ((x) << 8)
219 #define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4)
220 #define PROC_CMD_QSGMII_PORT 0x0c00
221 #define PROC_CMD_RST_CONF_PORT 0x0080
222 #define PROC_CMD_RECONF_PORT 0x0000
223 #define PROC_CMD_READ_MOD_WRITE_PORT 0x0040
224 #define PROC_CMD_WRITE 0x0040
225 #define PROC_CMD_READ 0x0000
226 #define PROC_CMD_FIBER_DISABLE 0x0020
227 #define PROC_CMD_FIBER_100BASE_FX 0x0010
228 #define PROC_CMD_FIBER_1000BASE_X 0x0000
229 #define PROC_CMD_SGMII_MAC 0x0030
230 #define PROC_CMD_QSGMII_MAC 0x0020
231 #define PROC_CMD_NO_MAC_CONF 0x0000
232 #define PROC_CMD_1588_DEFAULT_INIT 0x0010
233 #define PROC_CMD_NOP 0x000f
234 #define PROC_CMD_PHY_INIT 0x000a
235 #define PROC_CMD_CRC16 0x0008
236 #define PROC_CMD_FIBER_MEDIA_CONF 0x0001
237 #define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000
238 #define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500
240 #define MSCC_PHY_MAC_CFG_FASTLINK 19
241 #define MAC_CFG_MASK 0xc000
242 #define MAC_CFG_SGMII 0x0000
243 #define MAC_CFG_QSGMII 0x4000
244 #define MAC_CFG_RGMII 0x8000
246 /* Test page Registers */
247 #define MSCC_PHY_TEST_PAGE_5 5
248 #define MSCC_PHY_TEST_PAGE_8 8
249 #define MSCC_PHY_TEST_PAGE_9 9
250 #define MSCC_PHY_TEST_PAGE_20 20
251 #define MSCC_PHY_TEST_PAGE_24 24
253 /* Token ring page Registers */
254 #define MSCC_PHY_TR_CNTL 16
255 #define TR_WRITE 0x8000
256 #define TR_ADDR(x) (0x7fff & (x))
257 #define MSCC_PHY_TR_LSB 17
258 #define MSCC_PHY_TR_MSB 18
260 /* Microsemi PHY ID's
261 * Code assumes lowest nibble is 0
263 #define PHY_ID_VSC8504 0x000704c0
264 #define PHY_ID_VSC8514 0x00070670
265 #define PHY_ID_VSC8530 0x00070560
266 #define PHY_ID_VSC8531 0x00070570
267 #define PHY_ID_VSC8540 0x00070760
268 #define PHY_ID_VSC8541 0x00070770
269 #define PHY_ID_VSC8552 0x000704e0
270 #define PHY_ID_VSC856X 0x000707e0
271 #define PHY_ID_VSC8572 0x000704d0
272 #define PHY_ID_VSC8574 0x000704a0
273 #define PHY_ID_VSC8575 0x000707d0
274 #define PHY_ID_VSC8582 0x000707b0
275 #define PHY_ID_VSC8584 0x000707c0
277 #define MSCC_VDDMAC_1500 1500
278 #define MSCC_VDDMAC_1800 1800
279 #define MSCC_VDDMAC_2500 2500
280 #define MSCC_VDDMAC_3300 3300
282 #define DOWNSHIFT_COUNT_MAX 5
286 #define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
287 BIT(VSC8531_LINK_1000_ACTIVITY) | \
288 BIT(VSC8531_LINK_100_ACTIVITY) | \
289 BIT(VSC8531_LINK_10_ACTIVITY) | \
290 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
291 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
292 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
293 BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \
294 BIT(VSC8531_DUPLEX_COLLISION) | \
295 BIT(VSC8531_COLLISION) | \
296 BIT(VSC8531_ACTIVITY) | \
297 BIT(VSC8584_100FX_1000X_ACTIVITY) | \
298 BIT(VSC8531_AUTONEG_FAULT) | \
299 BIT(VSC8531_SERIAL_MODE) | \
300 BIT(VSC8531_FORCE_LED_OFF) | \
301 BIT(VSC8531_FORCE_LED_ON))
303 #define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
304 BIT(VSC8531_LINK_1000_ACTIVITY) | \
305 BIT(VSC8531_LINK_100_ACTIVITY) | \
306 BIT(VSC8531_LINK_10_ACTIVITY) | \
307 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
308 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
309 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
310 BIT(VSC8531_DUPLEX_COLLISION) | \
311 BIT(VSC8531_COLLISION) | \
312 BIT(VSC8531_ACTIVITY) | \
313 BIT(VSC8531_AUTONEG_FAULT) | \
314 BIT(VSC8531_SERIAL_MODE) | \
315 BIT(VSC8531_FORCE_LED_OFF) | \
316 BIT(VSC8531_FORCE_LED_ON))
318 #define MSCC_VSC8584_REVB_INT8051_FW "microchip/mscc_vsc8584_revb_int8051_fb48.bin"
319 #define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
320 #define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
322 #define MSCC_VSC8574_REVB_INT8051_FW "microchip/mscc_vsc8574_revb_int8051_29e8.bin"
323 #define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
324 #define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
326 #define VSC8584_REVB 0x0001
327 #define MSCC_DEV_REV_MASK GENMASK(3, 0)
334 struct vsc85xx_hw_stat {
341 struct vsc8531_private {
344 u32 leds_mode[MAX_LEDS];
346 const struct vsc85xx_hw_stat *hw_stats;
350 /* For multiple port PHYs; the MDIO address of the base PHY in the
353 unsigned int base_addr;
355 #if IS_ENABLED(CONFIG_MACSEC)
357 * - One SecY per device (enforced at the s/w implementation level)
358 * - macsec_flows: list of h/w flows
359 * - ingr_flows: bitmap of ingress flows
360 * - egr_flows: bitmap of egress flows
362 struct macsec_secy *secy;
363 struct list_head macsec_flows;
364 unsigned long ingr_flows;
365 unsigned long egr_flows;
369 #ifdef CONFIG_OF_MDIO
370 struct vsc8531_edge_rate_table {
374 #endif /* CONFIG_OF_MDIO */
376 #if IS_ENABLED(CONFIG_MACSEC)
377 int vsc8584_macsec_init(struct phy_device *phydev);
378 void vsc8584_handle_macsec_interrupt(struct phy_device *phydev);
379 void vsc8584_config_macsec_intr(struct phy_device *phydev);
381 static inline int vsc8584_macsec_init(struct phy_device *phydev)
385 static inline void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
388 static inline void vsc8584_config_macsec_intr(struct phy_device *phydev)
393 #endif /* _MSCC_PHY_H_ */