1 // SPDX-License-Identifier: GPL-2.0+
3 * Motorcomm 8511/8521/8531S PHY driver.
5 * Author: Peter Geis <pgwipeout@gmail.com>
6 * Author: Frank <Frank.Sae@motor-comm.com>
9 #include <linux/etherdevice.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/phy.h>
14 #define PHY_ID_YT8511 0x0000010a
15 #define PHY_ID_YT8521 0x0000011a
16 #define PHY_ID_YT8531S 0x4f51e91a
18 /* YT8521/YT8531S Register Overview
19 * UTP Register space | FIBER Register space
20 * ------------------------------------------------------------
21 * | UTP MII | FIBER MII |
23 * | UTP Extended | FIBER Extended |
24 * ------------------------------------------------------------
26 * ------------------------------------------------------------
29 /* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */
31 /* Specific Function Control Register */
32 #define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10
34 /* 2b00 Manual MDI configuration
35 * 2b01 Manual MDIX configuration
37 * 2b11 Enable automatic crossover for all modes *default*
39 #define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5))
40 #define YTPHY_SFCR_CROSSOVER_EN BIT(3)
41 #define YTPHY_SFCR_SQE_TEST_EN BIT(2)
42 #define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1)
43 #define YTPHY_SFCR_JABBER_DIS BIT(0)
45 /* Specific Status Register */
46 #define YTPHY_SPECIFIC_STATUS_REG 0x11
47 #define YTPHY_SSR_SPEED_MODE_OFFSET 14
49 #define YTPHY_SSR_SPEED_MODE_MASK (BIT(15) | BIT(14))
50 #define YTPHY_SSR_SPEED_10M 0x0
51 #define YTPHY_SSR_SPEED_100M 0x1
52 #define YTPHY_SSR_SPEED_1000M 0x2
53 #define YTPHY_SSR_DUPLEX_OFFSET 13
54 #define YTPHY_SSR_DUPLEX BIT(13)
55 #define YTPHY_SSR_PAGE_RECEIVED BIT(12)
56 #define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11)
57 #define YTPHY_SSR_LINK BIT(10)
58 #define YTPHY_SSR_MDIX_CROSSOVER BIT(6)
59 #define YTPHY_SSR_DOWNGRADE BIT(5)
60 #define YTPHY_SSR_TRANSMIT_PAUSE BIT(3)
61 #define YTPHY_SSR_RECEIVE_PAUSE BIT(2)
62 #define YTPHY_SSR_POLARITY BIT(1)
63 #define YTPHY_SSR_JABBER BIT(0)
65 /* Interrupt enable Register */
66 #define YTPHY_INTERRUPT_ENABLE_REG 0x12
67 #define YTPHY_IER_WOL BIT(6)
69 /* Interrupt Status Register */
70 #define YTPHY_INTERRUPT_STATUS_REG 0x13
71 #define YTPHY_ISR_AUTONEG_ERR BIT(15)
72 #define YTPHY_ISR_SPEED_CHANGED BIT(14)
73 #define YTPHY_ISR_DUPLEX_CHANGED BIT(13)
74 #define YTPHY_ISR_PAGE_RECEIVED BIT(12)
75 #define YTPHY_ISR_LINK_FAILED BIT(11)
76 #define YTPHY_ISR_LINK_SUCCESSED BIT(10)
77 #define YTPHY_ISR_WOL BIT(6)
78 #define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5)
79 #define YTPHY_ISR_SERDES_LINK_FAILED BIT(3)
80 #define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2)
81 #define YTPHY_ISR_POLARITY_CHANGED BIT(1)
82 #define YTPHY_ISR_JABBER_HAPPENED BIT(0)
84 /* Speed Auto Downgrade Control Register */
85 #define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14
86 #define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5)
88 /* If these bits are set to 3, the PHY attempts five times ( 3(set value) +
89 * additional 2) before downgrading, default 0x3
91 #define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2)
93 /* Rx Error Counter Register */
94 #define YTPHY_RX_ERROR_COUNTER_REG 0x15
96 /* Extended Register's Address Offset Register */
97 #define YTPHY_PAGE_SELECT 0x1E
99 /* Extended Register's Data Register */
100 #define YTPHY_PAGE_DATA 0x1F
102 /* FIBER Auto-Negotiation link partner ability */
103 #define YTPHY_FLPA_PAUSE (0x3 << 7)
104 #define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7)
106 #define YT8511_PAGE_SELECT 0x1e
107 #define YT8511_PAGE 0x1f
108 #define YT8511_EXT_CLK_GATE 0x0c
109 #define YT8511_EXT_DELAY_DRIVE 0x0d
110 #define YT8511_EXT_SLEEP_CTRL 0x27
113 * 2b01 25m from xtl *default*
117 #define YT8511_CLK_125M (BIT(2) | BIT(1))
118 #define YT8511_PLLON_SLP BIT(14)
120 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
121 #define YT8511_DELAY_RX BIT(0)
123 /* TX Gig-E Delay is bits 7:4, default 0x5
124 * TX Fast-E Delay is bits 15:12, default 0xf
125 * Delay = 150ps * N - 250ps
126 * On = 2000ps, off = 50ps
128 #define YT8511_DELAY_GE_TX_EN (0xf << 4)
129 #define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
130 #define YT8511_DELAY_FE_TX_EN (0xf << 12)
131 #define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
133 /* Extended register is different from MMD Register and MII Register.
134 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to
135 * operate extended register.
136 * Extended Register start
139 /* Phy gmii clock gating Register */
140 #define YT8521_CLOCK_GATING_REG 0xC
141 #define YT8521_CGR_RX_CLK_EN BIT(12)
143 #define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27
144 #define YT8521_ESC1R_SLEEP_SW BIT(15)
145 #define YT8521_ESC1R_PLLON_SLP BIT(14)
147 /* Phy fiber Link timer cfg2 Register */
148 #define YT8521_LINK_TIMER_CFG2_REG 0xA5
149 #define YT8521_LTCR_EN_AUTOSEN BIT(15)
151 /* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers
152 * of yt8521 phy. There is no need to switch reg space when operating these
156 #define YT8521_REG_SPACE_SELECT_REG 0xA000
157 #define YT8521_RSSR_SPACE_MASK BIT(1)
158 #define YT8521_RSSR_FIBER_SPACE (0x1 << 1)
159 #define YT8521_RSSR_UTP_SPACE (0x0 << 1)
160 #define YT8521_RSSR_TO_BE_ARBITRATED (0xFF)
162 #define YT8521_CHIP_CONFIG_REG 0xA001
163 #define YT8521_CCR_SW_RST BIT(15)
164 /* 1b0 disable 1.9ns rxc clock delay *default*
165 * 1b1 enable 1.9ns rxc clock delay
167 #define YT8521_CCR_RXC_DLY_EN BIT(8)
168 #define YT8521_CCR_RXC_DLY_1_900_NS 1900
170 #define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0))
171 #define YT8521_CCR_MODE_UTP_TO_RGMII 0
172 #define YT8521_CCR_MODE_FIBER_TO_RGMII 1
173 #define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2
174 #define YT8521_CCR_MODE_UTP_TO_SGMII 3
175 #define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4
176 #define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5
177 #define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6
178 #define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7
180 /* 3 phy polling modes,poll mode combines utp and fiber mode*/
181 #define YT8521_MODE_FIBER 0x1
182 #define YT8521_MODE_UTP 0x2
183 #define YT8521_MODE_POLL 0x3
185 #define YT8521_RGMII_CONFIG1_REG 0xA003
186 /* 1b0 use original tx_clk_rgmii *default*
187 * 1b1 use inverted tx_clk_rgmii.
189 #define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14)
190 /* TX Gig-E Delay is bits 3:0, default 0x1
191 * TX Fast-E Delay is bits 7:4, default 0xf
192 * RX Delay is bits 13:10, default 0x0
194 * On = 2250ps, off = 0ps
196 #define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10)
197 #define YT8521_RC1R_RX_DELAY_EN (0xF << 10)
198 #define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10)
199 #define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4)
200 #define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4)
201 #define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4)
202 #define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0)
203 #define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0)
204 #define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0)
205 #define YT8521_RC1R_RGMII_0_000_NS 0
206 #define YT8521_RC1R_RGMII_0_150_NS 1
207 #define YT8521_RC1R_RGMII_0_300_NS 2
208 #define YT8521_RC1R_RGMII_0_450_NS 3
209 #define YT8521_RC1R_RGMII_0_600_NS 4
210 #define YT8521_RC1R_RGMII_0_750_NS 5
211 #define YT8521_RC1R_RGMII_0_900_NS 6
212 #define YT8521_RC1R_RGMII_1_050_NS 7
213 #define YT8521_RC1R_RGMII_1_200_NS 8
214 #define YT8521_RC1R_RGMII_1_350_NS 9
215 #define YT8521_RC1R_RGMII_1_500_NS 10
216 #define YT8521_RC1R_RGMII_1_650_NS 11
217 #define YT8521_RC1R_RGMII_1_800_NS 12
218 #define YT8521_RC1R_RGMII_1_950_NS 13
219 #define YT8521_RC1R_RGMII_2_100_NS 14
220 #define YT8521_RC1R_RGMII_2_250_NS 15
222 #define YTPHY_MISC_CONFIG_REG 0xA006
223 #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0)
224 #define YTPHY_MCR_FIBER_1000BX (0x1 << 0)
225 #define YTPHY_MCR_FIBER_100FX (0x0 << 0)
227 /* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */
228 #define YTPHY_WOL_MACADDR2_REG 0xA007
229 #define YTPHY_WOL_MACADDR1_REG 0xA008
230 #define YTPHY_WOL_MACADDR0_REG 0xA009
232 #define YTPHY_WOL_CONFIG_REG 0xA00A
233 #define YTPHY_WCR_INTR_SEL BIT(6)
234 #define YTPHY_WCR_ENABLE BIT(3)
237 * 2b01 168ms *default*
241 #define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1))
242 #define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1))
244 /* 1b0 Interrupt and WOL events is level triggered and active LOW *default*
245 * 1b1 Interrupt and WOL events is pulse triggered and active LOW
247 #define YTPHY_WCR_TYPE_PULSE BIT(0)
249 #define YTPHY_SYNCE_CFG_REG 0xA012
250 #define YT8521_SCR_SYNCE_ENABLE BIT(5)
251 /* 1b0 output 25m clock
252 * 1b1 output 125m clock *default*
254 #define YT8521_SCR_CLK_FRE_SEL_125M BIT(3)
255 #define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1)
256 #define YT8521_SCR_CLK_SRC_PLL_125M 0
257 #define YT8521_SCR_CLK_SRC_UTP_RX 1
258 #define YT8521_SCR_CLK_SRC_SDS_RX 2
259 #define YT8521_SCR_CLK_SRC_REF_25M 3
260 #define YT8531_SCR_SYNCE_ENABLE BIT(6)
261 /* 1b0 output 25m clock *default*
262 * 1b1 output 125m clock
264 #define YT8531_SCR_CLK_FRE_SEL_125M BIT(4)
265 #define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1)
266 #define YT8531_SCR_CLK_SRC_PLL_125M 0
267 #define YT8531_SCR_CLK_SRC_UTP_RX 1
268 #define YT8531_SCR_CLK_SRC_SDS_RX 2
269 #define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3
270 #define YT8531_SCR_CLK_SRC_REF_25M 4
271 #define YT8531_SCR_CLK_SRC_SSC_25M 5
272 #define YT8531S_SYNCE_CFG_REG 0xA012
273 #define YT8531S_SCR_SYNCE_ENABLE BIT(6)
275 /* Extended Register end */
278 /* combo_advertising is used for case of YT8521 in combo mode,
279 * this means that yt8521 may work in utp or fiber mode which depends
280 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED).
282 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising);
284 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/
286 u8 strap_mode; /* 8 working modes */
287 /* current reg page of yt8521 phy:
288 * YT8521_RSSR_UTP_SPACE
289 * YT8521_RSSR_FIBER_SPACE
290 * YT8521_RSSR_TO_BE_ARBITRATED
296 * ytphy_read_ext() - read a PHY's extended register
297 * @phydev: a pointer to a &struct phy_device
298 * @regnum: register number to read
300 * NOTE:The caller must have taken the MDIO bus lock.
302 * returns the value of regnum reg or negative error code
304 static int ytphy_read_ext(struct phy_device *phydev, u16 regnum)
308 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
312 return __phy_read(phydev, YTPHY_PAGE_DATA);
316 * ytphy_read_ext_with_lock() - read a PHY's extended register
317 * @phydev: a pointer to a &struct phy_device
318 * @regnum: register number to read
320 * returns the value of regnum reg or negative error code
322 static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum)
326 phy_lock_mdio_bus(phydev);
327 ret = ytphy_read_ext(phydev, regnum);
328 phy_unlock_mdio_bus(phydev);
334 * ytphy_write_ext() - write a PHY's extended register
335 * @phydev: a pointer to a &struct phy_device
336 * @regnum: register number to write
337 * @val: value to write to @regnum
339 * NOTE:The caller must have taken the MDIO bus lock.
341 * returns 0 or negative error code
343 static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val)
347 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
351 return __phy_write(phydev, YTPHY_PAGE_DATA, val);
355 * ytphy_write_ext_with_lock() - write a PHY's extended register
356 * @phydev: a pointer to a &struct phy_device
357 * @regnum: register number to write
358 * @val: value to write to @regnum
360 * returns 0 or negative error code
362 static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum,
367 phy_lock_mdio_bus(phydev);
368 ret = ytphy_write_ext(phydev, regnum, val);
369 phy_unlock_mdio_bus(phydev);
375 * ytphy_modify_ext() - bits modify a PHY's extended register
376 * @phydev: a pointer to a &struct phy_device
377 * @regnum: register number to write
378 * @mask: bit mask of bits to clear
379 * @set: bit mask of bits to set
381 * NOTE: Convenience function which allows a PHY's extended register to be
382 * modified as new register value = (old register value & ~mask) | set.
383 * The caller must have taken the MDIO bus lock.
385 * returns 0 or negative error code
387 static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
392 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
396 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set);
400 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register
401 * @phydev: a pointer to a &struct phy_device
402 * @regnum: register number to write
403 * @mask: bit mask of bits to clear
404 * @set: bit mask of bits to set
406 * NOTE: Convenience function which allows a PHY's extended register to be
407 * modified as new register value = (old register value & ~mask) | set.
409 * returns 0 or negative error code
411 static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum,
416 phy_lock_mdio_bus(phydev);
417 ret = ytphy_modify_ext(phydev, regnum, mask, set);
418 phy_unlock_mdio_bus(phydev);
424 * ytphy_get_wol() - report whether wake-on-lan is enabled
425 * @phydev: a pointer to a &struct phy_device
426 * @wol: a pointer to a &struct ethtool_wolinfo
428 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg.
430 static void ytphy_get_wol(struct phy_device *phydev,
431 struct ethtool_wolinfo *wol)
435 wol->supported = WAKE_MAGIC;
438 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
442 if (wol_config & YTPHY_WCR_ENABLE)
443 wol->wolopts |= WAKE_MAGIC;
447 * ytphy_set_wol() - turn wake-on-lan on or off
448 * @phydev: a pointer to a &struct phy_device
449 * @wol: a pointer to a &struct ethtool_wolinfo
451 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG
452 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The
453 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register.
455 * returns 0 or negative errno code
457 static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
459 struct net_device *p_attached_dev;
460 const u16 mac_addr_reg[] = {
461 YTPHY_WOL_MACADDR2_REG,
462 YTPHY_WOL_MACADDR1_REG,
463 YTPHY_WOL_MACADDR0_REG,
472 if (wol->wolopts & WAKE_MAGIC) {
473 p_attached_dev = phydev->attached_dev;
477 mac_addr = (const u8 *)p_attached_dev->dev_addr;
478 if (!is_valid_ether_addr(mac_addr))
481 /* lock mdio bus then switch to utp reg space */
482 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
484 goto err_restore_page;
486 /* Store the device address for the magic packet */
487 for (i = 0; i < 3; i++) {
488 ret = ytphy_write_ext(phydev, mac_addr_reg[i],
489 ((mac_addr[i * 2] << 8)) |
490 (mac_addr[i * 2 + 1]));
492 goto err_restore_page;
495 /* Enable WOL feature */
496 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
497 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
498 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
499 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val);
501 goto err_restore_page;
503 /* Enable WOL interrupt */
504 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
507 goto err_restore_page;
510 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
512 goto err_restore_page;
514 /* Disable WOL feature */
515 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
516 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0);
518 /* Disable WOL interrupt */
519 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
522 goto err_restore_page;
526 return phy_restore_page(phydev, old_page, ret);
529 static int yt8511_read_page(struct phy_device *phydev)
531 return __phy_read(phydev, YT8511_PAGE_SELECT);
534 static int yt8511_write_page(struct phy_device *phydev, int page)
536 return __phy_write(phydev, YT8511_PAGE_SELECT, page);
539 static int yt8511_config_init(struct phy_device *phydev)
541 int oldpage, ret = 0;
544 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
546 goto err_restore_page;
548 /* set rgmii delay mode */
549 switch (phydev->interface) {
550 case PHY_INTERFACE_MODE_RGMII:
551 ge = YT8511_DELAY_GE_TX_DIS;
552 fe = YT8511_DELAY_FE_TX_DIS;
554 case PHY_INTERFACE_MODE_RGMII_RXID:
555 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
556 fe = YT8511_DELAY_FE_TX_DIS;
558 case PHY_INTERFACE_MODE_RGMII_TXID:
559 ge = YT8511_DELAY_GE_TX_EN;
560 fe = YT8511_DELAY_FE_TX_EN;
562 case PHY_INTERFACE_MODE_RGMII_ID:
563 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
564 fe = YT8511_DELAY_FE_TX_EN;
566 default: /* do not support other modes */
568 goto err_restore_page;
571 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
573 goto err_restore_page;
575 /* set clock mode to 125mhz */
576 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
578 goto err_restore_page;
580 /* fast ethernet delay is in a separate page */
581 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
583 goto err_restore_page;
585 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
587 goto err_restore_page;
589 /* leave pll enabled in sleep */
590 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
592 goto err_restore_page;
594 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
596 goto err_restore_page;
599 return phy_restore_page(phydev, oldpage, ret);
603 * yt8521_read_page() - read reg page
604 * @phydev: a pointer to a &struct phy_device
606 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/
607 * YT8521_RSSR_UTP_SPACE) or negative errno code
609 static int yt8521_read_page(struct phy_device *phydev)
613 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG);
617 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
618 return YT8521_RSSR_FIBER_SPACE;
620 return YT8521_RSSR_UTP_SPACE;
624 * yt8521_write_page() - write reg page
625 * @phydev: a pointer to a &struct phy_device
626 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write.
628 * returns 0 or negative errno code
630 static int yt8521_write_page(struct phy_device *phydev, int page)
632 int mask = YT8521_RSSR_SPACE_MASK;
635 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
636 set = YT8521_RSSR_FIBER_SPACE;
638 set = YT8521_RSSR_UTP_SPACE;
640 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set);
644 * yt8521_probe() - read chip config then set suitable polling_mode
645 * @phydev: a pointer to a &struct phy_device
647 * returns 0 or negative errno code
649 static int yt8521_probe(struct phy_device *phydev)
651 struct device *dev = &phydev->mdio.dev;
652 struct yt8521_priv *priv;
656 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
662 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
666 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK;
667 switch (priv->strap_mode) {
668 case YT8521_CCR_MODE_FIBER_TO_RGMII:
669 case YT8521_CCR_MODE_SGPHY_TO_RGMAC:
670 case YT8521_CCR_MODE_SGMAC_TO_RGPHY:
671 priv->polling_mode = YT8521_MODE_FIBER;
672 priv->reg_page = YT8521_RSSR_FIBER_SPACE;
673 phydev->port = PORT_FIBRE;
675 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII:
676 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO:
677 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE:
678 priv->polling_mode = YT8521_MODE_POLL;
679 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
680 phydev->port = PORT_NONE;
682 case YT8521_CCR_MODE_UTP_TO_SGMII:
683 case YT8521_CCR_MODE_UTP_TO_RGMII:
684 priv->polling_mode = YT8521_MODE_UTP;
685 priv->reg_page = YT8521_RSSR_UTP_SPACE;
686 phydev->port = PORT_TP;
689 /* set default reg space */
690 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
691 ret = ytphy_write_ext_with_lock(phydev,
692 YT8521_REG_SPACE_SELECT_REG,
702 * yt8531s_probe() - read chip config then set suitable polling_mode
703 * @phydev: a pointer to a &struct phy_device
705 * returns 0 or negative errno code
707 static int yt8531s_probe(struct phy_device *phydev)
711 /* Disable SyncE clock output by default */
712 ret = ytphy_modify_ext_with_lock(phydev, YT8531S_SYNCE_CFG_REG,
713 YT8531S_SCR_SYNCE_ENABLE, 0);
717 /* same as yt8521_probe */
718 return yt8521_probe(phydev);
722 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
723 * @phydev: a pointer to a &struct phy_device
725 * NOTE:The caller must have taken the MDIO bus lock.
727 * returns 0 or negative errno code
729 static int ytphy_utp_read_lpa(struct phy_device *phydev)
733 if (phydev->autoneg == AUTONEG_ENABLE) {
734 if (!phydev->autoneg_complete) {
735 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
737 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
741 if (phydev->is_gigabit_capable) {
742 lpagb = __phy_read(phydev, MII_STAT1000);
746 if (lpagb & LPA_1000MSFAIL) {
747 int adv = __phy_read(phydev, MII_CTRL1000);
752 if (adv & CTL1000_ENABLE_MASTER)
753 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
755 phydev_err(phydev, "Master/Slave resolution failed\n");
759 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
763 lpa = __phy_read(phydev, MII_LPA);
767 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
769 linkmode_zero(phydev->lp_advertising);
776 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber
777 * mode, adjust speed and duplex.
778 * @phydev: a pointer to a &struct phy_device
779 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG
780 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode)
782 * NOTE:The caller must have taken the MDIO bus lock.
786 static int yt8521_adjust_status(struct phy_device *phydev, int status,
789 int speed_mode, duplex;
795 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET;
797 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */
799 speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >>
800 YTPHY_SSR_SPEED_MODE_OFFSET;
802 switch (speed_mode) {
803 case YTPHY_SSR_SPEED_10M:
807 /* for fiber, it will never run here, default to
810 speed = SPEED_UNKNOWN;
812 case YTPHY_SSR_SPEED_100M:
815 case YTPHY_SSR_SPEED_1000M:
819 speed = SPEED_UNKNOWN;
823 phydev->speed = speed;
824 phydev->duplex = duplex;
827 err = ytphy_utp_read_lpa(phydev);
831 phy_resolve_aneg_pause(phydev);
833 lpa = __phy_read(phydev, MII_LPA);
837 /* only support 1000baseX Full */
838 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
839 phydev->lp_advertising, lpa & LPA_1000XFULL);
841 if (!(lpa & YTPHY_FLPA_PAUSE)) {
843 phydev->asym_pause = 0;
844 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) {
846 phydev->asym_pause = 1;
849 phydev->asym_pause = 0;
857 * yt8521_read_status_paged() - determines the speed and duplex of one page
858 * @phydev: a pointer to a &struct phy_device
859 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
862 * returns 1 (utp or fiber link),0 (no link) or negative errno code
864 static int yt8521_read_status_paged(struct phy_device *phydev, int page)
873 linkmode_zero(phydev->lp_advertising);
874 phydev->duplex = DUPLEX_UNKNOWN;
875 phydev->speed = SPEED_UNKNOWN;
876 phydev->asym_pause = 0;
879 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber
880 * respectively. but for utp/fiber combo mode, reg space should be
881 * arbitrated based on media priority. by default, utp takes
882 * priority. reg space should be properly set before read
883 * YTPHY_SPECIFIC_STATUS_REG.
886 page &= YT8521_RSSR_SPACE_MASK;
887 old_page = phy_select_page(phydev, page);
889 goto err_restore_page;
891 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex
892 * of the PHY is actually using.
894 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
896 goto err_restore_page;
899 link = !!(status & YTPHY_SSR_LINK);
901 /* When PHY is in fiber mode, speed transferred from 1000Mbps to
902 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so
903 * we need check MII_BMSR to identify such case.
905 if (page == YT8521_RSSR_FIBER_SPACE) {
906 ret = __phy_read(phydev, MII_BMSR);
908 goto err_restore_page;
910 fiber_latch_val = ret;
911 ret = __phy_read(phydev, MII_BMSR);
913 goto err_restore_page;
915 fiber_curr_val = ret;
916 if (link && fiber_latch_val != fiber_curr_val) {
919 "%s, fiber link down detect, latch = %04x, curr = %04x\n",
920 __func__, fiber_latch_val, fiber_curr_val);
923 /* Read autonegotiation status */
924 ret = __phy_read(phydev, MII_BMSR);
926 goto err_restore_page;
928 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0;
932 if (page == YT8521_RSSR_UTP_SPACE)
933 yt8521_adjust_status(phydev, status, true);
935 yt8521_adjust_status(phydev, status, false);
937 return phy_restore_page(phydev, old_page, link);
940 return phy_restore_page(phydev, old_page, ret);
944 * yt8521_read_status() - determines the negotiated speed and duplex
945 * @phydev: a pointer to a &struct phy_device
947 * returns 0 or negative errno code
949 static int yt8521_read_status(struct phy_device *phydev)
951 struct yt8521_priv *priv = phydev->priv;
957 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
958 link = yt8521_read_status_paged(phydev, priv->reg_page);
962 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is
963 * needed. by default, utp is higher priority.
966 link_utp = yt8521_read_status_paged(phydev,
967 YT8521_RSSR_UTP_SPACE);
972 link_fiber = yt8521_read_status_paged(phydev,
973 YT8521_RSSR_FIBER_SPACE);
978 link = link_utp || link_fiber;
982 if (phydev->link == 0) {
983 /* arbitrate reg space based on linkup media type. */
984 if (priv->polling_mode == YT8521_MODE_POLL &&
985 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
988 YT8521_RSSR_FIBER_SPACE;
990 priv->reg_page = YT8521_RSSR_UTP_SPACE;
992 ret = ytphy_write_ext_with_lock(phydev,
993 YT8521_REG_SPACE_SELECT_REG,
998 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP;
1000 phydev_info(phydev, "%s, link up, media: %s\n",
1002 (phydev->port == PORT_TP) ?
1008 if (phydev->link == 1) {
1009 phydev_info(phydev, "%s, link down, media: %s\n",
1010 __func__, (phydev->port == PORT_TP) ?
1013 /* When in YT8521_MODE_POLL mode, need prepare for next
1016 if (priv->polling_mode == YT8521_MODE_POLL) {
1017 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
1018 phydev->port = PORT_NONE;
1029 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page
1030 * @phydev: the phy_device struct
1031 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate
1032 * @mask: bit mask of bits to clear
1033 * @set: bit mask of bits to set
1035 * NOTE: Convenience function which allows a PHY's BMCR register to be
1036 * modified as new register value = (old register value & ~mask) | set.
1037 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1038 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1039 * If it is reset, it will wait for completion.
1041 * returns 0 or negative errno code
1043 static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page,
1046 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */
1050 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
1052 goto err_restore_page;
1054 ret = __phy_modify(phydev, MII_BMCR, mask, set);
1056 goto err_restore_page;
1058 /* If it is reset, need to wait for the reset to complete */
1059 if (set == BMCR_RESET) {
1061 usleep_range(1000, 1100);
1062 ret = __phy_read(phydev, MII_BMCR);
1064 goto err_restore_page;
1066 if (!(ret & BMCR_RESET))
1067 return phy_restore_page(phydev, old_page, 0);
1072 return phy_restore_page(phydev, old_page, ret);
1076 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register
1077 * @phydev: the phy_device struct
1078 * @mask: bit mask of bits to clear
1079 * @set: bit mask of bits to set
1081 * NOTE: Convenience function which allows a PHY's BMCR register to be
1082 * modified as new register value = (old register value & ~mask) | set.
1083 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1084 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1086 * returns 0 or negative errno code
1088 static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask,
1091 struct yt8521_priv *priv = phydev->priv;
1094 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1095 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask,
1100 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE,
1105 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE,
1114 * yt8521_soft_reset() - called to issue a PHY software reset
1115 * @phydev: a pointer to a &struct phy_device
1117 * returns 0 or negative errno code
1119 static int yt8521_soft_reset(struct phy_device *phydev)
1121 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET);
1125 * yt8521_suspend() - suspend the hardware
1126 * @phydev: a pointer to a &struct phy_device
1128 * returns 0 or negative errno code
1130 static int yt8521_suspend(struct phy_device *phydev)
1134 /* YTPHY_WOL_CONFIG_REG is common ext reg */
1135 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1139 /* if wol enable, do nothing */
1140 if (wol_config & YTPHY_WCR_ENABLE)
1143 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN);
1147 * yt8521_resume() - resume the hardware
1148 * @phydev: a pointer to a &struct phy_device
1150 * returns 0 or negative errno code
1152 static int yt8521_resume(struct phy_device *phydev)
1157 /* disable auto sleep */
1158 ret = ytphy_modify_ext_with_lock(phydev,
1159 YT8521_EXTREG_SLEEP_CONTROL1_REG,
1160 YT8521_ESC1R_SLEEP_SW, 0);
1164 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1168 /* if wol enable, do nothing */
1169 if (wol_config & YTPHY_WCR_ENABLE)
1172 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0);
1176 * yt8521_config_init() - called to initialize the PHY
1177 * @phydev: a pointer to a &struct phy_device
1179 * returns 0 or negative errno code
1181 static int yt8521_config_init(struct phy_device *phydev)
1187 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
1189 goto err_restore_page;
1191 switch (phydev->interface) {
1192 case PHY_INTERFACE_MODE_RGMII:
1193 val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS;
1194 val |= YT8521_RC1R_RX_DELAY_DIS;
1196 case PHY_INTERFACE_MODE_RGMII_RXID:
1197 val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS;
1198 val |= YT8521_RC1R_RX_DELAY_EN;
1200 case PHY_INTERFACE_MODE_RGMII_TXID:
1201 val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN;
1202 val |= YT8521_RC1R_RX_DELAY_DIS;
1204 case PHY_INTERFACE_MODE_RGMII_ID:
1205 val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN;
1206 val |= YT8521_RC1R_RX_DELAY_EN;
1208 case PHY_INTERFACE_MODE_SGMII:
1210 default: /* do not support other modes */
1212 goto err_restore_page;
1215 /* set rgmii delay mode */
1216 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1217 ret = ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG,
1218 (YT8521_RC1R_RX_DELAY_MASK |
1219 YT8521_RC1R_FE_TX_DELAY_MASK |
1220 YT8521_RC1R_GE_TX_DELAY_MASK),
1223 goto err_restore_page;
1226 /* disable auto sleep */
1227 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
1228 YT8521_ESC1R_SLEEP_SW, 0);
1230 goto err_restore_page;
1232 /* enable RXC clock when no wire plug */
1233 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
1234 YT8521_CGR_RX_CLK_EN, 0);
1236 goto err_restore_page;
1239 return phy_restore_page(phydev, old_page, ret);
1243 * yt8521_prepare_fiber_features() - A small helper function that setup
1245 * @phydev: a pointer to a &struct phy_device
1246 * @dst: a pointer to store fiber's features
1248 static void yt8521_prepare_fiber_features(struct phy_device *phydev,
1251 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst);
1252 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst);
1253 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst);
1254 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst);
1258 * yt8521_fiber_setup_forced - configures/forces speed from @phydev
1259 * @phydev: target phy_device struct
1261 * NOTE:The caller must have taken the MDIO bus lock.
1263 * returns 0 or negative errno code
1265 static int yt8521_fiber_setup_forced(struct phy_device *phydev)
1270 if (phydev->speed == SPEED_1000)
1271 val = YTPHY_MCR_FIBER_1000BX;
1272 else if (phydev->speed == SPEED_100)
1273 val = YTPHY_MCR_FIBER_100FX;
1277 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1281 /* disable Fiber auto sensing */
1282 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1283 YT8521_LTCR_EN_AUTOSEN, 0);
1287 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG,
1288 YTPHY_MCR_FIBER_SPEED_MASK, val);
1292 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1293 YT8521_CCR_SW_RST, 0);
1297 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation
1298 * @phydev: target phy_device struct
1299 * @restart: whether aneg restart is requested
1301 * NOTE:The caller must have taken the MDIO bus lock.
1303 * returns 0 or negative errno code
1305 static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
1310 /* Advertisement hasn't changed, but maybe aneg was never on to
1311 * begin with? Or maybe phy was isolated?
1313 ret = __phy_read(phydev, MII_BMCR);
1317 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
1320 /* Enable and Restart Autonegotiation
1321 * Don't isolate the PHY if we're negotiating
1324 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
1325 BMCR_ANENABLE | BMCR_ANRESTART);
1331 * yt8521_fiber_config_aneg - restart auto-negotiation or write
1332 * YTPHY_MISC_CONFIG_REG.
1333 * @phydev: target phy_device struct
1335 * NOTE:The caller must have taken the MDIO bus lock.
1337 * returns 0 or negative errno code
1339 static int yt8521_fiber_config_aneg(struct phy_device *phydev)
1341 int err, changed = 0;
1345 if (phydev->autoneg != AUTONEG_ENABLE)
1346 return yt8521_fiber_setup_forced(phydev);
1348 /* enable Fiber auto sensing */
1349 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1350 0, YT8521_LTCR_EN_AUTOSEN);
1354 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1355 YT8521_CCR_SW_RST, 0);
1359 bmcr = __phy_read(phydev, MII_BMCR);
1363 /* When it is coming from fiber forced mode, add bmcr power down
1364 * and power up to let aneg work fine.
1366 if (!(bmcr & BMCR_ANENABLE)) {
1367 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
1368 usleep_range(1000, 1100);
1369 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
1372 adv = linkmode_adv_to_mii_adv_x(phydev->advertising,
1373 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
1375 /* Setup fiber advertisement */
1376 err = __phy_modify_changed(phydev, MII_ADVERTISE,
1377 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
1378 ADVERTISE_1000XPAUSE |
1379 ADVERTISE_1000XPSE_ASYM,
1387 return ytphy_check_and_restart_aneg(phydev, changed);
1391 * ytphy_setup_master_slave
1392 * @phydev: target phy_device struct
1394 * NOTE: The caller must have taken the MDIO bus lock.
1396 * returns 0 or negative errno code
1398 static int ytphy_setup_master_slave(struct phy_device *phydev)
1402 if (!phydev->is_gigabit_capable)
1405 switch (phydev->master_slave_set) {
1406 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
1407 ctl |= CTL1000_PREFER_MASTER;
1409 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
1411 case MASTER_SLAVE_CFG_MASTER_FORCE:
1412 ctl |= CTL1000_AS_MASTER;
1414 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1415 ctl |= CTL1000_ENABLE_MASTER;
1417 case MASTER_SLAVE_CFG_UNKNOWN:
1418 case MASTER_SLAVE_CFG_UNSUPPORTED:
1421 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1425 return __phy_modify_changed(phydev, MII_CTRL1000,
1426 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
1427 CTL1000_PREFER_MASTER), ctl);
1431 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters
1432 * @phydev: target phy_device struct
1434 * NOTE: Writes MII_ADVERTISE with the appropriate values,
1435 * after sanitizing the values to make sure we only advertise
1436 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
1437 * hasn't changed, and > 0 if it has changed.
1438 * The caller must have taken the MDIO bus lock.
1440 * returns 0 or negative errno code
1442 static int ytphy_utp_config_advert(struct phy_device *phydev)
1444 int err, bmsr, changed = 0;
1447 /* Only allow advertising what this PHY supports */
1448 linkmode_and(phydev->advertising, phydev->advertising,
1451 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
1453 /* Setup standard advertisement */
1454 err = __phy_modify_changed(phydev, MII_ADVERTISE,
1455 ADVERTISE_ALL | ADVERTISE_100BASE4 |
1456 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
1463 bmsr = __phy_read(phydev, MII_BMSR);
1467 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
1468 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
1471 if (!(bmsr & BMSR_ESTATEN))
1474 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1476 err = __phy_modify_changed(phydev, MII_CTRL1000,
1477 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
1488 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR
1489 * @phydev: target phy_device struct
1490 * @changed: whether autoneg is requested
1492 * NOTE: If auto-negotiation is enabled, we configure the
1493 * advertising, and then restart auto-negotiation. If it is not
1494 * enabled, then we write the BMCR.
1495 * The caller must have taken the MDIO bus lock.
1497 * returns 0 or negative errno code
1499 static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed)
1504 err = ytphy_setup_master_slave(phydev);
1510 if (phydev->autoneg != AUTONEG_ENABLE) {
1511 /* configures/forces speed/duplex from @phydev */
1513 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
1515 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK |
1516 BMCR_ISOLATE | BMCR_PDOWN), ctl);
1519 err = ytphy_utp_config_advert(phydev);
1520 if (err < 0) /* error */
1525 return ytphy_check_and_restart_aneg(phydev, changed);
1529 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg
1531 * @phydev: a pointer to a &struct phy_device
1532 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1535 * returns 0 or negative errno code
1537 static int yt8521_config_aneg_paged(struct phy_device *phydev, int page)
1539 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported);
1540 struct yt8521_priv *priv = phydev->priv;
1544 page &= YT8521_RSSR_SPACE_MASK;
1546 old_page = phy_select_page(phydev, page);
1548 goto err_restore_page;
1550 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
1551 * phydev->advertising should be updated.
1553 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
1554 linkmode_zero(fiber_supported);
1555 yt8521_prepare_fiber_features(phydev, fiber_supported);
1557 /* prepare fiber_supported, then setup advertising. */
1558 if (page == YT8521_RSSR_FIBER_SPACE) {
1559 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
1561 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
1563 linkmode_and(phydev->advertising,
1564 priv->combo_advertising, fiber_supported);
1566 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */
1567 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1569 linkmode_andnot(phydev->advertising,
1570 priv->combo_advertising,
1575 if (page == YT8521_RSSR_FIBER_SPACE)
1576 ret = yt8521_fiber_config_aneg(phydev);
1578 ret = ytphy_utp_config_aneg(phydev, false);
1581 return phy_restore_page(phydev, old_page, ret);
1585 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged
1586 * @phydev: a pointer to a &struct phy_device
1588 * returns 0 or negative errno code
1590 static int yt8521_config_aneg(struct phy_device *phydev)
1592 struct yt8521_priv *priv = phydev->priv;
1595 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1596 ret = yt8521_config_aneg_paged(phydev, priv->reg_page);
1600 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
1601 * phydev->advertising need to be saved at first run.
1602 * Because it contains the advertising which supported by both
1603 * mac and yt8521(utp and fiber).
1605 if (linkmode_empty(priv->combo_advertising)) {
1606 linkmode_copy(priv->combo_advertising,
1607 phydev->advertising);
1610 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE);
1614 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE);
1618 /* we don't known which will be link, so restore
1619 * phydev->advertising as default value.
1621 linkmode_copy(phydev->advertising, priv->combo_advertising);
1627 * yt8521_aneg_done_paged() - determines the auto negotiation result of one
1629 * @phydev: a pointer to a &struct phy_device
1630 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1633 * returns 0(no link)or 1(fiber or utp link) or negative errno code
1635 static int yt8521_aneg_done_paged(struct phy_device *phydev, int page)
1641 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
1643 goto err_restore_page;
1645 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
1647 goto err_restore_page;
1649 link = !!(ret & YTPHY_SSR_LINK);
1653 return phy_restore_page(phydev, old_page, ret);
1657 * yt8521_aneg_done() - determines the auto negotiation result
1658 * @phydev: a pointer to a &struct phy_device
1660 * returns 0(no link)or 1(fiber or utp link) or negative errno code
1662 static int yt8521_aneg_done(struct phy_device *phydev)
1664 struct yt8521_priv *priv = phydev->priv;
1669 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1670 link = yt8521_aneg_done_paged(phydev, priv->reg_page);
1672 link_utp = yt8521_aneg_done_paged(phydev,
1673 YT8521_RSSR_UTP_SPACE);
1678 link_fiber = yt8521_aneg_done_paged(phydev,
1679 YT8521_RSSR_FIBER_SPACE);
1683 link = link_fiber || link_utp;
1684 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n",
1685 __func__, link_fiber, link_utp);
1692 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers
1693 * @phydev: target phy_device struct
1695 * NOTE: Reads the PHY's abilities and populates
1696 * phydev->supported accordingly.
1697 * The caller must have taken the MDIO bus lock.
1699 * returns 0 or negative errno code
1701 static int ytphy_utp_read_abilities(struct phy_device *phydev)
1705 linkmode_set_bit_array(phy_basic_ports_array,
1706 ARRAY_SIZE(phy_basic_ports_array),
1709 val = __phy_read(phydev, MII_BMSR);
1713 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
1714 val & BMSR_ANEGCAPABLE);
1716 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
1717 val & BMSR_100FULL);
1718 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
1719 val & BMSR_100HALF);
1720 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
1722 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
1725 if (val & BMSR_ESTATEN) {
1726 val = __phy_read(phydev, MII_ESTATUS);
1730 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1731 phydev->supported, val & ESTATUS_1000_TFULL);
1732 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1733 phydev->supported, val & ESTATUS_1000_THALF);
1734 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1735 phydev->supported, val & ESTATUS_1000_XFULL);
1742 * yt8521_get_features_paged() - read supported link modes for one page
1743 * @phydev: a pointer to a &struct phy_device
1744 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1747 * returns 0 or negative errno code
1749 static int yt8521_get_features_paged(struct phy_device *phydev, int page)
1754 page &= YT8521_RSSR_SPACE_MASK;
1755 old_page = phy_select_page(phydev, page);
1757 goto err_restore_page;
1759 if (page == YT8521_RSSR_FIBER_SPACE) {
1760 linkmode_zero(phydev->supported);
1761 yt8521_prepare_fiber_features(phydev, phydev->supported);
1763 ret = ytphy_utp_read_abilities(phydev);
1765 goto err_restore_page;
1769 return phy_restore_page(phydev, old_page, ret);
1773 * yt8521_get_features - switch reg space then call yt8521_get_features_paged
1774 * @phydev: target phy_device struct
1776 * returns 0 or negative errno code
1778 static int yt8521_get_features(struct phy_device *phydev)
1780 struct yt8521_priv *priv = phydev->priv;
1783 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1784 ret = yt8521_get_features_paged(phydev, priv->reg_page);
1786 ret = yt8521_get_features_paged(phydev,
1787 YT8521_RSSR_UTP_SPACE);
1791 /* add fiber's features to phydev->supported */
1792 yt8521_prepare_fiber_features(phydev, phydev->supported);
1797 static struct phy_driver motorcomm_phy_drvs[] = {
1799 PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
1800 .name = "YT8511 Gigabit Ethernet",
1801 .config_init = yt8511_config_init,
1802 .suspend = genphy_suspend,
1803 .resume = genphy_resume,
1804 .read_page = yt8511_read_page,
1805 .write_page = yt8511_write_page,
1808 PHY_ID_MATCH_EXACT(PHY_ID_YT8521),
1809 .name = "YT8521 Gigabit Ethernet",
1810 .get_features = yt8521_get_features,
1811 .probe = yt8521_probe,
1812 .read_page = yt8521_read_page,
1813 .write_page = yt8521_write_page,
1814 .get_wol = ytphy_get_wol,
1815 .set_wol = ytphy_set_wol,
1816 .config_aneg = yt8521_config_aneg,
1817 .aneg_done = yt8521_aneg_done,
1818 .config_init = yt8521_config_init,
1819 .read_status = yt8521_read_status,
1820 .soft_reset = yt8521_soft_reset,
1821 .suspend = yt8521_suspend,
1822 .resume = yt8521_resume,
1825 PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
1826 .name = "YT8531S Gigabit Ethernet",
1827 .get_features = yt8521_get_features,
1828 .probe = yt8531s_probe,
1829 .read_page = yt8521_read_page,
1830 .write_page = yt8521_write_page,
1831 .get_wol = ytphy_get_wol,
1832 .set_wol = ytphy_set_wol,
1833 .config_aneg = yt8521_config_aneg,
1834 .aneg_done = yt8521_aneg_done,
1835 .config_init = yt8521_config_init,
1836 .read_status = yt8521_read_status,
1837 .soft_reset = yt8521_soft_reset,
1838 .suspend = yt8521_suspend,
1839 .resume = yt8521_resume,
1843 module_phy_driver(motorcomm_phy_drvs);
1845 MODULE_DESCRIPTION("Motorcomm 8511/8521/8531S PHY driver");
1846 MODULE_AUTHOR("Peter Geis");
1847 MODULE_AUTHOR("Frank");
1848 MODULE_LICENSE("GPL");
1850 static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
1851 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
1852 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
1853 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
1857 MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);