drivers/net/phy/motorcomm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Motorcomm 8511/8521/8531/8531S PHY driver.
   4  *
   5  * Author: Peter Geis <pgwipeout@gmail.com>
   6  * Author: Frank <Frank.Sae@motor-comm.com>
   7  */
   8
   9 #include <linux/etherdevice.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/phy.h>
  13 #include <linux/of.h>
  14
  15 #define PHY_ID_YT8511           0x0000010a
  16 #define PHY_ID_YT8521           0x0000011a
  17 #define PHY_ID_YT8531           0x4f51e91b
  18 #define PHY_ID_YT8531S          0x4f51e91a
  19
  20 /* YT8521/YT8531S Register Overview
  21  *      UTP Register space      |       FIBER Register space
  22  *  ------------------------------------------------------------
  23  * |    UTP MII                 |       FIBER MII               |
  24  * |    UTP MMD                 |                               |
  25  * |    UTP Extended            |       FIBER Extended          |
  26  *  ------------------------------------------------------------
  27  * |                    Common Extended                         |
  28  *  ------------------------------------------------------------
  29  */
  30
  31 /* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */
  32
  33 /* Specific Function Control Register */
  34 #define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG     0x10
  35
  36 /* 2b00 Manual MDI configuration
  37  * 2b01 Manual MDIX configuration
  38  * 2b10 Reserved
  39  * 2b11 Enable automatic crossover for all modes  *default*
  40  */
  41 #define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK      (BIT(6) | BIT(5))
  42 #define YTPHY_SFCR_CROSSOVER_EN                 BIT(3)
  43 #define YTPHY_SFCR_SQE_TEST_EN                  BIT(2)
  44 #define YTPHY_SFCR_POLARITY_REVERSAL_EN         BIT(1)
  45 #define YTPHY_SFCR_JABBER_DIS                   BIT(0)
  46
  47 /* Specific Status Register */
  48 #define YTPHY_SPECIFIC_STATUS_REG               0x11
  49 #define YTPHY_SSR_SPEED_MODE_OFFSET             14
  50
  51 #define YTPHY_SSR_SPEED_MODE_MASK               (BIT(15) | BIT(14))
  52 #define YTPHY_SSR_SPEED_10M                     0x0
  53 #define YTPHY_SSR_SPEED_100M                    0x1
  54 #define YTPHY_SSR_SPEED_1000M                   0x2
  55 #define YTPHY_SSR_DUPLEX_OFFSET                 13
  56 #define YTPHY_SSR_DUPLEX                        BIT(13)
  57 #define YTPHY_SSR_PAGE_RECEIVED                 BIT(12)
  58 #define YTPHY_SSR_SPEED_DUPLEX_RESOLVED         BIT(11)
  59 #define YTPHY_SSR_LINK                          BIT(10)
  60 #define YTPHY_SSR_MDIX_CROSSOVER                BIT(6)
  61 #define YTPHY_SSR_DOWNGRADE                     BIT(5)
  62 #define YTPHY_SSR_TRANSMIT_PAUSE                BIT(3)
  63 #define YTPHY_SSR_RECEIVE_PAUSE                 BIT(2)
  64 #define YTPHY_SSR_POLARITY                      BIT(1)
  65 #define YTPHY_SSR_JABBER                        BIT(0)
  66
  67 /* Interrupt enable Register */
  68 #define YTPHY_INTERRUPT_ENABLE_REG              0x12
  69 #define YTPHY_IER_WOL                           BIT(6)
  70
  71 /* Interrupt Status Register */
  72 #define YTPHY_INTERRUPT_STATUS_REG              0x13
  73 #define YTPHY_ISR_AUTONEG_ERR                   BIT(15)
  74 #define YTPHY_ISR_SPEED_CHANGED                 BIT(14)
  75 #define YTPHY_ISR_DUPLEX_CHANGED                BIT(13)
  76 #define YTPHY_ISR_PAGE_RECEIVED                 BIT(12)
  77 #define YTPHY_ISR_LINK_FAILED                   BIT(11)
  78 #define YTPHY_ISR_LINK_SUCCESSED                BIT(10)
  79 #define YTPHY_ISR_WOL                           BIT(6)
  80 #define YTPHY_ISR_WIRESPEED_DOWNGRADE           BIT(5)
  81 #define YTPHY_ISR_SERDES_LINK_FAILED            BIT(3)
  82 #define YTPHY_ISR_SERDES_LINK_SUCCESSED         BIT(2)
  83 #define YTPHY_ISR_POLARITY_CHANGED              BIT(1)
  84 #define YTPHY_ISR_JABBER_HAPPENED               BIT(0)
  85
  86 /* Speed Auto Downgrade Control Register */
  87 #define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG  0x14
  88 #define YTPHY_SADCR_SPEED_DOWNGRADE_EN          BIT(5)
  89
  90 /* If these bits are set to 3, the PHY attempts five times ( 3(set value) +
  91  * additional 2) before downgrading, default 0x3
  92  */
  93 #define YTPHY_SADCR_SPEED_RETRY_LIMIT           (0x3 << 2)
  94
  95 /* Rx Error Counter Register */
  96 #define YTPHY_RX_ERROR_COUNTER_REG              0x15
  97
  98 /* Extended Register's Address Offset Register */
  99 #define YTPHY_PAGE_SELECT                       0x1E
 100
 101 /* Extended Register's Data Register */
 102 #define YTPHY_PAGE_DATA                         0x1F
 103
 104 /* FIBER Auto-Negotiation link partner ability */
 105 #define YTPHY_FLPA_PAUSE                        (0x3 << 7)
 106 #define YTPHY_FLPA_ASYM_PAUSE                   (0x2 << 7)
 107
 108 #define YT8511_PAGE_SELECT      0x1e
 109 #define YT8511_PAGE             0x1f
 110 #define YT8511_EXT_CLK_GATE     0x0c
 111 #define YT8511_EXT_DELAY_DRIVE  0x0d
 112 #define YT8511_EXT_SLEEP_CTRL   0x27
 113
 114 /* 2b00 25m from pll
 115  * 2b01 25m from xtl *default*
 116  * 2b10 62.m from pll
 117  * 2b11 125m from pll
 118  */
 119 #define YT8511_CLK_125M         (BIT(2) | BIT(1))
 120 #define YT8511_PLLON_SLP        BIT(14)
 121
 122 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
 123 #define YT8511_DELAY_RX         BIT(0)
 124
 125 /* TX Gig-E Delay is bits 7:4, default 0x5
 126  * TX Fast-E Delay is bits 15:12, default 0xf
 127  * Delay = 150ps * N - 250ps
 128  * On = 2000ps, off = 50ps
 129  */
 130 #define YT8511_DELAY_GE_TX_EN   (0xf << 4)
 131 #define YT8511_DELAY_GE_TX_DIS  (0x2 << 4)
 132 #define YT8511_DELAY_FE_TX_EN   (0xf << 12)
 133 #define YT8511_DELAY_FE_TX_DIS  (0x2 << 12)
 134
 135 /* Extended register is different from MMD Register and MII Register.
 136  * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to
 137  * operate extended register.
 138  * Extended Register  start
 139  */
 140
 141 /* Phy gmii clock gating Register */
 142 #define YT8521_CLOCK_GATING_REG                 0xC
 143 #define YT8521_CGR_RX_CLK_EN                    BIT(12)
 144
 145 #define YT8521_EXTREG_SLEEP_CONTROL1_REG        0x27
 146 #define YT8521_ESC1R_SLEEP_SW                   BIT(15)
 147 #define YT8521_ESC1R_PLLON_SLP                  BIT(14)
 148
 149 /* Phy fiber Link timer cfg2 Register */
 150 #define YT8521_LINK_TIMER_CFG2_REG              0xA5
 151 #define YT8521_LTCR_EN_AUTOSEN                  BIT(15)
 152
 153 /* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers
 154  * of yt8521 phy. There is no need to switch reg space when operating these
 155  * registers.
 156  */
 157
 158 #define YT8521_REG_SPACE_SELECT_REG             0xA000
 159 #define YT8521_RSSR_SPACE_MASK                  BIT(1)
 160 #define YT8521_RSSR_FIBER_SPACE                 (0x1 << 1)
 161 #define YT8521_RSSR_UTP_SPACE                   (0x0 << 1)
 162 #define YT8521_RSSR_TO_BE_ARBITRATED            (0xFF)
 163
 164 #define YT8521_CHIP_CONFIG_REG                  0xA001
 165 #define YT8521_CCR_SW_RST                       BIT(15)
 166 /* 1b0 disable 1.9ns rxc clock delay  *default*
 167  * 1b1 enable 1.9ns rxc clock delay
 168  */
 169 #define YT8521_CCR_RXC_DLY_EN                   BIT(8)
 170 #define YT8521_CCR_RXC_DLY_1_900_NS             1900
 171
 172 #define YT8521_CCR_MODE_SEL_MASK                (BIT(2) | BIT(1) | BIT(0))
 173 #define YT8521_CCR_MODE_UTP_TO_RGMII            0
 174 #define YT8521_CCR_MODE_FIBER_TO_RGMII          1
 175 #define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII      2
 176 #define YT8521_CCR_MODE_UTP_TO_SGMII            3
 177 #define YT8521_CCR_MODE_SGPHY_TO_RGMAC          4
 178 #define YT8521_CCR_MODE_SGMAC_TO_RGPHY          5
 179 #define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO       6
 180 #define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE      7
 181
 182 /* 3 phy polling modes,poll mode combines utp and fiber mode*/
 183 #define YT8521_MODE_FIBER                       0x1
 184 #define YT8521_MODE_UTP                         0x2
 185 #define YT8521_MODE_POLL                        0x3
 186
 187 #define YT8521_RGMII_CONFIG1_REG                0xA003
 188 /* 1b0 use original tx_clk_rgmii  *default*
 189  * 1b1 use inverted tx_clk_rgmii.
 190  */
 191 #define YT8521_RC1R_TX_CLK_SEL_INVERTED         BIT(14)
 192 #define YT8521_RC1R_RX_DELAY_MASK               GENMASK(13, 10)
 193 #define YT8521_RC1R_FE_TX_DELAY_MASK            GENMASK(7, 4)
 194 #define YT8521_RC1R_GE_TX_DELAY_MASK            GENMASK(3, 0)
 195 #define YT8521_RC1R_RGMII_0_000_NS              0
 196 #define YT8521_RC1R_RGMII_0_150_NS              1
 197 #define YT8521_RC1R_RGMII_0_300_NS              2
 198 #define YT8521_RC1R_RGMII_0_450_NS              3
 199 #define YT8521_RC1R_RGMII_0_600_NS              4
 200 #define YT8521_RC1R_RGMII_0_750_NS              5
 201 #define YT8521_RC1R_RGMII_0_900_NS              6
 202 #define YT8521_RC1R_RGMII_1_050_NS              7
 203 #define YT8521_RC1R_RGMII_1_200_NS              8
 204 #define YT8521_RC1R_RGMII_1_350_NS              9
 205 #define YT8521_RC1R_RGMII_1_500_NS              10
 206 #define YT8521_RC1R_RGMII_1_650_NS              11
 207 #define YT8521_RC1R_RGMII_1_800_NS              12
 208 #define YT8521_RC1R_RGMII_1_950_NS              13
 209 #define YT8521_RC1R_RGMII_2_100_NS              14
 210 #define YT8521_RC1R_RGMII_2_250_NS              15
 211
 212 #define YTPHY_MISC_CONFIG_REG                   0xA006
 213 #define YTPHY_MCR_FIBER_SPEED_MASK              BIT(0)
 214 #define YTPHY_MCR_FIBER_1000BX                  (0x1 << 0)
 215 #define YTPHY_MCR_FIBER_100FX                   (0x0 << 0)
 216
 217 /* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */
 218 #define YTPHY_WOL_MACADDR2_REG                  0xA007
 219 #define YTPHY_WOL_MACADDR1_REG                  0xA008
 220 #define YTPHY_WOL_MACADDR0_REG                  0xA009
 221
 222 #define YTPHY_WOL_CONFIG_REG                    0xA00A
 223 #define YTPHY_WCR_INTR_SEL                      BIT(6)
 224 #define YTPHY_WCR_ENABLE                        BIT(3)
 225
 226 /* 2b00 84ms
 227  * 2b01 168ms  *default*
 228  * 2b10 336ms
 229  * 2b11 672ms
 230  */
 231 #define YTPHY_WCR_PULSE_WIDTH_MASK              (BIT(2) | BIT(1))
 232 #define YTPHY_WCR_PULSE_WIDTH_672MS             (BIT(2) | BIT(1))
 233
 234 /* 1b0 Interrupt and WOL events is level triggered and active LOW  *default*
 235  * 1b1 Interrupt and WOL events is pulse triggered and active LOW
 236  */
 237 #define YTPHY_WCR_TYPE_PULSE                    BIT(0)
 238
 239 #define YTPHY_SYNCE_CFG_REG                     0xA012
 240 #define YT8521_SCR_SYNCE_ENABLE                 BIT(5)
 241 /* 1b0 output 25m clock
 242  * 1b1 output 125m clock  *default*
 243  */
 244 #define YT8521_SCR_CLK_FRE_SEL_125M             BIT(3)
 245 #define YT8521_SCR_CLK_SRC_MASK                 GENMASK(2, 1)
 246 #define YT8521_SCR_CLK_SRC_PLL_125M             0
 247 #define YT8521_SCR_CLK_SRC_UTP_RX               1
 248 #define YT8521_SCR_CLK_SRC_SDS_RX               2
 249 #define YT8521_SCR_CLK_SRC_REF_25M              3
 250 #define YT8531_SCR_SYNCE_ENABLE                 BIT(6)
 251 /* 1b0 output 25m clock   *default*
 252  * 1b1 output 125m clock
 253  */
 254 #define YT8531_SCR_CLK_FRE_SEL_125M             BIT(4)
 255 #define YT8531_SCR_CLK_SRC_MASK                 GENMASK(3, 1)
 256 #define YT8531_SCR_CLK_SRC_PLL_125M             0
 257 #define YT8531_SCR_CLK_SRC_UTP_RX               1
 258 #define YT8531_SCR_CLK_SRC_SDS_RX               2
 259 #define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL   3
 260 #define YT8531_SCR_CLK_SRC_REF_25M              4
 261 #define YT8531_SCR_CLK_SRC_SSC_25M              5
 262
 263 /* Extended Register  end */
 264
 265 #define YTPHY_DTS_OUTPUT_CLK_DIS                0
 266 #define YTPHY_DTS_OUTPUT_CLK_25M                25000000
 267 #define YTPHY_DTS_OUTPUT_CLK_125M               125000000
 268
 269 struct yt8521_priv {
 270         /* combo_advertising is used for case of YT8521 in combo mode,
 271          * this means that yt8521 may work in utp or fiber mode which depends
 272          * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED).
 273          */
 274         __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising);
 275
 276         /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/
 277         u8 polling_mode;
 278         u8 strap_mode; /* 8 working modes  */
 279         /* current reg page of yt8521 phy:
 280          * YT8521_RSSR_UTP_SPACE
 281          * YT8521_RSSR_FIBER_SPACE
 282          * YT8521_RSSR_TO_BE_ARBITRATED
 283          */
 284         u8 reg_page;
 285 };
 286
 287 /**
 288  * ytphy_read_ext() - read a PHY's extended register
 289  * @phydev: a pointer to a &struct phy_device
 290  * @regnum: register number to read
 291  *
 292  * NOTE:The caller must have taken the MDIO bus lock.
 293  *
 294  * returns the value of regnum reg or negative error code
 295  */
 296 static int ytphy_read_ext(struct phy_device *phydev, u16 regnum)
 297 {
 298         int ret;
 299
 300         ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
 301         if (ret < 0)
 302                 return ret;
 303
 304         return __phy_read(phydev, YTPHY_PAGE_DATA);
 305 }
 306
 307 /**
 308  * ytphy_read_ext_with_lock() - read a PHY's extended register
 309  * @phydev: a pointer to a &struct phy_device
 310  * @regnum: register number to read
 311  *
 312  * returns the value of regnum reg or negative error code
 313  */
 314 static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum)
 315 {
 316         int ret;
 317
 318         phy_lock_mdio_bus(phydev);
 319         ret = ytphy_read_ext(phydev, regnum);
 320         phy_unlock_mdio_bus(phydev);
 321
 322         return ret;
 323 }
 324
 325 /**
 326  * ytphy_write_ext() - write a PHY's extended register
 327  * @phydev: a pointer to a &struct phy_device
 328  * @regnum: register number to write
 329  * @val: value to write to @regnum
 330  *
 331  * NOTE:The caller must have taken the MDIO bus lock.
 332  *
 333  * returns 0 or negative error code
 334  */
 335 static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val)
 336 {
 337         int ret;
 338
 339         ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
 340         if (ret < 0)
 341                 return ret;
 342
 343         return __phy_write(phydev, YTPHY_PAGE_DATA, val);
 344 }
 345
 346 /**
 347  * ytphy_write_ext_with_lock() - write a PHY's extended register
 348  * @phydev: a pointer to a &struct phy_device
 349  * @regnum: register number to write
 350  * @val: value to write to @regnum
 351  *
 352  * returns 0 or negative error code
 353  */
 354 static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum,
 355                                      u16 val)
 356 {
 357         int ret;
 358
 359         phy_lock_mdio_bus(phydev);
 360         ret = ytphy_write_ext(phydev, regnum, val);
 361         phy_unlock_mdio_bus(phydev);
 362
 363         return ret;
 364 }
 365
 366 /**
 367  * ytphy_modify_ext() - bits modify a PHY's extended register
 368  * @phydev: a pointer to a &struct phy_device
 369  * @regnum: register number to write
 370  * @mask: bit mask of bits to clear
 371  * @set: bit mask of bits to set
 372  *
 373  * NOTE: Convenience function which allows a PHY's extended register to be
 374  * modified as new register value = (old register value & ~mask) | set.
 375  * The caller must have taken the MDIO bus lock.
 376  *
 377  * returns 0 or negative error code
 378  */
 379 static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
 380                             u16 set)
 381 {
 382         int ret;
 383
 384         ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
 385         if (ret < 0)
 386                 return ret;
 387
 388         return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set);
 389 }
 390
 391 /**
 392  * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register
 393  * @phydev: a pointer to a &struct phy_device
 394  * @regnum: register number to write
 395  * @mask: bit mask of bits to clear
 396  * @set: bit mask of bits to set
 397  *
 398  * NOTE: Convenience function which allows a PHY's extended register to be
 399  * modified as new register value = (old register value & ~mask) | set.
 400  *
 401  * returns 0 or negative error code
 402  */
 403 static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum,
 404                                       u16 mask, u16 set)
 405 {
 406         int ret;
 407
 408         phy_lock_mdio_bus(phydev);
 409         ret = ytphy_modify_ext(phydev, regnum, mask, set);
 410         phy_unlock_mdio_bus(phydev);
 411
 412         return ret;
 413 }
 414
 415 /**
 416  * ytphy_get_wol() - report whether wake-on-lan is enabled
 417  * @phydev: a pointer to a &struct phy_device
 418  * @wol: a pointer to a &struct ethtool_wolinfo
 419  *
 420  * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg.
 421  */
 422 static void ytphy_get_wol(struct phy_device *phydev,
 423                           struct ethtool_wolinfo *wol)
 424 {
 425         int wol_config;
 426
 427         wol->supported = WAKE_MAGIC;
 428         wol->wolopts = 0;
 429
 430         wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
 431         if (wol_config < 0)
 432                 return;
 433
 434         if (wol_config & YTPHY_WCR_ENABLE)
 435                 wol->wolopts |= WAKE_MAGIC;
 436 }
 437
 438 /**
 439  * ytphy_set_wol() - turn wake-on-lan on or off
 440  * @phydev: a pointer to a &struct phy_device
 441  * @wol: a pointer to a &struct ethtool_wolinfo
 442  *
 443  * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG
 444  * and YTPHY_WOL_MACADDR0_REG are common ext reg. The
 445  * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register.
 446  *
 447  * returns 0 or negative errno code
 448  */
 449 static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 450 {
 451         struct net_device *p_attached_dev;
 452         const u16 mac_addr_reg[] = {
 453                 YTPHY_WOL_MACADDR2_REG,
 454                 YTPHY_WOL_MACADDR1_REG,
 455                 YTPHY_WOL_MACADDR0_REG,
 456         };
 457         const u8 *mac_addr;
 458         int old_page;
 459         int ret = 0;
 460         u16 mask;
 461         u16 val;
 462         u8 i;
 463
 464         if (wol->wolopts & WAKE_MAGIC) {
 465                 p_attached_dev = phydev->attached_dev;
 466                 if (!p_attached_dev)
 467                         return -ENODEV;
 468
 469                 mac_addr = (const u8 *)p_attached_dev->dev_addr;
 470                 if (!is_valid_ether_addr(mac_addr))
 471                         return -EINVAL;
 472
 473                 /* lock mdio bus then switch to utp reg space */
 474                 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
 475                 if (old_page < 0)
 476                         goto err_restore_page;
 477
 478                 /* Store the device address for the magic packet */
 479                 for (i = 0; i < 3; i++) {
 480                         ret = ytphy_write_ext(phydev, mac_addr_reg[i],
 481                                               ((mac_addr[i * 2] << 8)) |
 482                                                       (mac_addr[i * 2 + 1]));
 483                         if (ret < 0)
 484                                 goto err_restore_page;
 485                 }
 486
 487                 /* Enable WOL feature */
 488                 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
 489                 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
 490                 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
 491                 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val);
 492                 if (ret < 0)
 493                         goto err_restore_page;
 494
 495                 /* Enable WOL interrupt */
 496                 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
 497                                    YTPHY_IER_WOL);
 498                 if (ret < 0)
 499                         goto err_restore_page;
 500
 501         } else {
 502                 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
 503                 if (old_page < 0)
 504                         goto err_restore_page;
 505
 506                 /* Disable WOL feature */
 507                 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
 508                 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0);
 509
 510                 /* Disable WOL interrupt */
 511                 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
 512                                    YTPHY_IER_WOL, 0);
 513                 if (ret < 0)
 514                         goto err_restore_page;
 515         }
 516
 517 err_restore_page:
 518         return phy_restore_page(phydev, old_page, ret);
 519 }
 520
 521 static int yt8531_set_wol(struct phy_device *phydev,
 522                           struct ethtool_wolinfo *wol)
 523 {
 524         const u16 mac_addr_reg[] = {
 525                 YTPHY_WOL_MACADDR2_REG,
 526                 YTPHY_WOL_MACADDR1_REG,
 527                 YTPHY_WOL_MACADDR0_REG,
 528         };
 529         const u8 *mac_addr;
 530         u16 mask, val;
 531         int ret;
 532         u8 i;
 533
 534         if (wol->wolopts & WAKE_MAGIC) {
 535                 mac_addr = phydev->attached_dev->dev_addr;
 536
 537                 /* Store the device address for the magic packet */
 538                 for (i = 0; i < 3; i++) {
 539                         ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i],
 540                                                         ((mac_addr[i * 2] << 8)) |
 541                                                         (mac_addr[i * 2 + 1]));
 542                         if (ret < 0)
 543                                 return ret;
 544                 }
 545
 546                 /* Enable WOL feature */
 547                 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
 548                 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
 549                 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
 550                 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG,
 551                                                  mask, val);
 552                 if (ret < 0)
 553                         return ret;
 554
 555                 /* Enable WOL interrupt */
 556                 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
 557                                  YTPHY_IER_WOL);
 558                 if (ret < 0)
 559                         return ret;
 560         } else {
 561                 /* Disable WOL feature */
 562                 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
 563                 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG,
 564                                                  mask, 0);
 565
 566                 /* Disable WOL interrupt */
 567                 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
 568                                  YTPHY_IER_WOL, 0);
 569                 if (ret < 0)
 570                         return ret;
 571         }
 572
 573         return 0;
 574 }
 575
 576 static int yt8511_read_page(struct phy_device *phydev)
 577 {
 578         return __phy_read(phydev, YT8511_PAGE_SELECT);
 579 };
 580
 581 static int yt8511_write_page(struct phy_device *phydev, int page)
 582 {
 583         return __phy_write(phydev, YT8511_PAGE_SELECT, page);
 584 };
 585
 586 static int yt8511_config_init(struct phy_device *phydev)
 587 {
 588         int oldpage, ret = 0;
 589         unsigned int ge, fe;
 590
 591         oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
 592         if (oldpage < 0)
 593                 goto err_restore_page;
 594
 595         /* set rgmii delay mode */
 596         switch (phydev->interface) {
 597         case PHY_INTERFACE_MODE_RGMII:
 598                 ge = YT8511_DELAY_GE_TX_DIS;
 599                 fe = YT8511_DELAY_FE_TX_DIS;
 600                 break;
 601         case PHY_INTERFACE_MODE_RGMII_RXID:
 602                 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
 603                 fe = YT8511_DELAY_FE_TX_DIS;
 604                 break;
 605         case PHY_INTERFACE_MODE_RGMII_TXID:
 606                 ge = YT8511_DELAY_GE_TX_EN;
 607                 fe = YT8511_DELAY_FE_TX_EN;
 608                 break;
 609         case PHY_INTERFACE_MODE_RGMII_ID:
 610                 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
 611                 fe = YT8511_DELAY_FE_TX_EN;
 612                 break;
 613         default: /* do not support other modes */
 614                 ret = -EOPNOTSUPP;
 615                 goto err_restore_page;
 616         }
 617
 618         ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
 619         if (ret < 0)
 620                 goto err_restore_page;
 621
 622         /* set clock mode to 125mhz */
 623         ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
 624         if (ret < 0)
 625                 goto err_restore_page;
 626
 627         /* fast ethernet delay is in a separate page */
 628         ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
 629         if (ret < 0)
 630                 goto err_restore_page;
 631
 632         ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
 633         if (ret < 0)
 634                 goto err_restore_page;
 635
 636         /* leave pll enabled in sleep */
 637         ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
 638         if (ret < 0)
 639                 goto err_restore_page;
 640
 641         ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
 642         if (ret < 0)
 643                 goto err_restore_page;
 644
 645 err_restore_page:
 646         return phy_restore_page(phydev, oldpage, ret);
 647 }
 648
 649 /**
 650  * yt8521_read_page() - read reg page
 651  * @phydev: a pointer to a &struct phy_device
 652  *
 653  * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/
 654  * YT8521_RSSR_UTP_SPACE) or negative errno code
 655  */
 656 static int yt8521_read_page(struct phy_device *phydev)
 657 {
 658         int old_page;
 659
 660         old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG);
 661         if (old_page < 0)
 662                 return old_page;
 663
 664         if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
 665                 return YT8521_RSSR_FIBER_SPACE;
 666
 667         return YT8521_RSSR_UTP_SPACE;
 668 };
 669
 670 /**
 671  * yt8521_write_page() - write reg page
 672  * @phydev: a pointer to a &struct phy_device
 673  * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write.
 674  *
 675  * returns 0 or negative errno code
 676  */
 677 static int yt8521_write_page(struct phy_device *phydev, int page)
 678 {
 679         int mask = YT8521_RSSR_SPACE_MASK;
 680         int set;
 681
 682         if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
 683                 set = YT8521_RSSR_FIBER_SPACE;
 684         else
 685                 set = YT8521_RSSR_UTP_SPACE;
 686
 687         return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set);
 688 };
 689
 690 /**
 691  * struct ytphy_cfg_reg_map - map a config value to a register value
 692  * @cfg: value in device configuration
 693  * @reg: value in the register
 694  */
 695 struct ytphy_cfg_reg_map {
 696         u32 cfg;
 697         u32 reg;
 698 };
 699
 700 static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = {
 701         /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */
 702         { 0,    YT8521_RC1R_RGMII_0_000_NS },
 703         { 150,  YT8521_RC1R_RGMII_0_150_NS },
 704         { 300,  YT8521_RC1R_RGMII_0_300_NS },
 705         { 450,  YT8521_RC1R_RGMII_0_450_NS },
 706         { 600,  YT8521_RC1R_RGMII_0_600_NS },
 707         { 750,  YT8521_RC1R_RGMII_0_750_NS },
 708         { 900,  YT8521_RC1R_RGMII_0_900_NS },
 709         { 1050, YT8521_RC1R_RGMII_1_050_NS },
 710         { 1200, YT8521_RC1R_RGMII_1_200_NS },
 711         { 1350, YT8521_RC1R_RGMII_1_350_NS },
 712         { 1500, YT8521_RC1R_RGMII_1_500_NS },
 713         { 1650, YT8521_RC1R_RGMII_1_650_NS },
 714         { 1800, YT8521_RC1R_RGMII_1_800_NS },
 715         { 1950, YT8521_RC1R_RGMII_1_950_NS },   /* default tx/rx delay */
 716         { 2100, YT8521_RC1R_RGMII_2_100_NS },
 717         { 2250, YT8521_RC1R_RGMII_2_250_NS },
 718
 719         /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */
 720         { 0    + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_0_000_NS },
 721         { 150  + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_0_150_NS },
 722         { 300  + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_0_300_NS },
 723         { 450  + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_0_450_NS },
 724         { 600  + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_0_600_NS },
 725         { 750  + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_0_750_NS },
 726         { 900  + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_0_900_NS },
 727         { 1050 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_1_050_NS },
 728         { 1200 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_1_200_NS },
 729         { 1350 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_1_350_NS },
 730         { 1500 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_1_500_NS },
 731         { 1650 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_1_650_NS },
 732         { 1800 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_1_800_NS },
 733         { 1950 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_1_950_NS },
 734         { 2100 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_2_100_NS },
 735         { 2250 + YT8521_CCR_RXC_DLY_1_900_NS,   YT8521_RC1R_RGMII_2_250_NS }
 736 };
 737
 738 static u32 ytphy_get_delay_reg_value(struct phy_device *phydev,
 739                                      const char *prop_name,
 740                                      const struct ytphy_cfg_reg_map *tbl,
 741                                      int tb_size,
 742                                      u16 *rxc_dly_en,
 743                                      u32 dflt)
 744 {
 745         struct device_node *node = phydev->mdio.dev.of_node;
 746         int tb_size_half = tb_size / 2;
 747         u32 val;
 748         int i;
 749
 750         if (of_property_read_u32(node, prop_name, &val))
 751                 goto err_dts_val;
 752
 753         /* when rxc_dly_en is NULL, it is get the delay for tx, only half of
 754          * tb_size is valid.
 755          */
 756         if (!rxc_dly_en)
 757                 tb_size = tb_size_half;
 758
 759         for (i = 0; i < tb_size; i++) {
 760                 if (tbl[i].cfg == val) {
 761                         if (rxc_dly_en && i < tb_size_half)
 762                                 *rxc_dly_en = 0;
 763                         return tbl[i].reg;
 764                 }
 765         }
 766
 767         phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n",
 768                     val, prop_name, dflt);
 769
 770 err_dts_val:
 771         /* when rxc_dly_en is not NULL, it is get the delay for rx.
 772          * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps,
 773          * so YT8521_CCR_RXC_DLY_EN should not be set.
 774          */
 775         if (rxc_dly_en)
 776                 *rxc_dly_en = 0;
 777
 778         return dflt;
 779 }
 780
 781 static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
 782 {
 783         int tb_size = ARRAY_SIZE(ytphy_rgmii_delays);
 784         u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN;
 785         u32 rx_reg, tx_reg;
 786         u16 mask, val = 0;
 787         int ret;
 788
 789         rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps",
 790                                            ytphy_rgmii_delays, tb_size,
 791                                            &rxc_dly_en,
 792                                            YT8521_RC1R_RGMII_1_950_NS);
 793         tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps",
 794                                            ytphy_rgmii_delays, tb_size, NULL,
 795                                            YT8521_RC1R_RGMII_1_950_NS);
 796
 797         switch (phydev->interface) {
 798         case PHY_INTERFACE_MODE_RGMII:
 799                 rxc_dly_en = 0;
 800                 break;
 801         case PHY_INTERFACE_MODE_RGMII_RXID:
 802                 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg);
 803                 break;
 804         case PHY_INTERFACE_MODE_RGMII_TXID:
 805                 rxc_dly_en = 0;
 806                 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
 807                 break;
 808         case PHY_INTERFACE_MODE_RGMII_ID:
 809                 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) |
 810                        FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
 811                 break;
 812         default: /* do not support other modes */
 813                 return -EOPNOTSUPP;
 814         }
 815
 816         ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
 817                                YT8521_CCR_RXC_DLY_EN, rxc_dly_en);
 818         if (ret < 0)
 819                 return ret;
 820
 821         /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */
 822         mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK;
 823         return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val);
 824 }
 825
 826 static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev)
 827 {
 828         int ret;
 829
 830         phy_lock_mdio_bus(phydev);
 831         ret = ytphy_rgmii_clk_delay_config(phydev);
 832         phy_unlock_mdio_bus(phydev);
 833
 834         return ret;
 835 }
 836
 837 /**
 838  * yt8521_probe() - read chip config then set suitable polling_mode
 839  * @phydev: a pointer to a &struct phy_device
 840  *
 841  * returns 0 or negative errno code
 842  */
 843 static int yt8521_probe(struct phy_device *phydev)
 844 {
 845         struct device_node *node = phydev->mdio.dev.of_node;
 846         struct device *dev = &phydev->mdio.dev;
 847         struct yt8521_priv *priv;
 848         int chip_config;
 849         u16 mask, val;
 850         u32 freq;
 851         int ret;
 852
 853         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 854         if (!priv)
 855                 return -ENOMEM;
 856
 857         phydev->priv = priv;
 858
 859         chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
 860         if (chip_config < 0)
 861                 return chip_config;
 862
 863         priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK;
 864         switch (priv->strap_mode) {
 865         case YT8521_CCR_MODE_FIBER_TO_RGMII:
 866         case YT8521_CCR_MODE_SGPHY_TO_RGMAC:
 867         case YT8521_CCR_MODE_SGMAC_TO_RGPHY:
 868                 priv->polling_mode = YT8521_MODE_FIBER;
 869                 priv->reg_page = YT8521_RSSR_FIBER_SPACE;
 870                 phydev->port = PORT_FIBRE;
 871                 break;
 872         case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII:
 873         case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO:
 874         case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE:
 875                 priv->polling_mode = YT8521_MODE_POLL;
 876                 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
 877                 phydev->port = PORT_NONE;
 878                 break;
 879         case YT8521_CCR_MODE_UTP_TO_SGMII:
 880         case YT8521_CCR_MODE_UTP_TO_RGMII:
 881                 priv->polling_mode = YT8521_MODE_UTP;
 882                 priv->reg_page = YT8521_RSSR_UTP_SPACE;
 883                 phydev->port = PORT_TP;
 884                 break;
 885         }
 886         /* set default reg space */
 887         if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
 888                 ret = ytphy_write_ext_with_lock(phydev,
 889                                                 YT8521_REG_SPACE_SELECT_REG,
 890                                                 priv->reg_page);
 891                 if (ret < 0)
 892                         return ret;
 893         }
 894
 895         if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
 896                 freq = YTPHY_DTS_OUTPUT_CLK_DIS;
 897
 898         if (phydev->drv->phy_id == PHY_ID_YT8521) {
 899                 switch (freq) {
 900                 case YTPHY_DTS_OUTPUT_CLK_DIS:
 901                         mask = YT8521_SCR_SYNCE_ENABLE;
 902                         val = 0;
 903                         break;
 904                 case YTPHY_DTS_OUTPUT_CLK_25M:
 905                         mask = YT8521_SCR_SYNCE_ENABLE |
 906                                YT8521_SCR_CLK_SRC_MASK |
 907                                YT8521_SCR_CLK_FRE_SEL_125M;
 908                         val = YT8521_SCR_SYNCE_ENABLE |
 909                               FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
 910                                          YT8521_SCR_CLK_SRC_REF_25M);
 911                         break;
 912                 case YTPHY_DTS_OUTPUT_CLK_125M:
 913                         mask = YT8521_SCR_SYNCE_ENABLE |
 914                                YT8521_SCR_CLK_SRC_MASK |
 915                                YT8521_SCR_CLK_FRE_SEL_125M;
 916                         val = YT8521_SCR_SYNCE_ENABLE |
 917                               YT8521_SCR_CLK_FRE_SEL_125M |
 918                               FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
 919                                          YT8521_SCR_CLK_SRC_PLL_125M);
 920                         break;
 921                 default:
 922                         phydev_warn(phydev, "Freq err:%u\n", freq);
 923                         return -EINVAL;
 924                 }
 925         } else if (phydev->drv->phy_id == PHY_ID_YT8531S) {
 926                 switch (freq) {
 927                 case YTPHY_DTS_OUTPUT_CLK_DIS:
 928                         mask = YT8531_SCR_SYNCE_ENABLE;
 929                         val = 0;
 930                         break;
 931                 case YTPHY_DTS_OUTPUT_CLK_25M:
 932                         mask = YT8531_SCR_SYNCE_ENABLE |
 933                                YT8531_SCR_CLK_SRC_MASK |
 934                                YT8531_SCR_CLK_FRE_SEL_125M;
 935                         val = YT8531_SCR_SYNCE_ENABLE |
 936                               FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
 937                                          YT8531_SCR_CLK_SRC_REF_25M);
 938                         break;
 939                 case YTPHY_DTS_OUTPUT_CLK_125M:
 940                         mask = YT8531_SCR_SYNCE_ENABLE |
 941                                YT8531_SCR_CLK_SRC_MASK |
 942                                YT8531_SCR_CLK_FRE_SEL_125M;
 943                         val = YT8531_SCR_SYNCE_ENABLE |
 944                               YT8531_SCR_CLK_FRE_SEL_125M |
 945                               FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
 946                                          YT8531_SCR_CLK_SRC_PLL_125M);
 947                         break;
 948                 default:
 949                         phydev_warn(phydev, "Freq err:%u\n", freq);
 950                         return -EINVAL;
 951                 }
 952         } else {
 953                 phydev_warn(phydev, "PHY id err\n");
 954                 return -EINVAL;
 955         }
 956
 957         return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask,
 958                                           val);
 959 }
 960
 961 static int yt8531_probe(struct phy_device *phydev)
 962 {
 963         struct device_node *node = phydev->mdio.dev.of_node;
 964         u16 mask, val;
 965         u32 freq;
 966
 967         if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq))
 968                 freq = YTPHY_DTS_OUTPUT_CLK_DIS;
 969
 970         switch (freq) {
 971         case YTPHY_DTS_OUTPUT_CLK_DIS:
 972                 mask = YT8531_SCR_SYNCE_ENABLE;
 973                 val = 0;
 974                 break;
 975         case YTPHY_DTS_OUTPUT_CLK_25M:
 976                 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
 977                        YT8531_SCR_CLK_FRE_SEL_125M;
 978                 val = YT8531_SCR_SYNCE_ENABLE |
 979                       FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
 980                                  YT8531_SCR_CLK_SRC_REF_25M);
 981                 break;
 982         case YTPHY_DTS_OUTPUT_CLK_125M:
 983                 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK |
 984                        YT8531_SCR_CLK_FRE_SEL_125M;
 985                 val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M |
 986                       FIELD_PREP(YT8531_SCR_CLK_SRC_MASK,
 987                                  YT8531_SCR_CLK_SRC_PLL_125M);
 988                 break;
 989         default:
 990                 phydev_warn(phydev, "Freq err:%u\n", freq);
 991                 return -EINVAL;
 992         }
 993
 994         return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask,
 995                                           val);
 996 }
 997
 998 /**
 999  * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
1000  * @phydev: a pointer to a &struct phy_device
1001  *
1002  * NOTE:The caller must have taken the MDIO bus lock.
1003  *
1004  * returns 0 or negative errno code
1005  */
1006 static int ytphy_utp_read_lpa(struct phy_device *phydev)
1007 {
1008         int lpa, lpagb;
1009
1010         if (phydev->autoneg == AUTONEG_ENABLE) {
1011                 if (!phydev->autoneg_complete) {
1012                         mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
1013                                                         0);
1014                         mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
1015                         return 0;
1016                 }
1017
1018                 if (phydev->is_gigabit_capable) {
1019                         lpagb = __phy_read(phydev, MII_STAT1000);
1020                         if (lpagb < 0)
1021                                 return lpagb;
1022
1023                         if (lpagb & LPA_1000MSFAIL) {
1024                                 int adv = __phy_read(phydev, MII_CTRL1000);
1025
1026                                 if (adv < 0)
1027                                         return adv;
1028
1029                                 if (adv & CTL1000_ENABLE_MASTER)
1030                                         phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
1031                                 else
1032                                         phydev_err(phydev, "Master/Slave resolution failed\n");
1033                                 return -ENOLINK;
1034                         }
1035
1036                         mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
1037                                                         lpagb);
1038                 }
1039
1040                 lpa = __phy_read(phydev, MII_LPA);
1041                 if (lpa < 0)
1042                         return lpa;
1043
1044                 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1045         } else {
1046                 linkmode_zero(phydev->lp_advertising);
1047         }
1048
1049         return 0;
1050 }
1051
1052 /**
1053  * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber
1054  * mode, adjust speed and duplex.
1055  * @phydev: a pointer to a &struct phy_device
1056  * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG
1057  * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode)
1058  *
1059  * NOTE:The caller must have taken the MDIO bus lock.
1060  *
1061  * returns 0
1062  */
1063 static int yt8521_adjust_status(struct phy_device *phydev, int status,
1064                                 bool is_utp)
1065 {
1066         int speed_mode, duplex;
1067         int speed;
1068         int err;
1069         int lpa;
1070
1071         if (is_utp)
1072                 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET;
1073         else
1074                 duplex = DUPLEX_FULL;   /* for fiber, it always DUPLEX_FULL */
1075
1076         speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >>
1077                      YTPHY_SSR_SPEED_MODE_OFFSET;
1078
1079         switch (speed_mode) {
1080         case YTPHY_SSR_SPEED_10M:
1081                 if (is_utp)
1082                         speed = SPEED_10;
1083                 else
1084                         /* for fiber, it will never run here, default to
1085                          * SPEED_UNKNOWN
1086                          */
1087                         speed = SPEED_UNKNOWN;
1088                 break;
1089         case YTPHY_SSR_SPEED_100M:
1090                 speed = SPEED_100;
1091                 break;
1092         case YTPHY_SSR_SPEED_1000M:
1093                 speed = SPEED_1000;
1094                 break;
1095         default:
1096                 speed = SPEED_UNKNOWN;
1097                 break;
1098         }
1099
1100         phydev->speed = speed;
1101         phydev->duplex = duplex;
1102
1103         if (is_utp) {
1104                 err = ytphy_utp_read_lpa(phydev);
1105                 if (err < 0)
1106                         return err;
1107
1108                 phy_resolve_aneg_pause(phydev);
1109         } else {
1110                 lpa = __phy_read(phydev, MII_LPA);
1111                 if (lpa < 0)
1112                         return lpa;
1113
1114                 /* only support 1000baseX Full */
1115                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1116                                  phydev->lp_advertising, lpa & LPA_1000XFULL);
1117
1118                 if (!(lpa & YTPHY_FLPA_PAUSE)) {
1119                         phydev->pause = 0;
1120                         phydev->asym_pause = 0;
1121                 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) {
1122                         phydev->pause = 1;
1123                         phydev->asym_pause = 1;
1124                 } else {
1125                         phydev->pause = 1;
1126                         phydev->asym_pause = 0;
1127                 }
1128         }
1129
1130         return 0;
1131 }
1132
1133 /**
1134  * yt8521_read_status_paged() -  determines the speed and duplex of one page
1135  * @phydev: a pointer to a &struct phy_device
1136  * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1137  * operate.
1138  *
1139  * returns 1 (utp or fiber link),0 (no link) or negative errno code
1140  */
1141 static int yt8521_read_status_paged(struct phy_device *phydev, int page)
1142 {
1143         int fiber_latch_val;
1144         int fiber_curr_val;
1145         int old_page;
1146         int ret = 0;
1147         int status;
1148         int link;
1149
1150         linkmode_zero(phydev->lp_advertising);
1151         phydev->duplex = DUPLEX_UNKNOWN;
1152         phydev->speed = SPEED_UNKNOWN;
1153         phydev->asym_pause = 0;
1154         phydev->pause = 0;
1155
1156         /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber
1157          * respectively. but for utp/fiber combo mode, reg space should be
1158          * arbitrated based on media priority. by default, utp takes
1159          * priority. reg space should be properly set before read
1160          * YTPHY_SPECIFIC_STATUS_REG.
1161          */
1162
1163         page &= YT8521_RSSR_SPACE_MASK;
1164         old_page = phy_select_page(phydev, page);
1165         if (old_page < 0)
1166                 goto err_restore_page;
1167
1168         /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex
1169          * of the PHY is actually using.
1170          */
1171         ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
1172         if (ret < 0)
1173                 goto err_restore_page;
1174
1175         status = ret;
1176         link = !!(status & YTPHY_SSR_LINK);
1177
1178         /* When PHY is in fiber mode, speed transferred from 1000Mbps to
1179          * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so
1180          * we need check MII_BMSR to identify such case.
1181          */
1182         if (page == YT8521_RSSR_FIBER_SPACE) {
1183                 ret = __phy_read(phydev, MII_BMSR);
1184                 if (ret < 0)
1185                         goto err_restore_page;
1186
1187                 fiber_latch_val = ret;
1188                 ret = __phy_read(phydev, MII_BMSR);
1189                 if (ret < 0)
1190                         goto err_restore_page;
1191
1192                 fiber_curr_val = ret;
1193                 if (link && fiber_latch_val != fiber_curr_val) {
1194                         link = 0;
1195                         phydev_info(phydev,
1196                                     "%s, fiber link down detect, latch = %04x, curr = %04x\n",
1197                                     __func__, fiber_latch_val, fiber_curr_val);
1198                 }
1199         } else {
1200                 /* Read autonegotiation status */
1201                 ret = __phy_read(phydev, MII_BMSR);
1202                 if (ret < 0)
1203                         goto err_restore_page;
1204
1205                 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0;
1206         }
1207
1208         if (link) {
1209                 if (page == YT8521_RSSR_UTP_SPACE)
1210                         yt8521_adjust_status(phydev, status, true);
1211                 else
1212                         yt8521_adjust_status(phydev, status, false);
1213         }
1214         return phy_restore_page(phydev, old_page, link);
1215
1216 err_restore_page:
1217         return phy_restore_page(phydev, old_page, ret);
1218 }
1219
1220 /**
1221  * yt8521_read_status() -  determines the negotiated speed and duplex
1222  * @phydev: a pointer to a &struct phy_device
1223  *
1224  * returns 0 or negative errno code
1225  */
1226 static int yt8521_read_status(struct phy_device *phydev)
1227 {
1228         struct yt8521_priv *priv = phydev->priv;
1229         int link_fiber = 0;
1230         int link_utp;
1231         int link;
1232         int ret;
1233
1234         if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1235                 link = yt8521_read_status_paged(phydev, priv->reg_page);
1236                 if (link < 0)
1237                         return link;
1238         } else {
1239                 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is
1240                  * needed. by default, utp is higher priority.
1241                  */
1242
1243                 link_utp = yt8521_read_status_paged(phydev,
1244                                                     YT8521_RSSR_UTP_SPACE);
1245                 if (link_utp < 0)
1246                         return link_utp;
1247
1248                 if (!link_utp) {
1249                         link_fiber = yt8521_read_status_paged(phydev,
1250                                                               YT8521_RSSR_FIBER_SPACE);
1251                         if (link_fiber < 0)
1252                                 return link_fiber;
1253                 }
1254
1255                 link = link_utp || link_fiber;
1256         }
1257
1258         if (link) {
1259                 if (phydev->link == 0) {
1260                         /* arbitrate reg space based on linkup media type. */
1261                         if (priv->polling_mode == YT8521_MODE_POLL &&
1262                             priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
1263                                 if (link_fiber)
1264                                         priv->reg_page =
1265                                                 YT8521_RSSR_FIBER_SPACE;
1266                                 else
1267                                         priv->reg_page = YT8521_RSSR_UTP_SPACE;
1268
1269                                 ret = ytphy_write_ext_with_lock(phydev,
1270                                                                 YT8521_REG_SPACE_SELECT_REG,
1271                                                                 priv->reg_page);
1272                                 if (ret < 0)
1273                                         return ret;
1274
1275                                 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP;
1276
1277                                 phydev_info(phydev, "%s, link up, media: %s\n",
1278                                             __func__,
1279                                             (phydev->port == PORT_TP) ?
1280                                             "UTP" : "Fiber");
1281                         }
1282                 }
1283                 phydev->link = 1;
1284         } else {
1285                 if (phydev->link == 1) {
1286                         phydev_info(phydev, "%s, link down, media: %s\n",
1287                                     __func__, (phydev->port == PORT_TP) ?
1288                                     "UTP" : "Fiber");
1289
1290                         /* When in YT8521_MODE_POLL mode, need prepare for next
1291                          * arbitration.
1292                          */
1293                         if (priv->polling_mode == YT8521_MODE_POLL) {
1294                                 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
1295                                 phydev->port = PORT_NONE;
1296                         }
1297                 }
1298
1299                 phydev->link = 0;
1300         }
1301
1302         return 0;
1303 }
1304
1305 /**
1306  * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page
1307  * @phydev: the phy_device struct
1308  * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate
1309  * @mask: bit mask of bits to clear
1310  * @set: bit mask of bits to set
1311  *
1312  * NOTE: Convenience function which allows a PHY's BMCR register to be
1313  * modified as new register value = (old register value & ~mask) | set.
1314  * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1315  * has MII_BMCR. poll mode combines utp and faber,so need do both.
1316  * If it is reset, it will wait for completion.
1317  *
1318  * returns 0 or negative errno code
1319  */
1320 static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page,
1321                                     u16 mask, u16 set)
1322 {
1323         int max_cnt = 500; /* the max wait time of reset ~ 500 ms */
1324         int old_page;
1325         int ret = 0;
1326
1327         old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
1328         if (old_page < 0)
1329                 goto err_restore_page;
1330
1331         ret = __phy_modify(phydev, MII_BMCR, mask, set);
1332         if (ret < 0)
1333                 goto err_restore_page;
1334
1335         /* If it is reset, need to wait for the reset to complete */
1336         if (set == BMCR_RESET) {
1337                 while (max_cnt--) {
1338                         usleep_range(1000, 1100);
1339                         ret = __phy_read(phydev, MII_BMCR);
1340                         if (ret < 0)
1341                                 goto err_restore_page;
1342
1343                         if (!(ret & BMCR_RESET))
1344                                 return phy_restore_page(phydev, old_page, 0);
1345                 }
1346         }
1347
1348 err_restore_page:
1349         return phy_restore_page(phydev, old_page, ret);
1350 }
1351
1352 /**
1353  * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register
1354  * @phydev: the phy_device struct
1355  * @mask: bit mask of bits to clear
1356  * @set: bit mask of bits to set
1357  *
1358  * NOTE: Convenience function which allows a PHY's BMCR register to be
1359  * modified as new register value = (old register value & ~mask) | set.
1360  * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1361  * has MII_BMCR. poll mode combines utp and faber,so need do both.
1362  *
1363  * returns 0 or negative errno code
1364  */
1365 static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask,
1366                                         u16 set)
1367 {
1368         struct yt8521_priv *priv = phydev->priv;
1369         int ret;
1370
1371         if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1372                 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask,
1373                                                set);
1374                 if (ret < 0)
1375                         return ret;
1376         } else {
1377                 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE,
1378                                                mask, set);
1379                 if (ret < 0)
1380                         return ret;
1381
1382                 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE,
1383                                                mask, set);
1384                 if (ret < 0)
1385                         return ret;
1386         }
1387         return 0;
1388 }
1389
1390 /**
1391  * yt8521_soft_reset() - called to issue a PHY software reset
1392  * @phydev: a pointer to a &struct phy_device
1393  *
1394  * returns 0 or negative errno code
1395  */
1396 static int yt8521_soft_reset(struct phy_device *phydev)
1397 {
1398         return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET);
1399 }
1400
1401 /**
1402  * yt8521_suspend() - suspend the hardware
1403  * @phydev: a pointer to a &struct phy_device
1404  *
1405  * returns 0 or negative errno code
1406  */
1407 static int yt8521_suspend(struct phy_device *phydev)
1408 {
1409         int wol_config;
1410
1411         /* YTPHY_WOL_CONFIG_REG is common ext reg */
1412         wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1413         if (wol_config < 0)
1414                 return wol_config;
1415
1416         /* if wol enable, do nothing */
1417         if (wol_config & YTPHY_WCR_ENABLE)
1418                 return 0;
1419
1420         return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN);
1421 }
1422
1423 /**
1424  * yt8521_resume() - resume the hardware
1425  * @phydev: a pointer to a &struct phy_device
1426  *
1427  * returns 0 or negative errno code
1428  */
1429 static int yt8521_resume(struct phy_device *phydev)
1430 {
1431         int ret;
1432         int wol_config;
1433
1434         /* disable auto sleep */
1435         ret = ytphy_modify_ext_with_lock(phydev,
1436                                          YT8521_EXTREG_SLEEP_CONTROL1_REG,
1437                                          YT8521_ESC1R_SLEEP_SW, 0);
1438         if (ret < 0)
1439                 return ret;
1440
1441         wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1442         if (wol_config < 0)
1443                 return wol_config;
1444
1445         /* if wol enable, do nothing */
1446         if (wol_config & YTPHY_WCR_ENABLE)
1447                 return 0;
1448
1449         return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0);
1450 }
1451
1452 /**
1453  * yt8521_config_init() - called to initialize the PHY
1454  * @phydev: a pointer to a &struct phy_device
1455  *
1456  * returns 0 or negative errno code
1457  */
1458 static int yt8521_config_init(struct phy_device *phydev)
1459 {
1460         struct device_node *node = phydev->mdio.dev.of_node;
1461         int old_page;
1462         int ret = 0;
1463
1464         old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
1465         if (old_page < 0)
1466                 goto err_restore_page;
1467
1468         /* set rgmii delay mode */
1469         if (phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1470                 ret = ytphy_rgmii_clk_delay_config(phydev);
1471                 if (ret < 0)
1472                         goto err_restore_page;
1473         }
1474
1475         if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
1476                 /* disable auto sleep */
1477                 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
1478                                        YT8521_ESC1R_SLEEP_SW, 0);
1479                 if (ret < 0)
1480                         goto err_restore_page;
1481         }
1482
1483         if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
1484                 /* enable RXC clock when no wire plug */
1485                 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
1486                                        YT8521_CGR_RX_CLK_EN, 0);
1487                 if (ret < 0)
1488                         goto err_restore_page;
1489         }
1490 err_restore_page:
1491         return phy_restore_page(phydev, old_page, ret);
1492 }
1493
1494 static int yt8531_config_init(struct phy_device *phydev)
1495 {
1496         struct device_node *node = phydev->mdio.dev.of_node;
1497         int ret;
1498
1499         ret = ytphy_rgmii_clk_delay_config_with_lock(phydev);
1500         if (ret < 0)
1501                 return ret;
1502
1503         if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
1504                 /* disable auto sleep */
1505                 ret = ytphy_modify_ext_with_lock(phydev,
1506                                                  YT8521_EXTREG_SLEEP_CONTROL1_REG,
1507                                                  YT8521_ESC1R_SLEEP_SW, 0);
1508                 if (ret < 0)
1509                         return ret;
1510         }
1511
1512         if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) {
1513                 /* enable RXC clock when no wire plug */
1514                 ret = ytphy_modify_ext_with_lock(phydev,
1515                                                  YT8521_CLOCK_GATING_REG,
1516                                                  YT8521_CGR_RX_CLK_EN, 0);
1517                 if (ret < 0)
1518                         return ret;
1519         }
1520
1521         return 0;
1522 }
1523
1524 /**
1525  * yt8531_link_change_notify() - Adjust the tx clock direction according to
1526  * the current speed and dts config.
1527  * @phydev: a pointer to a &struct phy_device
1528  *
1529  * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please
1530  * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not
1531  * JH7110.
1532  */
1533 static void yt8531_link_change_notify(struct phy_device *phydev)
1534 {
1535         struct device_node *node = phydev->mdio.dev.of_node;
1536         bool tx_clk_adj_enabled = false;
1537         bool tx_clk_1000_inverted;
1538         bool tx_clk_100_inverted;
1539         bool tx_clk_10_inverted;
1540         u16 val = 0;
1541         int ret;
1542
1543         if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled"))
1544                 tx_clk_adj_enabled = true;
1545
1546         if (!tx_clk_adj_enabled)
1547                 return;
1548
1549         if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted"))
1550                 tx_clk_10_inverted = true;
1551         if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted"))
1552                 tx_clk_100_inverted = true;
1553         if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted"))
1554                 tx_clk_1000_inverted = true;
1555
1556         if (phydev->speed < 0)
1557                 return;
1558
1559         switch (phydev->speed) {
1560         case SPEED_1000:
1561                 if (tx_clk_1000_inverted)
1562                         val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1563                 break;
1564         case SPEED_100:
1565                 if (tx_clk_100_inverted)
1566                         val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1567                 break;
1568         case SPEED_10:
1569                 if (tx_clk_10_inverted)
1570                         val = YT8521_RC1R_TX_CLK_SEL_INVERTED;
1571                 break;
1572         default:
1573                 return;
1574         }
1575
1576         ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG,
1577                                          YT8521_RC1R_TX_CLK_SEL_INVERTED, val);
1578         if (ret < 0)
1579                 phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret);
1580 }
1581
1582 /**
1583  * yt8521_prepare_fiber_features() -  A small helper function that setup
1584  * fiber's features.
1585  * @phydev: a pointer to a &struct phy_device
1586  * @dst: a pointer to store fiber's features
1587  */
1588 static void yt8521_prepare_fiber_features(struct phy_device *phydev,
1589                                           unsigned long *dst)
1590 {
1591         linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst);
1592         linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst);
1593         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst);
1594         linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst);
1595 }
1596
1597 /**
1598  * yt8521_fiber_setup_forced - configures/forces speed from @phydev
1599  * @phydev: target phy_device struct
1600  *
1601  * NOTE:The caller must have taken the MDIO bus lock.
1602  *
1603  * returns 0 or negative errno code
1604  */
1605 static int yt8521_fiber_setup_forced(struct phy_device *phydev)
1606 {
1607         u16 val;
1608         int ret;
1609
1610         if (phydev->speed == SPEED_1000)
1611                 val = YTPHY_MCR_FIBER_1000BX;
1612         else if (phydev->speed == SPEED_100)
1613                 val = YTPHY_MCR_FIBER_100FX;
1614         else
1615                 return -EINVAL;
1616
1617         ret =  __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1618         if (ret < 0)
1619                 return ret;
1620
1621         /* disable Fiber auto sensing */
1622         ret =  ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1623                                 YT8521_LTCR_EN_AUTOSEN, 0);
1624         if (ret < 0)
1625                 return ret;
1626
1627         ret =  ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG,
1628                                 YTPHY_MCR_FIBER_SPEED_MASK, val);
1629         if (ret < 0)
1630                 return ret;
1631
1632         return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1633                                 YT8521_CCR_SW_RST, 0);
1634 }
1635
1636 /**
1637  * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation
1638  * @phydev: target phy_device struct
1639  * @restart: whether aneg restart is requested
1640  *
1641  * NOTE:The caller must have taken the MDIO bus lock.
1642  *
1643  * returns 0 or negative errno code
1644  */
1645 static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
1646 {
1647         int ret;
1648
1649         if (!restart) {
1650                 /* Advertisement hasn't changed, but maybe aneg was never on to
1651                  * begin with?  Or maybe phy was isolated?
1652                  */
1653                 ret = __phy_read(phydev, MII_BMCR);
1654                 if (ret < 0)
1655                         return ret;
1656
1657                 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
1658                         restart = true;
1659         }
1660         /* Enable and Restart Autonegotiation
1661          * Don't isolate the PHY if we're negotiating
1662          */
1663         if (restart)
1664                 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
1665                                     BMCR_ANENABLE | BMCR_ANRESTART);
1666
1667         return 0;
1668 }
1669
1670 /**
1671  * yt8521_fiber_config_aneg - restart auto-negotiation or write
1672  * YTPHY_MISC_CONFIG_REG.
1673  * @phydev: target phy_device struct
1674  *
1675  * NOTE:The caller must have taken the MDIO bus lock.
1676  *
1677  * returns 0 or negative errno code
1678  */
1679 static int yt8521_fiber_config_aneg(struct phy_device *phydev)
1680 {
1681         int err, changed = 0;
1682         int bmcr;
1683         u16 adv;
1684
1685         if (phydev->autoneg != AUTONEG_ENABLE)
1686                 return yt8521_fiber_setup_forced(phydev);
1687
1688         /* enable Fiber auto sensing */
1689         err =  ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1690                                 0, YT8521_LTCR_EN_AUTOSEN);
1691         if (err < 0)
1692                 return err;
1693
1694         err =  ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1695                                 YT8521_CCR_SW_RST, 0);
1696         if (err < 0)
1697                 return err;
1698
1699         bmcr = __phy_read(phydev, MII_BMCR);
1700         if (bmcr < 0)
1701                 return bmcr;
1702
1703         /* When it is coming from fiber forced mode, add bmcr power down
1704          * and power up to let aneg work fine.
1705          */
1706         if (!(bmcr & BMCR_ANENABLE)) {
1707                 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
1708                 usleep_range(1000, 1100);
1709                 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
1710         }
1711
1712         adv = linkmode_adv_to_mii_adv_x(phydev->advertising,
1713                                         ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
1714
1715         /* Setup fiber advertisement */
1716         err = __phy_modify_changed(phydev, MII_ADVERTISE,
1717                                    ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
1718                                    ADVERTISE_1000XPAUSE |
1719                                    ADVERTISE_1000XPSE_ASYM,
1720                                    adv);
1721         if (err < 0)
1722                 return err;
1723
1724         if (err > 0)
1725                 changed = 1;
1726
1727         return ytphy_check_and_restart_aneg(phydev, changed);
1728 }
1729
1730 /**
1731  * ytphy_setup_master_slave
1732  * @phydev: target phy_device struct
1733  *
1734  * NOTE: The caller must have taken the MDIO bus lock.
1735  *
1736  * returns 0 or negative errno code
1737  */
1738 static int ytphy_setup_master_slave(struct phy_device *phydev)
1739 {
1740         u16 ctl = 0;
1741
1742         if (!phydev->is_gigabit_capable)
1743                 return 0;
1744
1745         switch (phydev->master_slave_set) {
1746         case MASTER_SLAVE_CFG_MASTER_PREFERRED:
1747                 ctl |= CTL1000_PREFER_MASTER;
1748                 break;
1749         case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
1750                 break;
1751         case MASTER_SLAVE_CFG_MASTER_FORCE:
1752                 ctl |= CTL1000_AS_MASTER;
1753                 fallthrough;
1754         case MASTER_SLAVE_CFG_SLAVE_FORCE:
1755                 ctl |= CTL1000_ENABLE_MASTER;
1756                 break;
1757         case MASTER_SLAVE_CFG_UNKNOWN:
1758         case MASTER_SLAVE_CFG_UNSUPPORTED:
1759                 return 0;
1760         default:
1761                 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1762                 return -EOPNOTSUPP;
1763         }
1764
1765         return __phy_modify_changed(phydev, MII_CTRL1000,
1766                                     (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
1767                                     CTL1000_PREFER_MASTER), ctl);
1768 }
1769
1770 /**
1771  * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters
1772  * @phydev: target phy_device struct
1773  *
1774  * NOTE: Writes MII_ADVERTISE with the appropriate values,
1775  * after sanitizing the values to make sure we only advertise
1776  * what is supported.  Returns < 0 on error, 0 if the PHY's advertisement
1777  * hasn't changed, and > 0 if it has changed.
1778  * The caller must have taken the MDIO bus lock.
1779  *
1780  * returns 0 or negative errno code
1781  */
1782 static int ytphy_utp_config_advert(struct phy_device *phydev)
1783 {
1784         int err, bmsr, changed = 0;
1785         u32 adv;
1786
1787         /* Only allow advertising what this PHY supports */
1788         linkmode_and(phydev->advertising, phydev->advertising,
1789                      phydev->supported);
1790
1791         adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
1792
1793         /* Setup standard advertisement */
1794         err = __phy_modify_changed(phydev, MII_ADVERTISE,
1795                                    ADVERTISE_ALL | ADVERTISE_100BASE4 |
1796                                    ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
1797                                    adv);
1798         if (err < 0)
1799                 return err;
1800         if (err > 0)
1801                 changed = 1;
1802
1803         bmsr = __phy_read(phydev, MII_BMSR);
1804         if (bmsr < 0)
1805                 return bmsr;
1806
1807         /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
1808          * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
1809          * logical 1.
1810          */
1811         if (!(bmsr & BMSR_ESTATEN))
1812                 return changed;
1813
1814         adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1815
1816         err = __phy_modify_changed(phydev, MII_CTRL1000,
1817                                    ADVERTISE_1000FULL | ADVERTISE_1000HALF,
1818                                    adv);
1819         if (err < 0)
1820                 return err;
1821         if (err > 0)
1822                 changed = 1;
1823
1824         return changed;
1825 }
1826
1827 /**
1828  * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR
1829  * @phydev: target phy_device struct
1830  * @changed: whether autoneg is requested
1831  *
1832  * NOTE: If auto-negotiation is enabled, we configure the
1833  * advertising, and then restart auto-negotiation.  If it is not
1834  * enabled, then we write the BMCR.
1835  * The caller must have taken the MDIO bus lock.
1836  *
1837  * returns 0 or negative errno code
1838  */
1839 static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed)
1840 {
1841         int err;
1842         u16 ctl;
1843
1844         err = ytphy_setup_master_slave(phydev);
1845         if (err < 0)
1846                 return err;
1847         else if (err)
1848                 changed = true;
1849
1850         if (phydev->autoneg != AUTONEG_ENABLE) {
1851                 /* configures/forces speed/duplex from @phydev */
1852
1853                 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
1854
1855                 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK |
1856                                     BMCR_ISOLATE | BMCR_PDOWN), ctl);
1857         }
1858
1859         err = ytphy_utp_config_advert(phydev);
1860         if (err < 0) /* error */
1861                 return err;
1862         else if (err)
1863                 changed = true;
1864
1865         return ytphy_check_and_restart_aneg(phydev, changed);
1866 }
1867
1868 /**
1869  * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg
1870  * of one page
1871  * @phydev: a pointer to a &struct phy_device
1872  * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1873  * operate.
1874  *
1875  * returns 0 or negative errno code
1876  */
1877 static int yt8521_config_aneg_paged(struct phy_device *phydev, int page)
1878 {
1879         __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported);
1880         struct yt8521_priv *priv = phydev->priv;
1881         int old_page;
1882         int ret = 0;
1883
1884         page &= YT8521_RSSR_SPACE_MASK;
1885
1886         old_page = phy_select_page(phydev, page);
1887         if (old_page < 0)
1888                 goto err_restore_page;
1889
1890         /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
1891          * phydev->advertising should be updated.
1892          */
1893         if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
1894                 linkmode_zero(fiber_supported);
1895                 yt8521_prepare_fiber_features(phydev, fiber_supported);
1896
1897                 /* prepare fiber_supported, then setup advertising. */
1898                 if (page == YT8521_RSSR_FIBER_SPACE) {
1899                         linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
1900                                          fiber_supported);
1901                         linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
1902                                          fiber_supported);
1903                         linkmode_and(phydev->advertising,
1904                                      priv->combo_advertising, fiber_supported);
1905                 } else {
1906                         /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */
1907                         linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1908                                            fiber_supported);
1909                         linkmode_andnot(phydev->advertising,
1910                                         priv->combo_advertising,
1911                                         fiber_supported);
1912                 }
1913         }
1914
1915         if (page == YT8521_RSSR_FIBER_SPACE)
1916                 ret = yt8521_fiber_config_aneg(phydev);
1917         else
1918                 ret = ytphy_utp_config_aneg(phydev, false);
1919
1920 err_restore_page:
1921         return phy_restore_page(phydev, old_page, ret);
1922 }
1923
1924 /**
1925  * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged
1926  * @phydev: a pointer to a &struct phy_device
1927  *
1928  * returns 0 or negative errno code
1929  */
1930 static int yt8521_config_aneg(struct phy_device *phydev)
1931 {
1932         struct yt8521_priv *priv = phydev->priv;
1933         int ret;
1934
1935         if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1936                 ret = yt8521_config_aneg_paged(phydev, priv->reg_page);
1937                 if (ret < 0)
1938                         return ret;
1939         } else {
1940                 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
1941                  * phydev->advertising need to be saved at first run.
1942                  * Because it contains the advertising which supported by both
1943                  * mac and yt8521(utp and fiber).
1944                  */
1945                 if (linkmode_empty(priv->combo_advertising)) {
1946                         linkmode_copy(priv->combo_advertising,
1947                                       phydev->advertising);
1948                 }
1949
1950                 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE);
1951                 if (ret < 0)
1952                         return ret;
1953
1954                 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE);
1955                 if (ret < 0)
1956                         return ret;
1957
1958                 /* we don't known which will be link, so restore
1959                  * phydev->advertising as default value.
1960                  */
1961                 linkmode_copy(phydev->advertising, priv->combo_advertising);
1962         }
1963         return 0;
1964 }
1965
1966 /**
1967  * yt8521_aneg_done_paged() - determines the auto negotiation result of one
1968  * page.
1969  * @phydev: a pointer to a &struct phy_device
1970  * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1971  * operate.
1972  *
1973  * returns 0(no link)or 1(fiber or utp link) or negative errno code
1974  */
1975 static int yt8521_aneg_done_paged(struct phy_device *phydev, int page)
1976 {
1977         int old_page;
1978         int ret = 0;
1979         int link;
1980
1981         old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
1982         if (old_page < 0)
1983                 goto err_restore_page;
1984
1985         ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
1986         if (ret < 0)
1987                 goto err_restore_page;
1988
1989         link = !!(ret & YTPHY_SSR_LINK);
1990         ret = link;
1991
1992 err_restore_page:
1993         return phy_restore_page(phydev, old_page, ret);
1994 }
1995
1996 /**
1997  * yt8521_aneg_done() - determines the auto negotiation result
1998  * @phydev: a pointer to a &struct phy_device
1999  *
2000  * returns 0(no link)or 1(fiber or utp link) or negative errno code
2001  */
2002 static int yt8521_aneg_done(struct phy_device *phydev)
2003 {
2004         struct yt8521_priv *priv = phydev->priv;
2005         int link_fiber = 0;
2006         int link_utp;
2007         int link;
2008
2009         if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
2010                 link = yt8521_aneg_done_paged(phydev, priv->reg_page);
2011         } else {
2012                 link_utp = yt8521_aneg_done_paged(phydev,
2013                                                   YT8521_RSSR_UTP_SPACE);
2014                 if (link_utp < 0)
2015                         return link_utp;
2016
2017                 if (!link_utp) {
2018                         link_fiber = yt8521_aneg_done_paged(phydev,
2019                                                             YT8521_RSSR_FIBER_SPACE);
2020                         if (link_fiber < 0)
2021                                 return link_fiber;
2022                 }
2023                 link = link_fiber || link_utp;
2024                 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n",
2025                             __func__, link_fiber, link_utp);
2026         }
2027
2028         return link;
2029 }
2030
2031 /**
2032  * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers
2033  * @phydev: target phy_device struct
2034  *
2035  * NOTE: Reads the PHY's abilities and populates
2036  * phydev->supported accordingly.
2037  * The caller must have taken the MDIO bus lock.
2038  *
2039  * returns 0 or negative errno code
2040  */
2041 static int ytphy_utp_read_abilities(struct phy_device *phydev)
2042 {
2043         int val;
2044
2045         linkmode_set_bit_array(phy_basic_ports_array,
2046                                ARRAY_SIZE(phy_basic_ports_array),
2047                                phydev->supported);
2048
2049         val = __phy_read(phydev, MII_BMSR);
2050         if (val < 0)
2051                 return val;
2052
2053         linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
2054                          val & BMSR_ANEGCAPABLE);
2055
2056         linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
2057                          val & BMSR_100FULL);
2058         linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
2059                          val & BMSR_100HALF);
2060         linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
2061                          val & BMSR_10FULL);
2062         linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
2063                          val & BMSR_10HALF);
2064
2065         if (val & BMSR_ESTATEN) {
2066                 val = __phy_read(phydev, MII_ESTATUS);
2067                 if (val < 0)
2068                         return val;
2069
2070                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2071                                  phydev->supported, val & ESTATUS_1000_TFULL);
2072                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
2073                                  phydev->supported, val & ESTATUS_1000_THALF);
2074                 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2075                                  phydev->supported, val & ESTATUS_1000_XFULL);
2076         }
2077
2078         return 0;
2079 }
2080
2081 /**
2082  * yt8521_get_features_paged() -  read supported link modes for one page
2083  * @phydev: a pointer to a &struct phy_device
2084  * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
2085  * operate.
2086  *
2087  * returns 0 or negative errno code
2088  */
2089 static int yt8521_get_features_paged(struct phy_device *phydev, int page)
2090 {
2091         int old_page;
2092         int ret = 0;
2093
2094         page &= YT8521_RSSR_SPACE_MASK;
2095         old_page = phy_select_page(phydev, page);
2096         if (old_page < 0)
2097                 goto err_restore_page;
2098
2099         if (page == YT8521_RSSR_FIBER_SPACE) {
2100                 linkmode_zero(phydev->supported);
2101                 yt8521_prepare_fiber_features(phydev, phydev->supported);
2102         } else {
2103                 ret = ytphy_utp_read_abilities(phydev);
2104                 if (ret < 0)
2105                         goto err_restore_page;
2106         }
2107
2108 err_restore_page:
2109         return phy_restore_page(phydev, old_page, ret);
2110 }
2111
2112 /**
2113  * yt8521_get_features - switch reg space then call yt8521_get_features_paged
2114  * @phydev: target phy_device struct
2115  *
2116  * returns 0 or negative errno code
2117  */
2118 static int yt8521_get_features(struct phy_device *phydev)
2119 {
2120         struct yt8521_priv *priv = phydev->priv;
2121         int ret;
2122
2123         if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
2124                 ret = yt8521_get_features_paged(phydev, priv->reg_page);
2125         } else {
2126                 ret = yt8521_get_features_paged(phydev,
2127                                                 YT8521_RSSR_UTP_SPACE);
2128                 if (ret < 0)
2129                         return ret;
2130
2131                 /* add fiber's features to phydev->supported */
2132                 yt8521_prepare_fiber_features(phydev, phydev->supported);
2133         }
2134         return ret;
2135 }
2136
2137 static struct phy_driver motorcomm_phy_drvs[] = {
2138         {
2139                 PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
2140                 .name           = "YT8511 Gigabit Ethernet",
2141                 .config_init    = yt8511_config_init,
2142                 .suspend        = genphy_suspend,
2143                 .resume         = genphy_resume,
2144                 .read_page      = yt8511_read_page,
2145                 .write_page     = yt8511_write_page,
2146         },
2147         {
2148                 PHY_ID_MATCH_EXACT(PHY_ID_YT8521),
2149                 .name           = "YT8521 Gigabit Ethernet",
2150                 .get_features   = yt8521_get_features,
2151                 .probe          = yt8521_probe,
2152                 .read_page      = yt8521_read_page,
2153                 .write_page     = yt8521_write_page,
2154                 .get_wol        = ytphy_get_wol,
2155                 .set_wol        = ytphy_set_wol,
2156                 .config_aneg    = yt8521_config_aneg,
2157                 .aneg_done      = yt8521_aneg_done,
2158                 .config_init    = yt8521_config_init,
2159                 .read_status    = yt8521_read_status,
2160                 .soft_reset     = yt8521_soft_reset,
2161                 .suspend        = yt8521_suspend,
2162                 .resume         = yt8521_resume,
2163         },
2164         {
2165                 PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
2166                 .name           = "YT8531 Gigabit Ethernet",
2167                 .probe          = yt8531_probe,
2168                 .config_init    = yt8531_config_init,
2169                 .suspend        = genphy_suspend,
2170                 .resume         = genphy_resume,
2171                 .get_wol        = ytphy_get_wol,
2172                 .set_wol        = yt8531_set_wol,
2173                 .link_change_notify = yt8531_link_change_notify,
2174         },
2175         {
2176                 PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
2177                 .name           = "YT8531S Gigabit Ethernet",
2178                 .get_features   = yt8521_get_features,
2179                 .probe          = yt8521_probe,
2180                 .read_page      = yt8521_read_page,
2181                 .write_page     = yt8521_write_page,
2182                 .get_wol        = ytphy_get_wol,
2183                 .set_wol        = ytphy_set_wol,
2184                 .config_aneg    = yt8521_config_aneg,
2185                 .aneg_done      = yt8521_aneg_done,
2186                 .config_init    = yt8521_config_init,
2187                 .read_status    = yt8521_read_status,
2188                 .soft_reset     = yt8521_soft_reset,
2189                 .suspend        = yt8521_suspend,
2190                 .resume         = yt8521_resume,
2191         },
2192 };
2193
2194 module_phy_driver(motorcomm_phy_drvs);
2195
2196 MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S PHY driver");
2197 MODULE_AUTHOR("Peter Geis");
2198 MODULE_AUTHOR("Frank");
2199 MODULE_LICENSE("GPL");
2200
2201 static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
2202         { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
2203         { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
2204         { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
2205         { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
2206         { /* sentinel */ }
2207 };
2208
2209 MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);