1 // SPDX-License-Identifier: GPL-2.0+
3 * Motorcomm 8511/8521 PHY driver.
5 * Author: Peter Geis <pgwipeout@gmail.com>
6 * Author: Frank <Frank.Sae@motor-comm.com>
9 #include <linux/etherdevice.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/phy.h>
14 #define PHY_ID_YT8511 0x0000010a
15 #define PHY_ID_YT8521 0x0000011A
17 /* YT8521 Register Overview
18 * UTP Register space | FIBER Register space
19 * ------------------------------------------------------------
20 * | UTP MII | FIBER MII |
22 * | UTP Extended | FIBER Extended |
23 * ------------------------------------------------------------
25 * ------------------------------------------------------------
28 /* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */
30 /* Specific Function Control Register */
31 #define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10
33 /* 2b00 Manual MDI configuration
34 * 2b01 Manual MDIX configuration
36 * 2b11 Enable automatic crossover for all modes *default*
38 #define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5))
39 #define YTPHY_SFCR_CROSSOVER_EN BIT(3)
40 #define YTPHY_SFCR_SQE_TEST_EN BIT(2)
41 #define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1)
42 #define YTPHY_SFCR_JABBER_DIS BIT(0)
44 /* Specific Status Register */
45 #define YTPHY_SPECIFIC_STATUS_REG 0x11
46 #define YTPHY_SSR_SPEED_MODE_OFFSET 14
48 #define YTPHY_SSR_SPEED_MODE_MASK (BIT(15) | BIT(14))
49 #define YTPHY_SSR_SPEED_10M 0x0
50 #define YTPHY_SSR_SPEED_100M 0x1
51 #define YTPHY_SSR_SPEED_1000M 0x2
52 #define YTPHY_SSR_DUPLEX_OFFSET 13
53 #define YTPHY_SSR_DUPLEX BIT(13)
54 #define YTPHY_SSR_PAGE_RECEIVED BIT(12)
55 #define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11)
56 #define YTPHY_SSR_LINK BIT(10)
57 #define YTPHY_SSR_MDIX_CROSSOVER BIT(6)
58 #define YTPHY_SSR_DOWNGRADE BIT(5)
59 #define YTPHY_SSR_TRANSMIT_PAUSE BIT(3)
60 #define YTPHY_SSR_RECEIVE_PAUSE BIT(2)
61 #define YTPHY_SSR_POLARITY BIT(1)
62 #define YTPHY_SSR_JABBER BIT(0)
64 /* Interrupt enable Register */
65 #define YTPHY_INTERRUPT_ENABLE_REG 0x12
66 #define YTPHY_IER_WOL BIT(6)
68 /* Interrupt Status Register */
69 #define YTPHY_INTERRUPT_STATUS_REG 0x13
70 #define YTPHY_ISR_AUTONEG_ERR BIT(15)
71 #define YTPHY_ISR_SPEED_CHANGED BIT(14)
72 #define YTPHY_ISR_DUPLEX_CHANGED BIT(13)
73 #define YTPHY_ISR_PAGE_RECEIVED BIT(12)
74 #define YTPHY_ISR_LINK_FAILED BIT(11)
75 #define YTPHY_ISR_LINK_SUCCESSED BIT(10)
76 #define YTPHY_ISR_WOL BIT(6)
77 #define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5)
78 #define YTPHY_ISR_SERDES_LINK_FAILED BIT(3)
79 #define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2)
80 #define YTPHY_ISR_POLARITY_CHANGED BIT(1)
81 #define YTPHY_ISR_JABBER_HAPPENED BIT(0)
83 /* Speed Auto Downgrade Control Register */
84 #define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14
85 #define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5)
87 /* If these bits are set to 3, the PHY attempts five times ( 3(set value) +
88 * additional 2) before downgrading, default 0x3
90 #define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2)
92 /* Rx Error Counter Register */
93 #define YTPHY_RX_ERROR_COUNTER_REG 0x15
95 /* Extended Register's Address Offset Register */
96 #define YTPHY_PAGE_SELECT 0x1E
98 /* Extended Register's Data Register */
99 #define YTPHY_PAGE_DATA 0x1F
101 /* FIBER Auto-Negotiation link partner ability */
102 #define YTPHY_FLPA_PAUSE (0x3 << 7)
103 #define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7)
105 #define YT8511_PAGE_SELECT 0x1e
106 #define YT8511_PAGE 0x1f
107 #define YT8511_EXT_CLK_GATE 0x0c
108 #define YT8511_EXT_DELAY_DRIVE 0x0d
109 #define YT8511_EXT_SLEEP_CTRL 0x27
112 * 2b01 25m from xtl *default*
116 #define YT8511_CLK_125M (BIT(2) | BIT(1))
117 #define YT8511_PLLON_SLP BIT(14)
119 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
120 #define YT8511_DELAY_RX BIT(0)
122 /* TX Gig-E Delay is bits 7:4, default 0x5
123 * TX Fast-E Delay is bits 15:12, default 0xf
124 * Delay = 150ps * N - 250ps
125 * On = 2000ps, off = 50ps
127 #define YT8511_DELAY_GE_TX_EN (0xf << 4)
128 #define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
129 #define YT8511_DELAY_FE_TX_EN (0xf << 12)
130 #define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
132 /* Extended register is different from MMD Register and MII Register.
133 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to
134 * operate extended register.
135 * Extended Register start
138 /* Phy gmii clock gating Register */
139 #define YT8521_CLOCK_GATING_REG 0xC
140 #define YT8521_CGR_RX_CLK_EN BIT(12)
142 #define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27
143 #define YT8521_ESC1R_SLEEP_SW BIT(15)
144 #define YT8521_ESC1R_PLLON_SLP BIT(14)
146 /* Phy fiber Link timer cfg2 Register */
147 #define YT8521_LINK_TIMER_CFG2_REG 0xA5
148 #define YT8521_LTCR_EN_AUTOSEN BIT(15)
150 /* 0xA000, 0xA001, 0xA003 ,and 0xA006 ~ 0xA00A are common ext registers
151 * of yt8521 phy. There is no need to switch reg space when operating these
155 #define YT8521_REG_SPACE_SELECT_REG 0xA000
156 #define YT8521_RSSR_SPACE_MASK BIT(1)
157 #define YT8521_RSSR_FIBER_SPACE (0x1 << 1)
158 #define YT8521_RSSR_UTP_SPACE (0x0 << 1)
159 #define YT8521_RSSR_TO_BE_ARBITRATED (0xFF)
161 #define YT8521_CHIP_CONFIG_REG 0xA001
162 #define YT8521_CCR_SW_RST BIT(15)
163 #define YT8521_CCR_RXC_DLY_EN BIT(8)
165 #define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0))
166 #define YT8521_CCR_MODE_UTP_TO_RGMII 0
167 #define YT8521_CCR_MODE_FIBER_TO_RGMII 1
168 #define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2
169 #define YT8521_CCR_MODE_UTP_TO_SGMII 3
170 #define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4
171 #define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5
172 #define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6
173 #define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7
175 /* 3 phy polling modes,poll mode combines utp and fiber mode*/
176 #define YT8521_MODE_FIBER 0x1
177 #define YT8521_MODE_UTP 0x2
178 #define YT8521_MODE_POLL 0x3
180 #define YT8521_RGMII_CONFIG1_REG 0xA003
182 /* TX Gig-E Delay is bits 3:0, default 0x1
183 * TX Fast-E Delay is bits 7:4, default 0xf
184 * RX Delay is bits 13:10, default 0x0
186 * On = 2250ps, off = 0ps
188 #define YT8521_RC1R_RX_DELAY_MASK (0xF << 10)
189 #define YT8521_RC1R_RX_DELAY_EN (0xF << 10)
190 #define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10)
191 #define YT8521_RC1R_FE_TX_DELAY_MASK (0xF << 4)
192 #define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4)
193 #define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4)
194 #define YT8521_RC1R_GE_TX_DELAY_MASK (0xF << 0)
195 #define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0)
196 #define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0)
198 #define YTPHY_MISC_CONFIG_REG 0xA006
199 #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0)
200 #define YTPHY_MCR_FIBER_1000BX (0x1 << 0)
201 #define YTPHY_MCR_FIBER_100FX (0x0 << 0)
203 /* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */
204 #define YTPHY_WOL_MACADDR2_REG 0xA007
205 #define YTPHY_WOL_MACADDR1_REG 0xA008
206 #define YTPHY_WOL_MACADDR0_REG 0xA009
208 #define YTPHY_WOL_CONFIG_REG 0xA00A
209 #define YTPHY_WCR_INTR_SEL BIT(6)
210 #define YTPHY_WCR_ENABLE BIT(3)
213 * 2b01 168ms *default*
217 #define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1))
218 #define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1))
220 /* 1b0 Interrupt and WOL events is level triggered and active LOW *default*
221 * 1b1 Interrupt and WOL events is pulse triggered and active LOW
223 #define YTPHY_WCR_TYPE_PULSE BIT(0)
225 /* Extended Register end */
228 /* combo_advertising is used for case of YT8521 in combo mode,
229 * this means that yt8521 may work in utp or fiber mode which depends
230 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED).
232 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising);
234 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/
236 u8 strap_mode; /* 8 working modes */
237 /* current reg page of yt8521 phy:
238 * YT8521_RSSR_UTP_SPACE
239 * YT8521_RSSR_FIBER_SPACE
240 * YT8521_RSSR_TO_BE_ARBITRATED
246 * ytphy_read_ext() - read a PHY's extended register
247 * @phydev: a pointer to a &struct phy_device
248 * @regnum: register number to read
250 * NOTE:The caller must have taken the MDIO bus lock.
252 * returns the value of regnum reg or negative error code
254 static int ytphy_read_ext(struct phy_device *phydev, u16 regnum)
258 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
262 return __phy_read(phydev, YTPHY_PAGE_DATA);
266 * ytphy_read_ext_with_lock() - read a PHY's extended register
267 * @phydev: a pointer to a &struct phy_device
268 * @regnum: register number to read
270 * returns the value of regnum reg or negative error code
272 static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum)
276 phy_lock_mdio_bus(phydev);
277 ret = ytphy_read_ext(phydev, regnum);
278 phy_unlock_mdio_bus(phydev);
284 * ytphy_write_ext() - write a PHY's extended register
285 * @phydev: a pointer to a &struct phy_device
286 * @regnum: register number to write
287 * @val: value to write to @regnum
289 * NOTE:The caller must have taken the MDIO bus lock.
291 * returns 0 or negative error code
293 static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val)
297 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
301 return __phy_write(phydev, YTPHY_PAGE_DATA, val);
305 * ytphy_write_ext_with_lock() - write a PHY's extended register
306 * @phydev: a pointer to a &struct phy_device
307 * @regnum: register number to write
308 * @val: value to write to @regnum
310 * returns 0 or negative error code
312 static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum,
317 phy_lock_mdio_bus(phydev);
318 ret = ytphy_write_ext(phydev, regnum, val);
319 phy_unlock_mdio_bus(phydev);
325 * ytphy_modify_ext() - bits modify a PHY's extended register
326 * @phydev: a pointer to a &struct phy_device
327 * @regnum: register number to write
328 * @mask: bit mask of bits to clear
329 * @set: bit mask of bits to set
331 * NOTE: Convenience function which allows a PHY's extended register to be
332 * modified as new register value = (old register value & ~mask) | set.
333 * The caller must have taken the MDIO bus lock.
335 * returns 0 or negative error code
337 static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
342 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
346 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set);
350 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register
351 * @phydev: a pointer to a &struct phy_device
352 * @regnum: register number to write
353 * @mask: bit mask of bits to clear
354 * @set: bit mask of bits to set
356 * NOTE: Convenience function which allows a PHY's extended register to be
357 * modified as new register value = (old register value & ~mask) | set.
359 * returns 0 or negative error code
361 static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum,
366 phy_lock_mdio_bus(phydev);
367 ret = ytphy_modify_ext(phydev, regnum, mask, set);
368 phy_unlock_mdio_bus(phydev);
374 * ytphy_get_wol() - report whether wake-on-lan is enabled
375 * @phydev: a pointer to a &struct phy_device
376 * @wol: a pointer to a &struct ethtool_wolinfo
378 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg.
380 static void ytphy_get_wol(struct phy_device *phydev,
381 struct ethtool_wolinfo *wol)
385 wol->supported = WAKE_MAGIC;
388 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
392 if (wol_config & YTPHY_WCR_ENABLE)
393 wol->wolopts |= WAKE_MAGIC;
397 * ytphy_set_wol() - turn wake-on-lan on or off
398 * @phydev: a pointer to a &struct phy_device
399 * @wol: a pointer to a &struct ethtool_wolinfo
401 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG
402 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The
403 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register.
405 * returns 0 or negative errno code
407 static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
409 struct net_device *p_attached_dev;
410 const u16 mac_addr_reg[] = {
411 YTPHY_WOL_MACADDR2_REG,
412 YTPHY_WOL_MACADDR1_REG,
413 YTPHY_WOL_MACADDR0_REG,
422 if (wol->wolopts & WAKE_MAGIC) {
423 p_attached_dev = phydev->attached_dev;
427 mac_addr = (const u8 *)p_attached_dev->dev_addr;
428 if (!is_valid_ether_addr(mac_addr))
431 /* lock mdio bus then switch to utp reg space */
432 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
434 goto err_restore_page;
436 /* Store the device address for the magic packet */
437 for (i = 0; i < 3; i++) {
438 ret = ytphy_write_ext(phydev, mac_addr_reg[i],
439 ((mac_addr[i * 2] << 8)) |
440 (mac_addr[i * 2 + 1]));
442 goto err_restore_page;
445 /* Enable WOL feature */
446 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
447 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
448 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
449 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val);
451 goto err_restore_page;
453 /* Enable WOL interrupt */
454 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
457 goto err_restore_page;
460 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
462 goto err_restore_page;
464 /* Disable WOL feature */
465 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
466 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0);
468 /* Disable WOL interrupt */
469 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
472 goto err_restore_page;
476 return phy_restore_page(phydev, old_page, ret);
479 static int yt8511_read_page(struct phy_device *phydev)
481 return __phy_read(phydev, YT8511_PAGE_SELECT);
484 static int yt8511_write_page(struct phy_device *phydev, int page)
486 return __phy_write(phydev, YT8511_PAGE_SELECT, page);
489 static int yt8511_config_init(struct phy_device *phydev)
491 int oldpage, ret = 0;
494 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
496 goto err_restore_page;
498 /* set rgmii delay mode */
499 switch (phydev->interface) {
500 case PHY_INTERFACE_MODE_RGMII:
501 ge = YT8511_DELAY_GE_TX_DIS;
502 fe = YT8511_DELAY_FE_TX_DIS;
504 case PHY_INTERFACE_MODE_RGMII_RXID:
505 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
506 fe = YT8511_DELAY_FE_TX_DIS;
508 case PHY_INTERFACE_MODE_RGMII_TXID:
509 ge = YT8511_DELAY_GE_TX_EN;
510 fe = YT8511_DELAY_FE_TX_EN;
512 case PHY_INTERFACE_MODE_RGMII_ID:
513 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
514 fe = YT8511_DELAY_FE_TX_EN;
516 default: /* do not support other modes */
518 goto err_restore_page;
521 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
523 goto err_restore_page;
525 /* set clock mode to 125mhz */
526 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
528 goto err_restore_page;
530 /* fast ethernet delay is in a separate page */
531 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
533 goto err_restore_page;
535 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
537 goto err_restore_page;
539 /* leave pll enabled in sleep */
540 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
542 goto err_restore_page;
544 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
546 goto err_restore_page;
549 return phy_restore_page(phydev, oldpage, ret);
553 * yt8521_read_page() - read reg page
554 * @phydev: a pointer to a &struct phy_device
556 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/
557 * YT8521_RSSR_UTP_SPACE) or negative errno code
559 static int yt8521_read_page(struct phy_device *phydev)
563 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG);
567 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
568 return YT8521_RSSR_FIBER_SPACE;
570 return YT8521_RSSR_UTP_SPACE;
574 * yt8521_write_page() - write reg page
575 * @phydev: a pointer to a &struct phy_device
576 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write.
578 * returns 0 or negative errno code
580 static int yt8521_write_page(struct phy_device *phydev, int page)
582 int mask = YT8521_RSSR_SPACE_MASK;
585 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
586 set = YT8521_RSSR_FIBER_SPACE;
588 set = YT8521_RSSR_UTP_SPACE;
590 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set);
594 * yt8521_probe() - read chip config then set suitable polling_mode
595 * @phydev: a pointer to a &struct phy_device
597 * returns 0 or negative errno code
599 static int yt8521_probe(struct phy_device *phydev)
601 struct device *dev = &phydev->mdio.dev;
602 struct yt8521_priv *priv;
606 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
612 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
616 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK;
617 switch (priv->strap_mode) {
618 case YT8521_CCR_MODE_FIBER_TO_RGMII:
619 case YT8521_CCR_MODE_SGPHY_TO_RGMAC:
620 case YT8521_CCR_MODE_SGMAC_TO_RGPHY:
621 priv->polling_mode = YT8521_MODE_FIBER;
622 priv->reg_page = YT8521_RSSR_FIBER_SPACE;
623 phydev->port = PORT_FIBRE;
625 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII:
626 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO:
627 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE:
628 priv->polling_mode = YT8521_MODE_POLL;
629 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
630 phydev->port = PORT_NONE;
632 case YT8521_CCR_MODE_UTP_TO_SGMII:
633 case YT8521_CCR_MODE_UTP_TO_RGMII:
634 priv->polling_mode = YT8521_MODE_UTP;
635 priv->reg_page = YT8521_RSSR_UTP_SPACE;
636 phydev->port = PORT_TP;
639 /* set default reg space */
640 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
641 ret = ytphy_write_ext_with_lock(phydev,
642 YT8521_REG_SPACE_SELECT_REG,
652 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
653 * @phydev: a pointer to a &struct phy_device
655 * NOTE:The caller must have taken the MDIO bus lock.
657 * returns 0 or negative errno code
659 static int ytphy_utp_read_lpa(struct phy_device *phydev)
663 if (phydev->autoneg == AUTONEG_ENABLE) {
664 if (!phydev->autoneg_complete) {
665 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
667 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
671 if (phydev->is_gigabit_capable) {
672 lpagb = __phy_read(phydev, MII_STAT1000);
676 if (lpagb & LPA_1000MSFAIL) {
677 int adv = __phy_read(phydev, MII_CTRL1000);
682 if (adv & CTL1000_ENABLE_MASTER)
683 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
685 phydev_err(phydev, "Master/Slave resolution failed\n");
689 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
693 lpa = __phy_read(phydev, MII_LPA);
697 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
699 linkmode_zero(phydev->lp_advertising);
706 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber
707 * mode, adjust speed and duplex.
708 * @phydev: a pointer to a &struct phy_device
709 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG
710 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode)
712 * NOTE:The caller must have taken the MDIO bus lock.
716 static int yt8521_adjust_status(struct phy_device *phydev, int status,
719 int speed_mode, duplex;
725 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET;
727 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */
729 speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >>
730 YTPHY_SSR_SPEED_MODE_OFFSET;
732 switch (speed_mode) {
733 case YTPHY_SSR_SPEED_10M:
737 /* for fiber, it will never run here, default to
740 speed = SPEED_UNKNOWN;
742 case YTPHY_SSR_SPEED_100M:
745 case YTPHY_SSR_SPEED_1000M:
749 speed = SPEED_UNKNOWN;
753 phydev->speed = speed;
754 phydev->duplex = duplex;
757 err = ytphy_utp_read_lpa(phydev);
761 phy_resolve_aneg_pause(phydev);
763 lpa = __phy_read(phydev, MII_LPA);
767 /* only support 1000baseX Full */
768 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
769 phydev->lp_advertising, lpa & LPA_1000XFULL);
771 if (!(lpa & YTPHY_FLPA_PAUSE)) {
773 phydev->asym_pause = 0;
774 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) {
776 phydev->asym_pause = 1;
779 phydev->asym_pause = 0;
787 * yt8521_read_status_paged() - determines the speed and duplex of one page
788 * @phydev: a pointer to a &struct phy_device
789 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
792 * returns 1 (utp or fiber link),0 (no link) or negative errno code
794 static int yt8521_read_status_paged(struct phy_device *phydev, int page)
803 linkmode_zero(phydev->lp_advertising);
804 phydev->duplex = DUPLEX_UNKNOWN;
805 phydev->speed = SPEED_UNKNOWN;
806 phydev->asym_pause = 0;
809 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber
810 * respectively. but for utp/fiber combo mode, reg space should be
811 * arbitrated based on media priority. by default, utp takes
812 * priority. reg space should be properly set before read
813 * YTPHY_SPECIFIC_STATUS_REG.
816 page &= YT8521_RSSR_SPACE_MASK;
817 old_page = phy_select_page(phydev, page);
819 goto err_restore_page;
821 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex
822 * of the PHY is actually using.
824 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
826 goto err_restore_page;
829 link = !!(status & YTPHY_SSR_LINK);
831 /* When PHY is in fiber mode, speed transferred from 1000Mbps to
832 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so
833 * we need check MII_BMSR to identify such case.
835 if (page == YT8521_RSSR_FIBER_SPACE) {
836 ret = __phy_read(phydev, MII_BMSR);
838 goto err_restore_page;
840 fiber_latch_val = ret;
841 ret = __phy_read(phydev, MII_BMSR);
843 goto err_restore_page;
845 fiber_curr_val = ret;
846 if (link && fiber_latch_val != fiber_curr_val) {
849 "%s, fiber link down detect, latch = %04x, curr = %04x\n",
850 __func__, fiber_latch_val, fiber_curr_val);
853 /* Read autonegotiation status */
854 ret = __phy_read(phydev, MII_BMSR);
856 goto err_restore_page;
858 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0;
862 if (page == YT8521_RSSR_UTP_SPACE)
863 yt8521_adjust_status(phydev, status, true);
865 yt8521_adjust_status(phydev, status, false);
867 return phy_restore_page(phydev, old_page, link);
870 return phy_restore_page(phydev, old_page, ret);
874 * yt8521_read_status() - determines the negotiated speed and duplex
875 * @phydev: a pointer to a &struct phy_device
877 * returns 0 or negative errno code
879 static int yt8521_read_status(struct phy_device *phydev)
881 struct yt8521_priv *priv = phydev->priv;
887 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
888 link = yt8521_read_status_paged(phydev, priv->reg_page);
892 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is
893 * needed. by default, utp is higher priority.
896 link_utp = yt8521_read_status_paged(phydev,
897 YT8521_RSSR_UTP_SPACE);
902 link_fiber = yt8521_read_status_paged(phydev,
903 YT8521_RSSR_FIBER_SPACE);
908 link = link_utp || link_fiber;
912 if (phydev->link == 0) {
913 /* arbitrate reg space based on linkup media type. */
914 if (priv->polling_mode == YT8521_MODE_POLL &&
915 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
918 YT8521_RSSR_FIBER_SPACE;
920 priv->reg_page = YT8521_RSSR_UTP_SPACE;
922 ret = ytphy_write_ext_with_lock(phydev,
923 YT8521_REG_SPACE_SELECT_REG,
928 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP;
930 phydev_info(phydev, "%s, link up, media: %s\n",
932 (phydev->port == PORT_TP) ?
938 if (phydev->link == 1) {
939 phydev_info(phydev, "%s, link down, media: %s\n",
940 __func__, (phydev->port == PORT_TP) ?
943 /* When in YT8521_MODE_POLL mode, need prepare for next
946 if (priv->polling_mode == YT8521_MODE_POLL) {
947 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
948 phydev->port = PORT_NONE;
959 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page
960 * @phydev: the phy_device struct
961 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate
962 * @mask: bit mask of bits to clear
963 * @set: bit mask of bits to set
965 * NOTE: Convenience function which allows a PHY's BMCR register to be
966 * modified as new register value = (old register value & ~mask) | set.
967 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
968 * has MII_BMCR. poll mode combines utp and faber,so need do both.
969 * If it is reset, it will wait for completion.
971 * returns 0 or negative errno code
973 static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page,
976 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */
980 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
982 goto err_restore_page;
984 ret = __phy_modify(phydev, MII_BMCR, mask, set);
986 goto err_restore_page;
988 /* If it is reset, need to wait for the reset to complete */
989 if (set == BMCR_RESET) {
991 usleep_range(1000, 1100);
992 ret = __phy_read(phydev, MII_BMCR);
994 goto err_restore_page;
996 if (!(ret & BMCR_RESET))
997 return phy_restore_page(phydev, old_page, 0);
1002 return phy_restore_page(phydev, old_page, ret);
1006 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register
1007 * @phydev: the phy_device struct
1008 * @mask: bit mask of bits to clear
1009 * @set: bit mask of bits to set
1011 * NOTE: Convenience function which allows a PHY's BMCR register to be
1012 * modified as new register value = (old register value & ~mask) | set.
1013 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
1014 * has MII_BMCR. poll mode combines utp and faber,so need do both.
1016 * returns 0 or negative errno code
1018 static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask,
1021 struct yt8521_priv *priv = phydev->priv;
1024 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1025 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask,
1030 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE,
1035 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE,
1044 * yt8521_soft_reset() - called to issue a PHY software reset
1045 * @phydev: a pointer to a &struct phy_device
1047 * returns 0 or negative errno code
1049 static int yt8521_soft_reset(struct phy_device *phydev)
1051 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET);
1055 * yt8521_suspend() - suspend the hardware
1056 * @phydev: a pointer to a &struct phy_device
1058 * returns 0 or negative errno code
1060 static int yt8521_suspend(struct phy_device *phydev)
1064 /* YTPHY_WOL_CONFIG_REG is common ext reg */
1065 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1069 /* if wol enable, do nothing */
1070 if (wol_config & YTPHY_WCR_ENABLE)
1073 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN);
1077 * yt8521_resume() - resume the hardware
1078 * @phydev: a pointer to a &struct phy_device
1080 * returns 0 or negative errno code
1082 static int yt8521_resume(struct phy_device *phydev)
1087 /* disable auto sleep */
1088 ret = ytphy_modify_ext_with_lock(phydev,
1089 YT8521_EXTREG_SLEEP_CONTROL1_REG,
1090 YT8521_ESC1R_SLEEP_SW, 0);
1094 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1098 /* if wol enable, do nothing */
1099 if (wol_config & YTPHY_WCR_ENABLE)
1102 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0);
1106 * yt8521_config_init() - called to initialize the PHY
1107 * @phydev: a pointer to a &struct phy_device
1109 * returns 0 or negative errno code
1111 static int yt8521_config_init(struct phy_device *phydev)
1117 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
1119 goto err_restore_page;
1121 switch (phydev->interface) {
1122 case PHY_INTERFACE_MODE_RGMII:
1123 val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_GE_TX_DELAY_DIS;
1124 val |= YT8521_RC1R_RX_DELAY_DIS;
1126 case PHY_INTERFACE_MODE_RGMII_RXID:
1127 val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_GE_TX_DELAY_DIS;
1128 val |= YT8521_RC1R_RX_DELAY_EN;
1130 case PHY_INTERFACE_MODE_RGMII_TXID:
1131 val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_GE_TX_DELAY_EN;
1132 val |= YT8521_RC1R_RX_DELAY_DIS;
1134 case PHY_INTERFACE_MODE_RGMII_ID:
1135 val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_GE_TX_DELAY_EN;
1136 val |= YT8521_RC1R_RX_DELAY_EN;
1138 case PHY_INTERFACE_MODE_SGMII:
1140 default: /* do not support other modes */
1142 goto err_restore_page;
1145 /* set rgmii delay mode */
1146 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1147 ret = ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG,
1148 (YT8521_RC1R_RX_DELAY_MASK |
1149 YT8521_RC1R_FE_TX_DELAY_MASK |
1150 YT8521_RC1R_GE_TX_DELAY_MASK),
1153 goto err_restore_page;
1155 /* disable rx delay */
1156 ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1157 YT8521_CCR_RXC_DLY_EN, 0);
1159 goto err_restore_page;
1162 /* disable auto sleep */
1163 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
1164 YT8521_ESC1R_SLEEP_SW, 0);
1166 goto err_restore_page;
1168 /* enable RXC clock when no wire plug */
1169 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
1170 YT8521_CGR_RX_CLK_EN, 0);
1172 goto err_restore_page;
1175 return phy_restore_page(phydev, old_page, ret);
1179 * yt8521_prepare_fiber_features() - A small helper function that setup
1181 * @phydev: a pointer to a &struct phy_device
1182 * @dst: a pointer to store fiber's features
1184 static void yt8521_prepare_fiber_features(struct phy_device *phydev,
1187 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst);
1188 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst);
1189 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst);
1190 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst);
1194 * yt8521_fiber_setup_forced - configures/forces speed from @phydev
1195 * @phydev: target phy_device struct
1197 * NOTE:The caller must have taken the MDIO bus lock.
1199 * returns 0 or negative errno code
1201 static int yt8521_fiber_setup_forced(struct phy_device *phydev)
1206 if (phydev->speed == SPEED_1000)
1207 val = YTPHY_MCR_FIBER_1000BX;
1208 else if (phydev->speed == SPEED_100)
1209 val = YTPHY_MCR_FIBER_100FX;
1213 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1217 /* disable Fiber auto sensing */
1218 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1219 YT8521_LTCR_EN_AUTOSEN, 0);
1223 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG,
1224 YTPHY_MCR_FIBER_SPEED_MASK, val);
1228 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1229 YT8521_CCR_SW_RST, 0);
1233 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation
1234 * @phydev: target phy_device struct
1235 * @restart: whether aneg restart is requested
1237 * NOTE:The caller must have taken the MDIO bus lock.
1239 * returns 0 or negative errno code
1241 static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
1246 /* Advertisement hasn't changed, but maybe aneg was never on to
1247 * begin with? Or maybe phy was isolated?
1249 ret = __phy_read(phydev, MII_BMCR);
1253 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
1256 /* Enable and Restart Autonegotiation
1257 * Don't isolate the PHY if we're negotiating
1260 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
1261 BMCR_ANENABLE | BMCR_ANRESTART);
1267 * yt8521_fiber_config_aneg - restart auto-negotiation or write
1268 * YTPHY_MISC_CONFIG_REG.
1269 * @phydev: target phy_device struct
1271 * NOTE:The caller must have taken the MDIO bus lock.
1273 * returns 0 or negative errno code
1275 static int yt8521_fiber_config_aneg(struct phy_device *phydev)
1277 int err, changed = 0;
1281 if (phydev->autoneg != AUTONEG_ENABLE)
1282 return yt8521_fiber_setup_forced(phydev);
1284 /* enable Fiber auto sensing */
1285 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1286 0, YT8521_LTCR_EN_AUTOSEN);
1290 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1291 YT8521_CCR_SW_RST, 0);
1295 bmcr = __phy_read(phydev, MII_BMCR);
1299 /* When it is coming from fiber forced mode, add bmcr power down
1300 * and power up to let aneg work fine.
1302 if (!(bmcr & BMCR_ANENABLE)) {
1303 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
1304 usleep_range(1000, 1100);
1305 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
1308 adv = linkmode_adv_to_mii_adv_x(phydev->advertising,
1309 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
1311 /* Setup fiber advertisement */
1312 err = __phy_modify_changed(phydev, MII_ADVERTISE,
1313 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
1314 ADVERTISE_1000XPAUSE |
1315 ADVERTISE_1000XPSE_ASYM,
1323 return ytphy_check_and_restart_aneg(phydev, changed);
1327 * ytphy_setup_master_slave
1328 * @phydev: target phy_device struct
1330 * NOTE: The caller must have taken the MDIO bus lock.
1332 * returns 0 or negative errno code
1334 static int ytphy_setup_master_slave(struct phy_device *phydev)
1338 if (!phydev->is_gigabit_capable)
1341 switch (phydev->master_slave_set) {
1342 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
1343 ctl |= CTL1000_PREFER_MASTER;
1345 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
1347 case MASTER_SLAVE_CFG_MASTER_FORCE:
1348 ctl |= CTL1000_AS_MASTER;
1350 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1351 ctl |= CTL1000_ENABLE_MASTER;
1353 case MASTER_SLAVE_CFG_UNKNOWN:
1354 case MASTER_SLAVE_CFG_UNSUPPORTED:
1357 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1361 return __phy_modify_changed(phydev, MII_CTRL1000,
1362 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
1363 CTL1000_PREFER_MASTER), ctl);
1367 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters
1368 * @phydev: target phy_device struct
1370 * NOTE: Writes MII_ADVERTISE with the appropriate values,
1371 * after sanitizing the values to make sure we only advertise
1372 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
1373 * hasn't changed, and > 0 if it has changed.
1374 * The caller must have taken the MDIO bus lock.
1376 * returns 0 or negative errno code
1378 static int ytphy_utp_config_advert(struct phy_device *phydev)
1380 int err, bmsr, changed = 0;
1383 /* Only allow advertising what this PHY supports */
1384 linkmode_and(phydev->advertising, phydev->advertising,
1387 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
1389 /* Setup standard advertisement */
1390 err = __phy_modify_changed(phydev, MII_ADVERTISE,
1391 ADVERTISE_ALL | ADVERTISE_100BASE4 |
1392 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
1399 bmsr = __phy_read(phydev, MII_BMSR);
1403 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
1404 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
1407 if (!(bmsr & BMSR_ESTATEN))
1410 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1412 err = __phy_modify_changed(phydev, MII_CTRL1000,
1413 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
1424 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR
1425 * @phydev: target phy_device struct
1426 * @changed: whether autoneg is requested
1428 * NOTE: If auto-negotiation is enabled, we configure the
1429 * advertising, and then restart auto-negotiation. If it is not
1430 * enabled, then we write the BMCR.
1431 * The caller must have taken the MDIO bus lock.
1433 * returns 0 or negative errno code
1435 static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed)
1440 err = ytphy_setup_master_slave(phydev);
1446 if (phydev->autoneg != AUTONEG_ENABLE) {
1447 /* configures/forces speed/duplex from @phydev */
1449 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
1451 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK |
1452 BMCR_ISOLATE | BMCR_PDOWN), ctl);
1455 err = ytphy_utp_config_advert(phydev);
1456 if (err < 0) /* error */
1461 return ytphy_check_and_restart_aneg(phydev, changed);
1465 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg
1467 * @phydev: a pointer to a &struct phy_device
1468 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1471 * returns 0 or negative errno code
1473 static int yt8521_config_aneg_paged(struct phy_device *phydev, int page)
1475 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported);
1476 struct yt8521_priv *priv = phydev->priv;
1480 page &= YT8521_RSSR_SPACE_MASK;
1482 old_page = phy_select_page(phydev, page);
1484 goto err_restore_page;
1486 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
1487 * phydev->advertising should be updated.
1489 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
1490 linkmode_zero(fiber_supported);
1491 yt8521_prepare_fiber_features(phydev, fiber_supported);
1493 /* prepare fiber_supported, then setup advertising. */
1494 if (page == YT8521_RSSR_FIBER_SPACE) {
1495 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
1497 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
1499 linkmode_and(phydev->advertising,
1500 priv->combo_advertising, fiber_supported);
1502 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */
1503 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1505 linkmode_andnot(phydev->advertising,
1506 priv->combo_advertising,
1511 if (page == YT8521_RSSR_FIBER_SPACE)
1512 ret = yt8521_fiber_config_aneg(phydev);
1514 ret = ytphy_utp_config_aneg(phydev, false);
1517 return phy_restore_page(phydev, old_page, ret);
1521 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged
1522 * @phydev: a pointer to a &struct phy_device
1524 * returns 0 or negative errno code
1526 static int yt8521_config_aneg(struct phy_device *phydev)
1528 struct yt8521_priv *priv = phydev->priv;
1531 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1532 ret = yt8521_config_aneg_paged(phydev, priv->reg_page);
1536 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
1537 * phydev->advertising need to be saved at first run.
1538 * Because it contains the advertising which supported by both
1539 * mac and yt8521(utp and fiber).
1541 if (linkmode_empty(priv->combo_advertising)) {
1542 linkmode_copy(priv->combo_advertising,
1543 phydev->advertising);
1546 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE);
1550 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE);
1554 /* we don't known which will be link, so restore
1555 * phydev->advertising as default value.
1557 linkmode_copy(phydev->advertising, priv->combo_advertising);
1563 * yt8521_aneg_done_paged() - determines the auto negotiation result of one
1565 * @phydev: a pointer to a &struct phy_device
1566 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1569 * returns 0(no link)or 1(fiber or utp link) or negative errno code
1571 static int yt8521_aneg_done_paged(struct phy_device *phydev, int page)
1577 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
1579 goto err_restore_page;
1581 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
1583 goto err_restore_page;
1585 link = !!(ret & YTPHY_SSR_LINK);
1589 return phy_restore_page(phydev, old_page, ret);
1593 * yt8521_aneg_done() - determines the auto negotiation result
1594 * @phydev: a pointer to a &struct phy_device
1596 * returns 0(no link)or 1(fiber or utp link) or negative errno code
1598 static int yt8521_aneg_done(struct phy_device *phydev)
1600 struct yt8521_priv *priv = phydev->priv;
1605 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1606 link = yt8521_aneg_done_paged(phydev, priv->reg_page);
1608 link_utp = yt8521_aneg_done_paged(phydev,
1609 YT8521_RSSR_UTP_SPACE);
1614 link_fiber = yt8521_aneg_done_paged(phydev,
1615 YT8521_RSSR_FIBER_SPACE);
1619 link = link_fiber || link_utp;
1620 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n",
1621 __func__, link_fiber, link_utp);
1628 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers
1629 * @phydev: target phy_device struct
1631 * NOTE: Reads the PHY's abilities and populates
1632 * phydev->supported accordingly.
1633 * The caller must have taken the MDIO bus lock.
1635 * returns 0 or negative errno code
1637 static int ytphy_utp_read_abilities(struct phy_device *phydev)
1641 linkmode_set_bit_array(phy_basic_ports_array,
1642 ARRAY_SIZE(phy_basic_ports_array),
1645 val = __phy_read(phydev, MII_BMSR);
1649 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
1650 val & BMSR_ANEGCAPABLE);
1652 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
1653 val & BMSR_100FULL);
1654 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
1655 val & BMSR_100HALF);
1656 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
1658 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
1661 if (val & BMSR_ESTATEN) {
1662 val = __phy_read(phydev, MII_ESTATUS);
1666 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1667 phydev->supported, val & ESTATUS_1000_TFULL);
1668 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1669 phydev->supported, val & ESTATUS_1000_THALF);
1670 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1671 phydev->supported, val & ESTATUS_1000_XFULL);
1678 * yt8521_get_features_paged() - read supported link modes for one page
1679 * @phydev: a pointer to a &struct phy_device
1680 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1683 * returns 0 or negative errno code
1685 static int yt8521_get_features_paged(struct phy_device *phydev, int page)
1690 page &= YT8521_RSSR_SPACE_MASK;
1691 old_page = phy_select_page(phydev, page);
1693 goto err_restore_page;
1695 if (page == YT8521_RSSR_FIBER_SPACE) {
1696 linkmode_zero(phydev->supported);
1697 yt8521_prepare_fiber_features(phydev, phydev->supported);
1699 ret = ytphy_utp_read_abilities(phydev);
1701 goto err_restore_page;
1705 return phy_restore_page(phydev, old_page, ret);
1709 * yt8521_get_features - switch reg space then call yt8521_get_features_paged
1710 * @phydev: target phy_device struct
1712 * returns 0 or negative errno code
1714 static int yt8521_get_features(struct phy_device *phydev)
1716 struct yt8521_priv *priv = phydev->priv;
1719 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1720 ret = yt8521_get_features_paged(phydev, priv->reg_page);
1722 ret = yt8521_get_features_paged(phydev,
1723 YT8521_RSSR_UTP_SPACE);
1727 /* add fiber's features to phydev->supported */
1728 yt8521_prepare_fiber_features(phydev, phydev->supported);
1733 static struct phy_driver motorcomm_phy_drvs[] = {
1735 PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
1736 .name = "YT8511 Gigabit Ethernet",
1737 .config_init = yt8511_config_init,
1738 .suspend = genphy_suspend,
1739 .resume = genphy_resume,
1740 .read_page = yt8511_read_page,
1741 .write_page = yt8511_write_page,
1744 PHY_ID_MATCH_EXACT(PHY_ID_YT8521),
1745 .name = "YT8521 Gigabit Ethernet",
1746 .get_features = yt8521_get_features,
1747 .probe = yt8521_probe,
1748 .read_page = yt8521_read_page,
1749 .write_page = yt8521_write_page,
1750 .get_wol = ytphy_get_wol,
1751 .set_wol = ytphy_set_wol,
1752 .config_aneg = yt8521_config_aneg,
1753 .aneg_done = yt8521_aneg_done,
1754 .config_init = yt8521_config_init,
1755 .read_status = yt8521_read_status,
1756 .soft_reset = yt8521_soft_reset,
1757 .suspend = yt8521_suspend,
1758 .resume = yt8521_resume,
1762 module_phy_driver(motorcomm_phy_drvs);
1764 MODULE_DESCRIPTION("Motorcomm 8511/8521 PHY driver");
1765 MODULE_AUTHOR("Peter Geis");
1766 MODULE_AUTHOR("Frank");
1767 MODULE_LICENSE("GPL");
1769 static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
1770 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
1771 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
1775 MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);