1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 Industrie Dial Face S.p.A.
4 * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
7 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
11 * This provides a bit-banged interface to the ethernet MII management
17 #include <ppc_asm.tmpl>
19 #include <asm/global_data.h>
21 #define BB_MII_RELOCATE(v,off) (v += (v?off:0))
23 DECLARE_GLOBAL_DATA_PTR;
25 #ifndef CONFIG_BITBANGMII_MULTI
28 * If CONFIG_BITBANGMII_MULTI is not defined we use a
29 * compatibility layer with the previous miiphybb implementation
30 * based on macros usage.
33 static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
41 static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
50 static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
59 static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
68 static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
77 static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
86 static int bb_delay_wrap(struct bb_miiphy_bus *bus)
92 struct bb_miiphy_bus bb_miiphy_buses[] = {
94 .name = BB_MII_DEVNAME,
95 .init = bb_mii_init_wrap,
96 .mdio_active = bb_mdio_active_wrap,
97 .mdio_tristate = bb_mdio_tristate_wrap,
98 .set_mdio = bb_set_mdio_wrap,
99 .get_mdio = bb_get_mdio_wrap,
100 .set_mdc = bb_set_mdc_wrap,
101 .delay = bb_delay_wrap,
105 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
106 sizeof(bb_miiphy_buses[0]);
109 int bb_miiphy_init(void)
113 for (i = 0; i < bb_miiphy_buses_num; i++) {
114 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
115 /* Relocate the hook pointers*/
116 BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
117 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
118 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
119 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
120 BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
121 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
122 BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
124 if (bb_miiphy_buses[i].init != NULL) {
125 bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
132 static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
134 #ifdef CONFIG_BITBANGMII_MULTI
137 /* Search the correct bus */
138 for (i = 0; i < bb_miiphy_buses_num; i++) {
139 if (!strcmp(bb_miiphy_buses[i].name, devname)) {
140 return &bb_miiphy_buses[i];
145 /* We have just one bitbanging bus */
146 return &bb_miiphy_buses[0];
150 /*****************************************************************************
152 * Utility to send the preamble, address, and register (common to read
155 static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
156 unsigned char addr, unsigned char reg)
161 * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
162 * The IEEE spec says this is a PHY optional requirement. The AMD
163 * 79C874 requires one after power up and one after a MII communications
164 * error. This means that we are doing more preambles than we need,
165 * but it is safer and will be much more robust.
168 bus->mdio_active(bus);
169 bus->set_mdio(bus, 1);
170 for (j = 0; j < 32; j++) {
171 bus->set_mdc(bus, 0);
173 bus->set_mdc(bus, 1);
177 /* send the start bit (01) and the read opcode (10) or write (10) */
178 bus->set_mdc(bus, 0);
179 bus->set_mdio(bus, 0);
181 bus->set_mdc(bus, 1);
183 bus->set_mdc(bus, 0);
184 bus->set_mdio(bus, 1);
186 bus->set_mdc(bus, 1);
188 bus->set_mdc(bus, 0);
189 bus->set_mdio(bus, read);
191 bus->set_mdc(bus, 1);
193 bus->set_mdc(bus, 0);
194 bus->set_mdio(bus, !read);
196 bus->set_mdc(bus, 1);
199 /* send the PHY address */
200 for (j = 0; j < 5; j++) {
201 bus->set_mdc(bus, 0);
202 if ((addr & 0x10) == 0) {
203 bus->set_mdio(bus, 0);
205 bus->set_mdio(bus, 1);
208 bus->set_mdc(bus, 1);
213 /* send the register address */
214 for (j = 0; j < 5; j++) {
215 bus->set_mdc(bus, 0);
216 if ((reg & 0x10) == 0) {
217 bus->set_mdio(bus, 0);
219 bus->set_mdio(bus, 1);
222 bus->set_mdc(bus, 1);
228 /*****************************************************************************
230 * Read a MII PHY register.
235 int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
237 unsigned short rdreg; /* register working value */
240 struct bb_miiphy_bus *bus;
242 bus = bb_miiphy_getbus(miidev->name);
247 miiphy_pre (bus, 1, addr, reg);
249 /* tri-state our MDIO I/O pin so we can read */
250 bus->set_mdc(bus, 0);
251 bus->mdio_tristate(bus);
253 bus->set_mdc(bus, 1);
256 /* check the turnaround bit: the PHY should be driving it to zero */
257 bus->get_mdio(bus, &v);
259 /* puts ("PHY didn't drive TA low\n"); */
260 for (j = 0; j < 32; j++) {
261 bus->set_mdc(bus, 0);
263 bus->set_mdc(bus, 1);
266 /* There is no PHY, return */
270 bus->set_mdc(bus, 0);
273 /* read 16 bits of register data, MSB first */
275 for (j = 0; j < 16; j++) {
276 bus->set_mdc(bus, 1);
279 bus->get_mdio(bus, &v);
281 bus->set_mdc(bus, 0);
285 bus->set_mdc(bus, 1);
287 bus->set_mdc(bus, 0);
289 bus->set_mdc(bus, 1);
293 printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg);
300 /*****************************************************************************
302 * Write a MII PHY register.
307 int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
310 struct bb_miiphy_bus *bus;
313 bus = bb_miiphy_getbus(miidev->name);
319 miiphy_pre (bus, 0, addr, reg);
321 /* send the turnaround (10) */
322 bus->set_mdc(bus, 0);
323 bus->set_mdio(bus, 1);
325 bus->set_mdc(bus, 1);
327 bus->set_mdc(bus, 0);
328 bus->set_mdio(bus, 0);
330 bus->set_mdc(bus, 1);
333 /* write 16 bits of register data, MSB first */
334 for (j = 0; j < 16; j++) {
335 bus->set_mdc(bus, 0);
336 if ((value & 0x00008000) == 0) {
337 bus->set_mdio(bus, 0);
339 bus->set_mdio(bus, 1);
342 bus->set_mdc(bus, 1);
348 * Tri-state the MDIO line.
350 bus->mdio_tristate(bus);
351 bus->set_mdc(bus, 0);
353 bus->set_mdc(bus, 1);