drivers/net/phy/microchip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Microchip Technology
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/module.h>
   7 #include <linux/mii.h>
   8 #include <linux/ethtool.h>
   9 #include <linux/phy.h>
  10 #include <linux/microchipphy.h>
  11 #include <linux/delay.h>
  12 #include <linux/of.h>
  13 #include <dt-bindings/net/microchip-lan78xx.h>
  14
  15 #define DRIVER_AUTHOR   "WOOJUNG HUH <woojung.huh@microchip.com>"
  16 #define DRIVER_DESC     "Microchip LAN88XX PHY driver"
  17
  18 struct lan88xx_priv {
  19         int     chip_id;
  20         int     chip_rev;
  21         __u32   wolopts;
  22 };
  23
  24 static int lan88xx_read_page(struct phy_device *phydev)
  25 {
  26         return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
  27 }
  28
  29 static int lan88xx_write_page(struct phy_device *phydev, int page)
  30 {
  31         return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
  32 }
  33
  34 static int lan88xx_phy_config_intr(struct phy_device *phydev)
  35 {
  36         int rc;
  37
  38         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  39                 /* unmask all source and clear them before enable */
  40                 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
  41                 rc = phy_read(phydev, LAN88XX_INT_STS);
  42                 rc = phy_write(phydev, LAN88XX_INT_MASK,
  43                                LAN88XX_INT_MASK_MDINTPIN_EN_ |
  44                                LAN88XX_INT_MASK_LINK_CHANGE_);
  45         } else {
  46                 rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
  47                 if (rc)
  48                         return rc;
  49
  50                 /* Ack interrupts after they have been disabled */
  51                 rc = phy_read(phydev, LAN88XX_INT_STS);
  52         }
  53
  54         return rc < 0 ? rc : 0;
  55 }
  56
  57 static irqreturn_t lan88xx_handle_interrupt(struct phy_device *phydev)
  58 {
  59         int irq_status;
  60
  61         irq_status = phy_read(phydev, LAN88XX_INT_STS);
  62         if (irq_status < 0) {
  63                 phy_error(phydev);
  64                 return IRQ_NONE;
  65         }
  66
  67         if (!(irq_status & LAN88XX_INT_STS_LINK_CHANGE_))
  68                 return IRQ_NONE;
  69
  70         phy_trigger_machine(phydev);
  71
  72         return IRQ_HANDLED;
  73 }
  74
  75 static int lan88xx_suspend(struct phy_device *phydev)
  76 {
  77         struct lan88xx_priv *priv = phydev->priv;
  78
  79         /* do not power down PHY when WOL is enabled */
  80         if (!priv->wolopts)
  81                 genphy_suspend(phydev);
  82
  83         return 0;
  84 }
  85
  86 static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
  87                               u32 data)
  88 {
  89         int val, save_page, ret = 0;
  90         u16 buf;
  91
  92         /* Save current page */
  93         save_page = phy_save_page(phydev);
  94         if (save_page < 0) {
  95                 phydev_warn(phydev, "Failed to get current page\n");
  96                 goto err;
  97         }
  98
  99         /* Switch to TR page */
 100         lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
 101
 102         ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
 103                           (data & 0xFFFF));
 104         if (ret < 0) {
 105                 phydev_warn(phydev, "Failed to write TR low data\n");
 106                 goto err;
 107         }
 108
 109         ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
 110                           (data & 0x00FF0000) >> 16);
 111         if (ret < 0) {
 112                 phydev_warn(phydev, "Failed to write TR high data\n");
 113                 goto err;
 114         }
 115
 116         /* Config control bits [15:13] of register */
 117         buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
 118         buf |= 0x8000; /* Set [15] to Packet transmit */
 119
 120         ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
 121         if (ret < 0) {
 122                 phydev_warn(phydev, "Failed to write data in reg\n");
 123                 goto err;
 124         }
 125
 126         usleep_range(1000, 2000);/* Wait for Data to be written */
 127         val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
 128         if (!(val & 0x8000))
 129                 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
 130                             regaddr);
 131 err:
 132         return phy_restore_page(phydev, save_page, ret);
 133 }
 134
 135 static void lan88xx_config_TR_regs(struct phy_device *phydev)
 136 {
 137         int err;
 138
 139         /* Get access to Channel 0x1, Node 0xF , Register 0x01.
 140          * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
 141          * MrvlTrFix1000Kp, MasterEnableTR bits.
 142          */
 143         err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
 144         if (err < 0)
 145                 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
 146
 147         /* Get access to Channel b'10, Node b'1101, Register 0x06.
 148          * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
 149          * SSTrKp1000Mas bits.
 150          */
 151         err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
 152         if (err < 0)
 153                 phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
 154
 155         /* Get access to Channel b'10, Node b'1111, Register 0x11.
 156          * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
 157          * bits
 158          */
 159         err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
 160         if (err < 0)
 161                 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
 162
 163         /* Get access to Channel b'10, Node b'1101, Register 0x10.
 164          * Write 24-bit value 0xEEFFDD to register. Setting
 165          * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
 166          * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
 167          */
 168         err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
 169         if (err < 0)
 170                 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
 171
 172         /* Get access to Channel b'10, Node b'1101, Register 0x13.
 173          * Write 24-bit value 0x071448 to register. Setting
 174          * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
 175          */
 176         err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
 177         if (err < 0)
 178                 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
 179
 180         /* Get access to Channel b'10, Node b'1101, Register 0x12.
 181          * Write 24-bit value 0x13132F to register. Setting
 182          * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
 183          */
 184         err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
 185         if (err < 0)
 186                 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
 187
 188         /* Get access to Channel b'10, Node b'1101, Register 0x14.
 189          * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
 190          * eee_TrKf_freeze_delay bits.
 191          */
 192         err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
 193         if (err < 0)
 194                 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
 195
 196         /* Get access to Channel b'01, Node b'1111, Register 0x34.
 197          * Write 24-bit value 0x91B06C to register. Setting
 198          * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
 199          * FastMseSearchUpdGain1000 bits.
 200          */
 201         err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
 202         if (err < 0)
 203                 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
 204
 205         /* Get access to Channel b'01, Node b'1111, Register 0x3E.
 206          * Write 24-bit value 0xC0A028 to register. Setting
 207          * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
 208          * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
 209          */
 210         err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
 211         if (err < 0)
 212                 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
 213
 214         /* Get access to Channel b'01, Node b'1111, Register 0x35.
 215          * Write 24-bit value 0x041600 to register. Setting
 216          * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
 217          * FastMsePhChangeDelay1000 bits.
 218          */
 219         err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
 220         if (err < 0)
 221                 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
 222
 223         /* Get access to Channel b'10, Node b'1101, Register 0x03.
 224          * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
 225          */
 226         err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
 227         if (err < 0)
 228                 phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
 229 }
 230
 231 static int lan88xx_probe(struct phy_device *phydev)
 232 {
 233         struct device *dev = &phydev->mdio.dev;
 234         struct lan88xx_priv *priv;
 235         u32 led_modes[4];
 236         u32 downshift_after = 0;
 237         int len;
 238
 239         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 240         if (!priv)
 241                 return -ENOMEM;
 242
 243         priv->wolopts = 0;
 244
 245         len = of_property_read_variable_u32_array(dev->of_node,
 246                                                   "microchip,led-modes",
 247                                                   led_modes,
 248                                                   0,
 249                                                   ARRAY_SIZE(led_modes));
 250         if (len >= 0) {
 251                 u32 reg = 0;
 252                 int i;
 253
 254                 for (i = 0; i < len; i++) {
 255                         if (led_modes[i] > 15)
 256                                 return -EINVAL;
 257                         reg |= led_modes[i] << (i * 4);
 258                 }
 259                 for (; i < ARRAY_SIZE(led_modes); i++)
 260                         reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
 261                 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
 262         } else if (len == -EOVERFLOW) {
 263                 return -EINVAL;
 264         }
 265
 266         if (!of_property_read_u32(dev->of_node,
 267                                   "microchip,downshift-after",
 268                                   &downshift_after)) {
 269                 u32 mask = LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK;
 270                 u32 val= LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
 271
 272                 switch (downshift_after) {
 273                 case 2: val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2;
 274                         break;
 275                 case 3: val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3;
 276                         break;
 277                 case 4: val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4;
 278                         break;
 279                 case 5: val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5;
 280                         break;
 281                 case 0: // Disable completely
 282                         mask = LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
 283                         val = 0;
 284                         break;
 285                 default:
 286                         return -EINVAL;
 287                 }
 288                 (void)phy_modify_paged(phydev, 1, LAN78XX_PHY_CTRL3,
 289                                        mask, val);
 290         }
 291
 292         /* these values can be used to identify internal PHY */
 293         priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
 294         priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
 295
 296         phydev->priv = priv;
 297
 298         return 0;
 299 }
 300
 301 static void lan88xx_remove(struct phy_device *phydev)
 302 {
 303         struct device *dev = &phydev->mdio.dev;
 304         struct lan88xx_priv *priv = phydev->priv;
 305
 306         if (priv)
 307                 devm_kfree(dev, priv);
 308 }
 309
 310 static int lan88xx_set_wol(struct phy_device *phydev,
 311                            struct ethtool_wolinfo *wol)
 312 {
 313         struct lan88xx_priv *priv = phydev->priv;
 314
 315         priv->wolopts = wol->wolopts;
 316
 317         return 0;
 318 }
 319
 320 static void lan88xx_set_mdix(struct phy_device *phydev)
 321 {
 322         int buf;
 323         int val;
 324
 325         switch (phydev->mdix_ctrl) {
 326         case ETH_TP_MDI:
 327                 val = LAN88XX_EXT_MODE_CTRL_MDI_;
 328                 break;
 329         case ETH_TP_MDI_X:
 330                 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
 331                 break;
 332         case ETH_TP_MDI_AUTO:
 333                 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
 334                 break;
 335         default:
 336                 return;
 337         }
 338
 339         phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
 340         buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
 341         buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
 342         buf |= val;
 343         phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
 344         phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
 345 }
 346
 347 static int lan88xx_config_init(struct phy_device *phydev)
 348 {
 349         int val;
 350
 351         /*Zerodetect delay enable */
 352         val = phy_read_mmd(phydev, MDIO_MMD_PCS,
 353                            PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
 354         val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
 355
 356         phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
 357                       val);
 358
 359         /* Config DSP registers */
 360         lan88xx_config_TR_regs(phydev);
 361
 362         return 0;
 363 }
 364
 365 static int lan88xx_config_aneg(struct phy_device *phydev)
 366 {
 367         lan88xx_set_mdix(phydev);
 368
 369         return genphy_config_aneg(phydev);
 370 }
 371
 372 static struct phy_driver microchip_phy_driver[] = {
 373 {
 374         .phy_id         = 0x0007c130,
 375         .phy_id_mask    = 0xfffffff0,
 376         .name           = "Microchip LAN88xx",
 377
 378         /* PHY_GBIT_FEATURES */
 379
 380         .probe          = lan88xx_probe,
 381         .remove         = lan88xx_remove,
 382
 383         .config_init    = lan88xx_config_init,
 384         .config_aneg    = lan88xx_config_aneg,
 385
 386         .config_intr    = lan88xx_phy_config_intr,
 387         .handle_interrupt = lan88xx_handle_interrupt,
 388
 389         .suspend        = lan88xx_suspend,
 390         .resume         = genphy_resume,
 391         .set_wol        = lan88xx_set_wol,
 392         .read_page      = lan88xx_read_page,
 393         .write_page     = lan88xx_write_page,
 394 } };
 395
 396 module_phy_driver(microchip_phy_driver);
 397
 398 static struct mdio_device_id __maybe_unused microchip_tbl[] = {
 399         { 0x0007c130, 0xfffffff0 },
 400         { }
 401 };
 402
 403 MODULE_DEVICE_TABLE(mdio, microchip_tbl);
 404
 405 MODULE_AUTHOR(DRIVER_AUTHOR);
 406 MODULE_DESCRIPTION(DRIVER_DESC);
 407 MODULE_LICENSE("GPL");