drivers/net/phy/micrel_ksz90x1.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Micrel PHY drivers
   4  *
   5  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   6  * author Andy Fleming
   7  * (C) 2012 NetModule AG, David Andrey, added KSZ9031
   8  * (C) Copyright 2017 Adaptrum, Inc.
   9  * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
  10  */
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <env.h>
  14 #include <errno.h>
  15 #include <micrel.h>
  16 #include <phy.h>
  17
  18 /*
  19  * KSZ9021 - KSZ9031 common
  20  */
  21
  22 #define MII_KSZ90xx_PHY_CTL             0x1f
  23 #define MIIM_KSZ90xx_PHYCTL_1000        (1 << 6)
  24 #define MIIM_KSZ90xx_PHYCTL_100         (1 << 5)
  25 #define MIIM_KSZ90xx_PHYCTL_10          (1 << 4)
  26 #define MIIM_KSZ90xx_PHYCTL_DUPLEX      (1 << 3)
  27
  28 /* KSZ9021 PHY Registers */
  29 #define MII_KSZ9021_EXTENDED_CTRL       0x0b
  30 #define MII_KSZ9021_EXTENDED_DATAW      0x0c
  31 #define MII_KSZ9021_EXTENDED_DATAR      0x0d
  32
  33 #define CTRL1000_PREFER_MASTER          (1 << 10)
  34 #define CTRL1000_CONFIG_MASTER          (1 << 11)
  35 #define CTRL1000_MANUAL_CONFIG          (1 << 12)
  36
  37 #define KSZ9021_PS_TO_REG               120
  38
  39 /* KSZ9031 PHY Registers */
  40 #define MII_KSZ9031_MMD_ACCES_CTRL      0x0d
  41 #define MII_KSZ9031_MMD_REG_DATA        0x0e
  42
  43 #define KSZ9031_PS_TO_REG               60
  44
  45 static int ksz90xx_startup(struct phy_device *phydev)
  46 {
  47         unsigned phy_ctl;
  48         int ret;
  49
  50         ret = genphy_update_link(phydev);
  51         if (ret)
  52                 return ret;
  53
  54         phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
  55
  56         if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
  57                 phydev->duplex = DUPLEX_FULL;
  58         else
  59                 phydev->duplex = DUPLEX_HALF;
  60
  61         if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
  62                 phydev->speed = SPEED_1000;
  63         else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
  64                 phydev->speed = SPEED_100;
  65         else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
  66                 phydev->speed = SPEED_10;
  67         return 0;
  68 }
  69
  70 /* Common OF config bits for KSZ9021 and KSZ9031 */
  71 #ifdef CONFIG_DM_ETH
  72 struct ksz90x1_reg_field {
  73         const char      *name;
  74         const u8        size;   /* Size of the bitfield, in bits */
  75         const u8        off;    /* Offset from bit 0 */
  76         const u8        dflt;   /* Default value */
  77 };
  78
  79 struct ksz90x1_ofcfg {
  80         const u16                       reg;
  81         const u16                       devad;
  82         const struct ksz90x1_reg_field  *grp;
  83         const u16                       grpsz;
  84 };
  85
  86 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
  87         { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
  88         { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
  89 };
  90
  91 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
  92         { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
  93         { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
  94 };
  95
  96 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
  97         { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
  98         { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
  99 };
 100
 101 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
 102         { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
 103 };
 104
 105 static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
 106         { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
 107 };
 108
 109 static int ksz90x1_of_config_group(struct phy_device *phydev,
 110                                    struct ksz90x1_ofcfg *ofcfg,
 111                                    int ps_to_regval)
 112 {
 113         struct udevice *dev = phydev->dev;
 114         struct phy_driver *drv = phydev->drv;
 115         int val[4];
 116         int i, changed = 0, offset, max;
 117         u16 regval = 0;
 118         ofnode node;
 119
 120         if (!drv || !drv->writeext)
 121                 return -EOPNOTSUPP;
 122
 123         node = phydev->node;
 124
 125         if (!ofnode_valid(node)) {
 126                 /* Look for a PHY node under the Ethernet node */
 127                 node = dev_read_subnode(dev, "ethernet-phy");
 128         }
 129
 130         if (!ofnode_valid(node)) {
 131                 /* No node found, look in the Ethernet node */
 132                 node = dev_ofnode(dev);
 133         }
 134
 135         for (i = 0; i < ofcfg->grpsz; i++) {
 136                 val[i] = ofnode_read_u32_default(node, ofcfg->grp[i].name, ~0);
 137                 offset = ofcfg->grp[i].off;
 138                 if (val[i] == -1) {
 139                         /* Default register value for KSZ9021 */
 140                         regval |= ofcfg->grp[i].dflt << offset;
 141                 } else {
 142                         changed = 1;    /* Value was changed in OF */
 143                         /* Calculate the register value and fix corner cases */
 144                         max = (1 << ofcfg->grp[i].size) - 1;
 145                         if (val[i] > ps_to_regval * max) {
 146                                 regval |= max << offset;
 147                         } else {
 148                                 regval |= (val[i] / ps_to_regval) << offset;
 149                         }
 150                 }
 151         }
 152
 153         if (!changed)
 154                 return 0;
 155
 156         return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
 157 }
 158
 159 static int ksz9021_of_config(struct phy_device *phydev)
 160 {
 161         struct ksz90x1_ofcfg ofcfg[] = {
 162                 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
 163                 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
 164                 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
 165         };
 166         int i, ret = 0;
 167
 168         for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
 169                 ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
 170                                               KSZ9021_PS_TO_REG);
 171                 if (ret)
 172                         return ret;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static int ksz9031_of_config(struct phy_device *phydev)
 179 {
 180         struct ksz90x1_ofcfg ofcfg[] = {
 181                 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
 182                 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
 183                 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
 184                 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
 185         };
 186         int i, ret = 0;
 187
 188         for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
 189                 ret = ksz90x1_of_config_group(phydev, &ofcfg[i],
 190                                               KSZ9031_PS_TO_REG);
 191                 if (ret)
 192                         return ret;
 193         }
 194
 195         return 0;
 196 }
 197
 198 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 199 {
 200         struct phy_driver *drv = phydev->drv;
 201         int ret = 0;
 202
 203         if (!drv || !drv->writeext)
 204                 return -EOPNOTSUPP;
 205
 206         ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
 207         if (ret)
 208                 return ret;
 209
 210         ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
 211         return ret;
 212 }
 213
 214 #else /* !CONFIG_DM_ETH */
 215 static int ksz9021_of_config(struct phy_device *phydev)
 216 {
 217         return 0;
 218 }
 219
 220 static int ksz9031_of_config(struct phy_device *phydev)
 221 {
 222         return 0;
 223 }
 224
 225 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 226 {
 227         return 0;
 228 }
 229 #endif
 230
 231 /*
 232  * KSZ9021
 233  */
 234 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
 235 {
 236         /* extended registers */
 237         phy_write(phydev, MDIO_DEVAD_NONE,
 238                   MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
 239         return phy_write(phydev, MDIO_DEVAD_NONE,
 240                          MII_KSZ9021_EXTENDED_DATAW, val);
 241 }
 242
 243 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
 244 {
 245         /* extended registers */
 246         phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
 247         return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
 248 }
 249
 250
 251 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
 252                                int regnum)
 253 {
 254         return ksz9021_phy_extended_read(phydev, regnum);
 255 }
 256
 257 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
 258                                 int devaddr, int regnum, u16 val)
 259 {
 260         return ksz9021_phy_extended_write(phydev, regnum, val);
 261 }
 262
 263 static int ksz9021_config(struct phy_device *phydev)
 264 {
 265         unsigned ctrl1000 = 0;
 266         const unsigned master = CTRL1000_PREFER_MASTER |
 267         CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
 268         unsigned features = phydev->drv->features;
 269         int ret;
 270
 271         ret = ksz9021_of_config(phydev);
 272         if (ret)
 273                 return ret;
 274
 275         if (env_get("disable_giga"))
 276                 features &= ~(SUPPORTED_1000baseT_Half |
 277                 SUPPORTED_1000baseT_Full);
 278         /* force master mode for 1000BaseT due to chip errata */
 279         if (features & SUPPORTED_1000baseT_Half)
 280                 ctrl1000 |= ADVERTISE_1000HALF | master;
 281         if (features & SUPPORTED_1000baseT_Full)
 282                 ctrl1000 |= ADVERTISE_1000FULL | master;
 283         phydev->advertising = features;
 284         phydev->supported = features;
 285         phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
 286         genphy_config_aneg(phydev);
 287         genphy_restart_aneg(phydev);
 288         return 0;
 289 }
 290
 291 static struct phy_driver ksz9021_driver = {
 292         .name = "Micrel ksz9021",
 293         .uid  = 0x221610,
 294         .mask = 0xfffffe,
 295         .features = PHY_GBIT_FEATURES,
 296         .config = &ksz9021_config,
 297         .startup = &ksz90xx_startup,
 298         .shutdown = &genphy_shutdown,
 299         .writeext = &ksz9021_phy_extwrite,
 300         .readext = &ksz9021_phy_extread,
 301 };
 302
 303 /*
 304  * KSZ9031
 305  */
 306 int ksz9031_phy_extended_write(struct phy_device *phydev,
 307                                int devaddr, int regnum, u16 mode, u16 val)
 308 {
 309         /*select register addr for mmd*/
 310         phy_write(phydev, MDIO_DEVAD_NONE,
 311                   MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
 312         /*select register for mmd*/
 313         phy_write(phydev, MDIO_DEVAD_NONE,
 314                   MII_KSZ9031_MMD_REG_DATA, regnum);
 315         /*setup mode*/
 316         phy_write(phydev, MDIO_DEVAD_NONE,
 317                   MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
 318         /*write the value*/
 319         return  phy_write(phydev, MDIO_DEVAD_NONE,
 320                           MII_KSZ9031_MMD_REG_DATA, val);
 321 }
 322
 323 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
 324                               int regnum, u16 mode)
 325 {
 326         phy_write(phydev, MDIO_DEVAD_NONE,
 327                   MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
 328         phy_write(phydev, MDIO_DEVAD_NONE,
 329                   MII_KSZ9031_MMD_REG_DATA, regnum);
 330         phy_write(phydev, MDIO_DEVAD_NONE,
 331                   MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
 332         return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
 333 }
 334
 335 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
 336                                int regnum)
 337 {
 338         return ksz9031_phy_extended_read(phydev, devaddr, regnum,
 339                                          MII_KSZ9031_MOD_DATA_NO_POST_INC);
 340 }
 341
 342 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
 343                                 int devaddr, int regnum, u16 val)
 344 {
 345         return ksz9031_phy_extended_write(phydev, devaddr, regnum,
 346                                           MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
 347 }
 348
 349 static int ksz9031_config(struct phy_device *phydev)
 350 {
 351         int ret;
 352
 353         ret = ksz9031_of_config(phydev);
 354         if (ret)
 355                 return ret;
 356         ret = ksz9031_center_flp_timing(phydev);
 357         if (ret)
 358                 return ret;
 359
 360         /* add an option to disable the gigabit feature of this PHY */
 361         if (env_get("disable_giga")) {
 362                 unsigned features;
 363                 unsigned bmcr;
 364
 365                 /* disable speed 1000 in features supported by the PHY */
 366                 features = phydev->drv->features;
 367                 features &= ~(SUPPORTED_1000baseT_Half |
 368                                 SUPPORTED_1000baseT_Full);
 369                 phydev->advertising = phydev->supported = features;
 370
 371                 /* disable speed 1000 in Basic Control Register */
 372                 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
 373                 bmcr &= ~(1 << 6);
 374                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
 375
 376                 /* disable speed 1000 in 1000Base-T Control Register */
 377                 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
 378
 379                 /* start autoneg */
 380                 genphy_config_aneg(phydev);
 381                 genphy_restart_aneg(phydev);
 382
 383                 return 0;
 384         }
 385
 386         return genphy_config(phydev);
 387 }
 388
 389 static struct phy_driver ksz9031_driver = {
 390         .name = "Micrel ksz9031",
 391         .uid  = PHY_ID_KSZ9031,
 392         .mask = MII_KSZ9x31_SILICON_REV_MASK,
 393         .features = PHY_GBIT_FEATURES,
 394         .config   = &ksz9031_config,
 395         .startup  = &ksz90xx_startup,
 396         .shutdown = &genphy_shutdown,
 397         .writeext = &ksz9031_phy_extwrite,
 398         .readext = &ksz9031_phy_extread,
 399 };
 400
 401 /*
 402  * KSZ9131
 403  */
 404
 405 #define KSZ9131RN_MMD_COMMON_CTRL_REG   2
 406 #define KSZ9131RN_RXC_DLL_CTRL          76
 407 #define KSZ9131RN_TXC_DLL_CTRL          77
 408 #define KSZ9131RN_DLL_CTRL_BYPASS       BIT_MASK(12)
 409 #define KSZ9131RN_DLL_ENABLE_DELAY      0
 410 #define KSZ9131RN_DLL_DISABLE_DELAY     BIT(12)
 411
 412 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
 413 {
 414         struct phy_driver *drv = phydev->drv;
 415         u16 rxcdll_val, txcdll_val, val;
 416         int ret;
 417
 418         switch (phydev->interface) {
 419         case PHY_INTERFACE_MODE_RGMII:
 420                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
 421                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
 422                 break;
 423         case PHY_INTERFACE_MODE_RGMII_ID:
 424                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
 425                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
 426                 break;
 427         case PHY_INTERFACE_MODE_RGMII_RXID:
 428                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
 429                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
 430                 break;
 431         case PHY_INTERFACE_MODE_RGMII_TXID:
 432                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
 433                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
 434                 break;
 435         default:
 436                 return 0;
 437         }
 438
 439         val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
 440                            KSZ9131RN_RXC_DLL_CTRL);
 441         val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
 442         val |= rxcdll_val;
 443         ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
 444                             KSZ9131RN_RXC_DLL_CTRL, val);
 445         if (ret)
 446                 return ret;
 447
 448         val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
 449                            KSZ9131RN_TXC_DLL_CTRL);
 450
 451         val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
 452         val |= txcdll_val;
 453         ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
 454                             KSZ9131RN_TXC_DLL_CTRL, val);
 455
 456         return ret;
 457 }
 458
 459 static int ksz9131_config(struct phy_device *phydev)
 460 {
 461         int ret;
 462
 463         if (phy_interface_is_rgmii(phydev)) {
 464                 ret = ksz9131_config_rgmii_delay(phydev);
 465                 if (ret)
 466                         return ret;
 467         }
 468
 469         /* add an option to disable the gigabit feature of this PHY */
 470         if (env_get("disable_giga")) {
 471                 unsigned features;
 472                 unsigned bmcr;
 473
 474                 /* disable speed 1000 in features supported by the PHY */
 475                 features = phydev->drv->features;
 476                 features &= ~(SUPPORTED_1000baseT_Half |
 477                                 SUPPORTED_1000baseT_Full);
 478                 phydev->advertising = phydev->supported = features;
 479
 480                 /* disable speed 1000 in Basic Control Register */
 481                 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
 482                 bmcr &= ~(1 << 6);
 483                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
 484
 485                 /* disable speed 1000 in 1000Base-T Control Register */
 486                 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
 487
 488                 /* start autoneg */
 489                 genphy_config_aneg(phydev);
 490                 genphy_restart_aneg(phydev);
 491
 492                 return 0;
 493         }
 494
 495         return genphy_config(phydev);
 496 }
 497
 498 static struct phy_driver ksz9131_driver = {
 499         .name = "Micrel ksz9131",
 500         .uid  = PHY_ID_KSZ9131,
 501         .mask = MII_KSZ9x31_SILICON_REV_MASK,
 502         .features = PHY_GBIT_FEATURES,
 503         .config   = &ksz9131_config,
 504         .startup  = &ksz90xx_startup,
 505         .shutdown = &genphy_shutdown,
 506         .writeext = &ksz9031_phy_extwrite,
 507         .readext = &ksz9031_phy_extread,
 508 };
 509
 510 int ksz9xx1_phy_get_id(struct phy_device *phydev)
 511 {
 512         unsigned int phyid;
 513
 514         get_phy_id(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, &phyid);
 515
 516         return phyid;
 517 }
 518
 519 int phy_micrel_ksz90x1_init(void)
 520 {
 521         phy_register(&ksz9021_driver);
 522         phy_register(&ksz9031_driver);
 523         phy_register(&ksz9131_driver);
 524         return 0;
 525 }