drivers/net/phy/micrel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/micrel.c
   4  *
   5  * Driver for Micrel PHYs
   6  *
   7  * Author: David J. Choi
   8  *
   9  * Copyright (c) 2010-2013 Micrel, Inc.
  10  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  11  *
  12  * Support : Micrel Phys:
  13  *              Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
  14  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  15  *                         ksz8021, ksz8031, ksz8051,
  16  *                         ksz8081, ksz8091,
  17  *                         ksz8061,
  18  *              Switch : ksz8873, ksz886x
  19  *                       ksz9477, lan8804
  20  */
  21
  22 #include <linux/bitfield.h>
  23 #include <linux/ethtool_netlink.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/phy.h>
  27 #include <linux/micrel_phy.h>
  28 #include <linux/of.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31 #include <linux/ptp_clock_kernel.h>
  32 #include <linux/ptp_clock.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/net_tstamp.h>
  35 #include <linux/gpio/consumer.h>
  36
  37 /* Operation Mode Strap Override */
  38 #define MII_KSZPHY_OMSO                         0x16
  39 #define KSZPHY_OMSO_FACTORY_TEST                BIT(15)
  40 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  41 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  42 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  43 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  44
  45 /* general Interrupt control/status reg in vendor specific block. */
  46 #define MII_KSZPHY_INTCS                        0x1B
  47 #define KSZPHY_INTCS_JABBER                     BIT(15)
  48 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  49 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  50 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  51 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  52 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  53 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  54 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  55 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  56                                                 KSZPHY_INTCS_LINK_DOWN)
  57 #define KSZPHY_INTCS_LINK_DOWN_STATUS           BIT(2)
  58 #define KSZPHY_INTCS_LINK_UP_STATUS             BIT(0)
  59 #define KSZPHY_INTCS_STATUS                     (KSZPHY_INTCS_LINK_DOWN_STATUS |\
  60                                                  KSZPHY_INTCS_LINK_UP_STATUS)
  61
  62 /* LinkMD Control/Status */
  63 #define KSZ8081_LMD                             0x1d
  64 #define KSZ8081_LMD_ENABLE_TEST                 BIT(15)
  65 #define KSZ8081_LMD_STAT_NORMAL                 0
  66 #define KSZ8081_LMD_STAT_OPEN                   1
  67 #define KSZ8081_LMD_STAT_SHORT                  2
  68 #define KSZ8081_LMD_STAT_FAIL                   3
  69 #define KSZ8081_LMD_STAT_MASK                   GENMASK(14, 13)
  70 /* Short cable (<10 meter) has been detected by LinkMD */
  71 #define KSZ8081_LMD_SHORT_INDICATOR             BIT(12)
  72 #define KSZ8081_LMD_DELTA_TIME_MASK             GENMASK(8, 0)
  73
  74 #define KSZ9x31_LMD                             0x12
  75 #define KSZ9x31_LMD_VCT_EN                      BIT(15)
  76 #define KSZ9x31_LMD_VCT_DIS_TX                  BIT(14)
  77 #define KSZ9x31_LMD_VCT_PAIR(n)                 (((n) & 0x3) << 12)
  78 #define KSZ9x31_LMD_VCT_SEL_RESULT              0
  79 #define KSZ9x31_LMD_VCT_SEL_THRES_HI            BIT(10)
  80 #define KSZ9x31_LMD_VCT_SEL_THRES_LO            BIT(11)
  81 #define KSZ9x31_LMD_VCT_SEL_MASK                GENMASK(11, 10)
  82 #define KSZ9x31_LMD_VCT_ST_NORMAL               0
  83 #define KSZ9x31_LMD_VCT_ST_OPEN                 1
  84 #define KSZ9x31_LMD_VCT_ST_SHORT                2
  85 #define KSZ9x31_LMD_VCT_ST_FAIL                 3
  86 #define KSZ9x31_LMD_VCT_ST_MASK                 GENMASK(9, 8)
  87 #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID  BIT(7)
  88 #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG  BIT(6)
  89 #define KSZ9x31_LMD_VCT_DATA_MASK100            BIT(5)
  90 #define KSZ9x31_LMD_VCT_DATA_NLP_FLP            BIT(4)
  91 #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK      GENMASK(3, 2)
  92 #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK      GENMASK(1, 0)
  93 #define KSZ9x31_LMD_VCT_DATA_MASK               GENMASK(7, 0)
  94
  95 #define KSZPHY_WIRE_PAIR_MASK                   0x3
  96
  97 #define LAN8814_CABLE_DIAG                      0x12
  98 #define LAN8814_CABLE_DIAG_STAT_MASK            GENMASK(9, 8)
  99 #define LAN8814_CABLE_DIAG_VCT_DATA_MASK        GENMASK(7, 0)
 100 #define LAN8814_PAIR_BIT_SHIFT                  12
 101
 102 #define LAN8814_WIRE_PAIR_MASK                  0xF
 103
 104 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
 105 #define LAN8814_INTC                            0x18
 106 #define LAN8814_INTS                            0x1B
 107
 108 #define LAN8814_INT_LINK_DOWN                   BIT(2)
 109 #define LAN8814_INT_LINK_UP                     BIT(0)
 110 #define LAN8814_INT_LINK                        (LAN8814_INT_LINK_UP |\
 111                                                  LAN8814_INT_LINK_DOWN)
 112
 113 #define LAN8814_INTR_CTRL_REG                   0x34
 114 #define LAN8814_INTR_CTRL_REG_POLARITY          BIT(1)
 115 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE       BIT(0)
 116
 117 /* Represents 1ppm adjustment in 2^32 format with
 118  * each nsec contains 4 clock cycles.
 119  * The value is calculated as following: (1/1000000)/((2^-32)/4)
 120  */
 121 #define LAN8814_1PPM_FORMAT                     17179
 122
 123 #define PTP_RX_MOD                              0x024F
 124 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 125 #define PTP_RX_TIMESTAMP_EN                     0x024D
 126 #define PTP_TX_TIMESTAMP_EN                     0x028D
 127
 128 #define PTP_TIMESTAMP_EN_SYNC_                  BIT(0)
 129 #define PTP_TIMESTAMP_EN_DREQ_                  BIT(1)
 130 #define PTP_TIMESTAMP_EN_PDREQ_                 BIT(2)
 131 #define PTP_TIMESTAMP_EN_PDRES_                 BIT(3)
 132
 133 #define PTP_TX_PARSE_L2_ADDR_EN                 0x0284
 134 #define PTP_RX_PARSE_L2_ADDR_EN                 0x0244
 135
 136 #define PTP_TX_PARSE_IP_ADDR_EN                 0x0285
 137 #define PTP_RX_PARSE_IP_ADDR_EN                 0x0245
 138 #define LTC_HARD_RESET                          0x023F
 139 #define LTC_HARD_RESET_                         BIT(0)
 140
 141 #define TSU_HARD_RESET                          0x02C1
 142 #define TSU_HARD_RESET_                         BIT(0)
 143
 144 #define PTP_CMD_CTL                             0x0200
 145 #define PTP_CMD_CTL_PTP_DISABLE_                BIT(0)
 146 #define PTP_CMD_CTL_PTP_ENABLE_                 BIT(1)
 147 #define PTP_CMD_CTL_PTP_CLOCK_READ_             BIT(3)
 148 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_             BIT(4)
 149 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_           BIT(5)
 150 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_          BIT(6)
 151
 152 #define PTP_CLOCK_SET_SEC_MID                   0x0206
 153 #define PTP_CLOCK_SET_SEC_LO                    0x0207
 154 #define PTP_CLOCK_SET_NS_HI                     0x0208
 155 #define PTP_CLOCK_SET_NS_LO                     0x0209
 156
 157 #define PTP_CLOCK_READ_SEC_MID                  0x022A
 158 #define PTP_CLOCK_READ_SEC_LO                   0x022B
 159 #define PTP_CLOCK_READ_NS_HI                    0x022C
 160 #define PTP_CLOCK_READ_NS_LO                    0x022D
 161
 162 #define PTP_OPERATING_MODE                      0x0241
 163 #define PTP_OPERATING_MODE_STANDALONE_          BIT(0)
 164
 165 #define PTP_TX_MOD                              0x028F
 166 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_       BIT(12)
 167 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 168
 169 #define PTP_RX_PARSE_CONFIG                     0x0242
 170 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 171 #define PTP_RX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 172 #define PTP_RX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 173
 174 #define PTP_TX_PARSE_CONFIG                     0x0282
 175 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 176 #define PTP_TX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 177 #define PTP_TX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 178
 179 #define PTP_CLOCK_RATE_ADJ_HI                   0x020C
 180 #define PTP_CLOCK_RATE_ADJ_LO                   0x020D
 181 #define PTP_CLOCK_RATE_ADJ_DIR_                 BIT(15)
 182
 183 #define PTP_LTC_STEP_ADJ_HI                     0x0212
 184 #define PTP_LTC_STEP_ADJ_LO                     0x0213
 185 #define PTP_LTC_STEP_ADJ_DIR_                   BIT(15)
 186
 187 #define LAN8814_INTR_STS_REG                    0x0033
 188 #define LAN8814_INTR_STS_REG_1588_TSU0_         BIT(0)
 189 #define LAN8814_INTR_STS_REG_1588_TSU1_         BIT(1)
 190 #define LAN8814_INTR_STS_REG_1588_TSU2_         BIT(2)
 191 #define LAN8814_INTR_STS_REG_1588_TSU3_         BIT(3)
 192
 193 #define PTP_CAP_INFO                            0x022A
 194 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)    (((reg_val) & 0x0f00) >> 8)
 195 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val)    ((reg_val) & 0x000f)
 196
 197 #define PTP_TX_EGRESS_SEC_HI                    0x0296
 198 #define PTP_TX_EGRESS_SEC_LO                    0x0297
 199 #define PTP_TX_EGRESS_NS_HI                     0x0294
 200 #define PTP_TX_EGRESS_NS_LO                     0x0295
 201 #define PTP_TX_MSG_HEADER2                      0x0299
 202
 203 #define PTP_RX_INGRESS_SEC_HI                   0x0256
 204 #define PTP_RX_INGRESS_SEC_LO                   0x0257
 205 #define PTP_RX_INGRESS_NS_HI                    0x0254
 206 #define PTP_RX_INGRESS_NS_LO                    0x0255
 207 #define PTP_RX_MSG_HEADER2                      0x0259
 208
 209 #define PTP_TSU_INT_EN                          0x0200
 210 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_      BIT(3)
 211 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_            BIT(2)
 212 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_      BIT(1)
 213 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_            BIT(0)
 214
 215 #define PTP_TSU_INT_STS                         0x0201
 216 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_    BIT(3)
 217 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_           BIT(2)
 218 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_    BIT(1)
 219 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_           BIT(0)
 220
 221 #define LAN8814_LED_CTRL_1                      0x0
 222 #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_    BIT(6)
 223
 224 /* PHY Control 1 */
 225 #define MII_KSZPHY_CTRL_1                       0x1e
 226 #define KSZ8081_CTRL1_MDIX_STAT                 BIT(4)
 227
 228 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
 229 #define MII_KSZPHY_CTRL_2                       0x1f
 230 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
 231 /* bitmap of PHY register to set interrupt mode */
 232 #define KSZ8081_CTRL2_HP_MDIX                   BIT(15)
 233 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT          BIT(14)
 234 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX         BIT(13)
 235 #define KSZ8081_CTRL2_FORCE_LINK                BIT(11)
 236 #define KSZ8081_CTRL2_POWER_SAVING              BIT(10)
 237 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
 238 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
 239
 240 /* Write/read to/from extended registers */
 241 #define MII_KSZPHY_EXTREG                       0x0b
 242 #define KSZPHY_EXTREG_WRITE                     0x8000
 243
 244 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
 245 #define MII_KSZPHY_EXTREG_READ                  0x0d
 246
 247 /* Extended registers */
 248 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
 249 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
 250 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
 251
 252 #define PS_TO_REG                               200
 253 #define FIFO_SIZE                               8
 254
 255 /* Delay used to get the second part from the LTC */
 256 #define LAN8841_GET_SEC_LTC_DELAY               (500 * NSEC_PER_MSEC)
 257
 258 struct kszphy_hw_stat {
 259         const char *string;
 260         u8 reg;
 261         u8 bits;
 262 };
 263
 264 static struct kszphy_hw_stat kszphy_hw_stats[] = {
 265         { "phy_receive_errors", 21, 16},
 266         { "phy_idle_errors", 10, 8 },
 267 };
 268
 269 struct kszphy_type {
 270         u32 led_mode_reg;
 271         u16 interrupt_level_mask;
 272         u16 cable_diag_reg;
 273         unsigned long pair_mask;
 274         u16 disable_dll_tx_bit;
 275         u16 disable_dll_rx_bit;
 276         u16 disable_dll_mask;
 277         bool has_broadcast_disable;
 278         bool has_nand_tree_disable;
 279         bool has_rmii_ref_clk_sel;
 280 };
 281
 282 /* Shared structure between the PHYs of the same package. */
 283 struct lan8814_shared_priv {
 284         struct phy_device *phydev;
 285         struct ptp_clock *ptp_clock;
 286         struct ptp_clock_info ptp_clock_info;
 287
 288         /* Reference counter to how many ports in the package are enabling the
 289          * timestamping
 290          */
 291         u8 ref;
 292
 293         /* Lock for ptp_clock and ref */
 294         struct mutex shared_lock;
 295 };
 296
 297 struct lan8814_ptp_rx_ts {
 298         struct list_head list;
 299         u32 seconds;
 300         u32 nsec;
 301         u16 seq_id;
 302 };
 303
 304 struct kszphy_ptp_priv {
 305         struct mii_timestamper mii_ts;
 306         struct phy_device *phydev;
 307
 308         struct sk_buff_head tx_queue;
 309         struct sk_buff_head rx_queue;
 310
 311         struct list_head rx_ts_list;
 312         /* Lock for Rx ts fifo */
 313         spinlock_t rx_ts_lock;
 314
 315         int hwts_tx_type;
 316         enum hwtstamp_rx_filters rx_filter;
 317         int layer;
 318         int version;
 319
 320         struct ptp_clock *ptp_clock;
 321         struct ptp_clock_info ptp_clock_info;
 322         /* Lock for ptp_clock */
 323         struct mutex ptp_lock;
 324         struct ptp_pin_desc *pin_config;
 325
 326         s64 seconds;
 327         /* Lock for accessing seconds */
 328         spinlock_t seconds_lock;
 329 };
 330
 331 struct kszphy_priv {
 332         struct kszphy_ptp_priv ptp_priv;
 333         const struct kszphy_type *type;
 334         int led_mode;
 335         u16 vct_ctrl1000;
 336         bool rmii_ref_clk_sel;
 337         bool rmii_ref_clk_sel_val;
 338         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 339 };
 340
 341 static const struct kszphy_type lan8814_type = {
 342         .led_mode_reg           = ~LAN8814_LED_CTRL_1,
 343         .cable_diag_reg         = LAN8814_CABLE_DIAG,
 344         .pair_mask              = LAN8814_WIRE_PAIR_MASK,
 345 };
 346
 347 static const struct kszphy_type ksz886x_type = {
 348         .cable_diag_reg         = KSZ8081_LMD,
 349         .pair_mask              = KSZPHY_WIRE_PAIR_MASK,
 350 };
 351
 352 static const struct kszphy_type ksz8021_type = {
 353         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 354         .has_broadcast_disable  = true,
 355         .has_nand_tree_disable  = true,
 356         .has_rmii_ref_clk_sel   = true,
 357 };
 358
 359 static const struct kszphy_type ksz8041_type = {
 360         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 361 };
 362
 363 static const struct kszphy_type ksz8051_type = {
 364         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 365         .has_nand_tree_disable  = true,
 366 };
 367
 368 static const struct kszphy_type ksz8081_type = {
 369         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 370         .has_broadcast_disable  = true,
 371         .has_nand_tree_disable  = true,
 372         .has_rmii_ref_clk_sel   = true,
 373 };
 374
 375 static const struct kszphy_type ks8737_type = {
 376         .interrupt_level_mask   = BIT(14),
 377 };
 378
 379 static const struct kszphy_type ksz9021_type = {
 380         .interrupt_level_mask   = BIT(14),
 381 };
 382
 383 static const struct kszphy_type ksz9131_type = {
 384         .interrupt_level_mask   = BIT(14),
 385         .disable_dll_tx_bit     = BIT(12),
 386         .disable_dll_rx_bit     = BIT(12),
 387         .disable_dll_mask       = BIT_MASK(12),
 388 };
 389
 390 static const struct kszphy_type lan8841_type = {
 391         .disable_dll_tx_bit     = BIT(14),
 392         .disable_dll_rx_bit     = BIT(14),
 393         .disable_dll_mask       = BIT_MASK(14),
 394         .cable_diag_reg         = LAN8814_CABLE_DIAG,
 395         .pair_mask              = LAN8814_WIRE_PAIR_MASK,
 396 };
 397
 398 static int kszphy_extended_write(struct phy_device *phydev,
 399                                 u32 regnum, u16 val)
 400 {
 401         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 402         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 403 }
 404
 405 static int kszphy_extended_read(struct phy_device *phydev,
 406                                 u32 regnum)
 407 {
 408         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 409         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 410 }
 411
 412 static int kszphy_ack_interrupt(struct phy_device *phydev)
 413 {
 414         /* bit[7..0] int status, which is a read and clear register. */
 415         int rc;
 416
 417         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 418
 419         return (rc < 0) ? rc : 0;
 420 }
 421
 422 static int kszphy_config_intr(struct phy_device *phydev)
 423 {
 424         const struct kszphy_type *type = phydev->drv->driver_data;
 425         int temp, err;
 426         u16 mask;
 427
 428         if (type && type->interrupt_level_mask)
 429                 mask = type->interrupt_level_mask;
 430         else
 431                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 432
 433         /* set the interrupt pin active low */
 434         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 435         if (temp < 0)
 436                 return temp;
 437         temp &= ~mask;
 438         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 439
 440         /* enable / disable interrupts */
 441         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 442                 err = kszphy_ack_interrupt(phydev);
 443                 if (err)
 444                         return err;
 445
 446                 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
 447         } else {
 448                 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
 449                 if (err)
 450                         return err;
 451
 452                 err = kszphy_ack_interrupt(phydev);
 453         }
 454
 455         return err;
 456 }
 457
 458 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
 459 {
 460         int irq_status;
 461
 462         irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
 463         if (irq_status < 0) {
 464                 phy_error(phydev);
 465                 return IRQ_NONE;
 466         }
 467
 468         if (!(irq_status & KSZPHY_INTCS_STATUS))
 469                 return IRQ_NONE;
 470
 471         phy_trigger_machine(phydev);
 472
 473         return IRQ_HANDLED;
 474 }
 475
 476 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 477 {
 478         int ctrl;
 479
 480         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 481         if (ctrl < 0)
 482                 return ctrl;
 483
 484         if (val)
 485                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 486         else
 487                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 488
 489         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 490 }
 491
 492 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 493 {
 494         int rc, temp, shift;
 495
 496         switch (reg) {
 497         case MII_KSZPHY_CTRL_1:
 498                 shift = 14;
 499                 break;
 500         case MII_KSZPHY_CTRL_2:
 501                 shift = 4;
 502                 break;
 503         default:
 504                 return -EINVAL;
 505         }
 506
 507         temp = phy_read(phydev, reg);
 508         if (temp < 0) {
 509                 rc = temp;
 510                 goto out;
 511         }
 512
 513         temp &= ~(3 << shift);
 514         temp |= val << shift;
 515         rc = phy_write(phydev, reg, temp);
 516 out:
 517         if (rc < 0)
 518                 phydev_err(phydev, "failed to set led mode\n");
 519
 520         return rc;
 521 }
 522
 523 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 524  * unique (non-broadcast) address on a shared bus.
 525  */
 526 static int kszphy_broadcast_disable(struct phy_device *phydev)
 527 {
 528         int ret;
 529
 530         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 531         if (ret < 0)
 532                 goto out;
 533
 534         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 535 out:
 536         if (ret)
 537                 phydev_err(phydev, "failed to disable broadcast address\n");
 538
 539         return ret;
 540 }
 541
 542 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 543 {
 544         int ret;
 545
 546         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 547         if (ret < 0)
 548                 goto out;
 549
 550         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 551                 return 0;
 552
 553         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 554                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 555 out:
 556         if (ret)
 557                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 558
 559         return ret;
 560 }
 561
 562 /* Some config bits need to be set again on resume, handle them here. */
 563 static int kszphy_config_reset(struct phy_device *phydev)
 564 {
 565         struct kszphy_priv *priv = phydev->priv;
 566         int ret;
 567
 568         if (priv->rmii_ref_clk_sel) {
 569                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 570                 if (ret) {
 571                         phydev_err(phydev,
 572                                    "failed to set rmii reference clock\n");
 573                         return ret;
 574                 }
 575         }
 576
 577         if (priv->type && priv->led_mode >= 0)
 578                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 579
 580         return 0;
 581 }
 582
 583 static int kszphy_config_init(struct phy_device *phydev)
 584 {
 585         struct kszphy_priv *priv = phydev->priv;
 586         const struct kszphy_type *type;
 587
 588         if (!priv)
 589                 return 0;
 590
 591         type = priv->type;
 592
 593         if (type && type->has_broadcast_disable)
 594                 kszphy_broadcast_disable(phydev);
 595
 596         if (type && type->has_nand_tree_disable)
 597                 kszphy_nand_tree_disable(phydev);
 598
 599         return kszphy_config_reset(phydev);
 600 }
 601
 602 static int ksz8041_fiber_mode(struct phy_device *phydev)
 603 {
 604         struct device_node *of_node = phydev->mdio.dev.of_node;
 605
 606         return of_property_read_bool(of_node, "micrel,fiber-mode");
 607 }
 608
 609 static int ksz8041_config_init(struct phy_device *phydev)
 610 {
 611         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 612
 613         /* Limit supported and advertised modes in fiber mode */
 614         if (ksz8041_fiber_mode(phydev)) {
 615                 phydev->dev_flags |= MICREL_PHY_FXEN;
 616                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 617                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 618
 619                 linkmode_and(phydev->supported, phydev->supported, mask);
 620                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 621                                  phydev->supported);
 622                 linkmode_and(phydev->advertising, phydev->advertising, mask);
 623                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 624                                  phydev->advertising);
 625                 phydev->autoneg = AUTONEG_DISABLE;
 626         }
 627
 628         return kszphy_config_init(phydev);
 629 }
 630
 631 static int ksz8041_config_aneg(struct phy_device *phydev)
 632 {
 633         /* Skip auto-negotiation in fiber mode */
 634         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 635                 phydev->speed = SPEED_100;
 636                 return 0;
 637         }
 638
 639         return genphy_config_aneg(phydev);
 640 }
 641
 642 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
 643                                             const bool ksz_8051)
 644 {
 645         int ret;
 646
 647         if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
 648                 return 0;
 649
 650         ret = phy_read(phydev, MII_BMSR);
 651         if (ret < 0)
 652                 return ret;
 653
 654         /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
 655          * exact PHY ID. However, they can be told apart by the extended
 656          * capability registers presence. The KSZ8051 PHY has them while
 657          * the switch does not.
 658          */
 659         ret &= BMSR_ERCAP;
 660         if (ksz_8051)
 661                 return ret;
 662         else
 663                 return !ret;
 664 }
 665
 666 static int ksz8051_match_phy_device(struct phy_device *phydev)
 667 {
 668         return ksz8051_ksz8795_match_phy_device(phydev, true);
 669 }
 670
 671 static int ksz8081_config_init(struct phy_device *phydev)
 672 {
 673         /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
 674          * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
 675          * pull-down is missing, the factory test mode should be cleared by
 676          * manually writing a 0.
 677          */
 678         phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
 679
 680         return kszphy_config_init(phydev);
 681 }
 682
 683 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
 684 {
 685         u16 val;
 686
 687         switch (ctrl) {
 688         case ETH_TP_MDI:
 689                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
 690                 break;
 691         case ETH_TP_MDI_X:
 692                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
 693                         KSZ8081_CTRL2_MDI_MDI_X_SELECT;
 694                 break;
 695         case ETH_TP_MDI_AUTO:
 696                 val = 0;
 697                 break;
 698         default:
 699                 return 0;
 700         }
 701
 702         return phy_modify(phydev, MII_KSZPHY_CTRL_2,
 703                           KSZ8081_CTRL2_HP_MDIX |
 704                           KSZ8081_CTRL2_MDI_MDI_X_SELECT |
 705                           KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
 706                           KSZ8081_CTRL2_HP_MDIX | val);
 707 }
 708
 709 static int ksz8081_config_aneg(struct phy_device *phydev)
 710 {
 711         int ret;
 712
 713         ret = genphy_config_aneg(phydev);
 714         if (ret)
 715                 return ret;
 716
 717         /* The MDI-X configuration is automatically changed by the PHY after
 718          * switching from autoneg off to on. So, take MDI-X configuration under
 719          * own control and set it after autoneg configuration was done.
 720          */
 721         return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
 722 }
 723
 724 static int ksz8081_mdix_update(struct phy_device *phydev)
 725 {
 726         int ret;
 727
 728         ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
 729         if (ret < 0)
 730                 return ret;
 731
 732         if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
 733                 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
 734                         phydev->mdix_ctrl = ETH_TP_MDI_X;
 735                 else
 736                         phydev->mdix_ctrl = ETH_TP_MDI;
 737         } else {
 738                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 739         }
 740
 741         ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
 742         if (ret < 0)
 743                 return ret;
 744
 745         if (ret & KSZ8081_CTRL1_MDIX_STAT)
 746                 phydev->mdix = ETH_TP_MDI;
 747         else
 748                 phydev->mdix = ETH_TP_MDI_X;
 749
 750         return 0;
 751 }
 752
 753 static int ksz8081_read_status(struct phy_device *phydev)
 754 {
 755         int ret;
 756
 757         ret = ksz8081_mdix_update(phydev);
 758         if (ret < 0)
 759                 return ret;
 760
 761         return genphy_read_status(phydev);
 762 }
 763
 764 static int ksz8061_config_init(struct phy_device *phydev)
 765 {
 766         int ret;
 767
 768         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 769         if (ret)
 770                 return ret;
 771
 772         return kszphy_config_init(phydev);
 773 }
 774
 775 static int ksz8795_match_phy_device(struct phy_device *phydev)
 776 {
 777         return ksz8051_ksz8795_match_phy_device(phydev, false);
 778 }
 779
 780 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 781                                        const struct device_node *of_node,
 782                                        u16 reg,
 783                                        const char *field1, const char *field2,
 784                                        const char *field3, const char *field4)
 785 {
 786         int val1 = -1;
 787         int val2 = -2;
 788         int val3 = -3;
 789         int val4 = -4;
 790         int newval;
 791         int matches = 0;
 792
 793         if (!of_property_read_u32(of_node, field1, &val1))
 794                 matches++;
 795
 796         if (!of_property_read_u32(of_node, field2, &val2))
 797                 matches++;
 798
 799         if (!of_property_read_u32(of_node, field3, &val3))
 800                 matches++;
 801
 802         if (!of_property_read_u32(of_node, field4, &val4))
 803                 matches++;
 804
 805         if (!matches)
 806                 return 0;
 807
 808         if (matches < 4)
 809                 newval = kszphy_extended_read(phydev, reg);
 810         else
 811                 newval = 0;
 812
 813         if (val1 != -1)
 814                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 815
 816         if (val2 != -2)
 817                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 818
 819         if (val3 != -3)
 820                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 821
 822         if (val4 != -4)
 823                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 824
 825         return kszphy_extended_write(phydev, reg, newval);
 826 }
 827
 828 static int ksz9021_config_init(struct phy_device *phydev)
 829 {
 830         const struct device_node *of_node;
 831         const struct device *dev_walker;
 832
 833         /* The Micrel driver has a deprecated option to place phy OF
 834          * properties in the MAC node. Walk up the tree of devices to
 835          * find a device with an OF node.
 836          */
 837         dev_walker = &phydev->mdio.dev;
 838         do {
 839                 of_node = dev_walker->of_node;
 840                 dev_walker = dev_walker->parent;
 841
 842         } while (!of_node && dev_walker);
 843
 844         if (of_node) {
 845                 ksz9021_load_values_from_of(phydev, of_node,
 846                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 847                                     "txen-skew-ps", "txc-skew-ps",
 848                                     "rxdv-skew-ps", "rxc-skew-ps");
 849                 ksz9021_load_values_from_of(phydev, of_node,
 850                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 851                                     "rxd0-skew-ps", "rxd1-skew-ps",
 852                                     "rxd2-skew-ps", "rxd3-skew-ps");
 853                 ksz9021_load_values_from_of(phydev, of_node,
 854                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 855                                     "txd0-skew-ps", "txd1-skew-ps",
 856                                     "txd2-skew-ps", "txd3-skew-ps");
 857         }
 858         return 0;
 859 }
 860
 861 #define KSZ9031_PS_TO_REG               60
 862
 863 /* Extended registers */
 864 /* MMD Address 0x0 */
 865 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 866 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 867
 868 /* MMD Address 0x2 */
 869 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 870 #define MII_KSZ9031RN_RX_CTL_M          GENMASK(7, 4)
 871 #define MII_KSZ9031RN_TX_CTL_M          GENMASK(3, 0)
 872
 873 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 874 #define MII_KSZ9031RN_RXD3              GENMASK(15, 12)
 875 #define MII_KSZ9031RN_RXD2              GENMASK(11, 8)
 876 #define MII_KSZ9031RN_RXD1              GENMASK(7, 4)
 877 #define MII_KSZ9031RN_RXD0              GENMASK(3, 0)
 878
 879 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 880 #define MII_KSZ9031RN_TXD3              GENMASK(15, 12)
 881 #define MII_KSZ9031RN_TXD2              GENMASK(11, 8)
 882 #define MII_KSZ9031RN_TXD1              GENMASK(7, 4)
 883 #define MII_KSZ9031RN_TXD0              GENMASK(3, 0)
 884
 885 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 886 #define MII_KSZ9031RN_GTX_CLK           GENMASK(9, 5)
 887 #define MII_KSZ9031RN_RX_CLK            GENMASK(4, 0)
 888
 889 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
 890  * provide different RGMII options we need to configure delay offset
 891  * for each pad relative to build in delay.
 892  */
 893 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
 894  * 1.80ns
 895  */
 896 #define RX_ID                           0x7
 897 #define RX_CLK_ID                       0x19
 898
 899 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
 900  * internal 1.2ns delay.
 901  */
 902 #define RX_ND                           0xc
 903 #define RX_CLK_ND                       0x0
 904
 905 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
 906 #define TX_ID                           0x0
 907 #define TX_CLK_ID                       0x1f
 908
 909 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
 910  * dealy
 911  */
 912 #define TX_ND                           0x7
 913 #define TX_CLK_ND                       0xf
 914
 915 /* MMD Address 0x1C */
 916 #define MII_KSZ9031RN_EDPD              0x23
 917 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 918
 919 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 920                                        const struct device_node *of_node,
 921                                        u16 reg, size_t field_sz,
 922                                        const char *field[], u8 numfields,
 923                                        bool *update)
 924 {
 925         int val[4] = {-1, -2, -3, -4};
 926         int matches = 0;
 927         u16 mask;
 928         u16 maxval;
 929         u16 newval;
 930         int i;
 931
 932         for (i = 0; i < numfields; i++)
 933                 if (!of_property_read_u32(of_node, field[i], val + i))
 934                         matches++;
 935
 936         if (!matches)
 937                 return 0;
 938
 939         *update |= true;
 940
 941         if (matches < numfields)
 942                 newval = phy_read_mmd(phydev, 2, reg);
 943         else
 944                 newval = 0;
 945
 946         maxval = (field_sz == 4) ? 0xf : 0x1f;
 947         for (i = 0; i < numfields; i++)
 948                 if (val[i] != -(i + 1)) {
 949                         mask = 0xffff;
 950                         mask ^= maxval << (field_sz * i);
 951                         newval = (newval & mask) |
 952                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 953                                         << (field_sz * i));
 954                 }
 955
 956         return phy_write_mmd(phydev, 2, reg, newval);
 957 }
 958
 959 /* Center KSZ9031RNX FLP timing at 16ms. */
 960 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 961 {
 962         int result;
 963
 964         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
 965                                0x0006);
 966         if (result)
 967                 return result;
 968
 969         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
 970                                0x1A80);
 971         if (result)
 972                 return result;
 973
 974         return genphy_restart_aneg(phydev);
 975 }
 976
 977 /* Enable energy-detect power-down mode */
 978 static int ksz9031_enable_edpd(struct phy_device *phydev)
 979 {
 980         int reg;
 981
 982         reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
 983         if (reg < 0)
 984                 return reg;
 985         return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
 986                              reg | MII_KSZ9031RN_EDPD_ENABLE);
 987 }
 988
 989 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
 990 {
 991         u16 rx, tx, rx_clk, tx_clk;
 992         int ret;
 993
 994         switch (phydev->interface) {
 995         case PHY_INTERFACE_MODE_RGMII:
 996                 tx = TX_ND;
 997                 tx_clk = TX_CLK_ND;
 998                 rx = RX_ND;
 999                 rx_clk = RX_CLK_ND;
1000                 break;
1001         case PHY_INTERFACE_MODE_RGMII_ID:
1002                 tx = TX_ID;
1003                 tx_clk = TX_CLK_ID;
1004                 rx = RX_ID;
1005                 rx_clk = RX_CLK_ID;
1006                 break;
1007         case PHY_INTERFACE_MODE_RGMII_RXID:
1008                 tx = TX_ND;
1009                 tx_clk = TX_CLK_ND;
1010                 rx = RX_ID;
1011                 rx_clk = RX_CLK_ID;
1012                 break;
1013         case PHY_INTERFACE_MODE_RGMII_TXID:
1014                 tx = TX_ID;
1015                 tx_clk = TX_CLK_ID;
1016                 rx = RX_ND;
1017                 rx_clk = RX_CLK_ND;
1018                 break;
1019         default:
1020                 return 0;
1021         }
1022
1023         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1024                             FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1025                             FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1026         if (ret < 0)
1027                 return ret;
1028
1029         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1030                             FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1031                             FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1032                             FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1033                             FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1034         if (ret < 0)
1035                 return ret;
1036
1037         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1038                             FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1039                             FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1040                             FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1041                             FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1042         if (ret < 0)
1043                 return ret;
1044
1045         return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1046                              FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1047                              FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1048 }
1049
1050 static int ksz9031_config_init(struct phy_device *phydev)
1051 {
1052         const struct device_node *of_node;
1053         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1054         static const char *rx_data_skews[4] = {
1055                 "rxd0-skew-ps", "rxd1-skew-ps",
1056                 "rxd2-skew-ps", "rxd3-skew-ps"
1057         };
1058         static const char *tx_data_skews[4] = {
1059                 "txd0-skew-ps", "txd1-skew-ps",
1060                 "txd2-skew-ps", "txd3-skew-ps"
1061         };
1062         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1063         const struct device *dev_walker;
1064         int result;
1065
1066         result = ksz9031_enable_edpd(phydev);
1067         if (result < 0)
1068                 return result;
1069
1070         /* The Micrel driver has a deprecated option to place phy OF
1071          * properties in the MAC node. Walk up the tree of devices to
1072          * find a device with an OF node.
1073          */
1074         dev_walker = &phydev->mdio.dev;
1075         do {
1076                 of_node = dev_walker->of_node;
1077                 dev_walker = dev_walker->parent;
1078         } while (!of_node && dev_walker);
1079
1080         if (of_node) {
1081                 bool update = false;
1082
1083                 if (phy_interface_is_rgmii(phydev)) {
1084                         result = ksz9031_config_rgmii_delay(phydev);
1085                         if (result < 0)
1086                                 return result;
1087                 }
1088
1089                 ksz9031_of_load_skew_values(phydev, of_node,
1090                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1091                                 clk_skews, 2, &update);
1092
1093                 ksz9031_of_load_skew_values(phydev, of_node,
1094                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1095                                 control_skews, 2, &update);
1096
1097                 ksz9031_of_load_skew_values(phydev, of_node,
1098                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1099                                 rx_data_skews, 4, &update);
1100
1101                 ksz9031_of_load_skew_values(phydev, of_node,
1102                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1103                                 tx_data_skews, 4, &update);
1104
1105                 if (update && !phy_interface_is_rgmii(phydev))
1106                         phydev_warn(phydev,
1107                                     "*-skew-ps values should be used only with RGMII PHY modes\n");
1108
1109                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1110                  * When the device links in the 1000BASE-T slave mode only,
1111                  * the optional 125MHz reference output clock (CLK125_NDO)
1112                  * has wide duty cycle variation.
1113                  *
1114                  * The optional CLK125_NDO clock does not meet the RGMII
1115                  * 45/55 percent (min/max) duty cycle requirement and therefore
1116                  * cannot be used directly by the MAC side for clocking
1117                  * applications that have setup/hold time requirements on
1118                  * rising and falling clock edges.
1119                  *
1120                  * Workaround:
1121                  * Force the phy to be the master to receive a stable clock
1122                  * which meets the duty cycle requirement.
1123                  */
1124                 if (of_property_read_bool(of_node, "micrel,force-master")) {
1125                         result = phy_read(phydev, MII_CTRL1000);
1126                         if (result < 0)
1127                                 goto err_force_master;
1128
1129                         /* enable master mode, config & prefer master */
1130                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1131                         result = phy_write(phydev, MII_CTRL1000, result);
1132                         if (result < 0)
1133                                 goto err_force_master;
1134                 }
1135         }
1136
1137         return ksz9031_center_flp_timing(phydev);
1138
1139 err_force_master:
1140         phydev_err(phydev, "failed to force the phy to master mode\n");
1141         return result;
1142 }
1143
1144 #define KSZ9131_SKEW_5BIT_MAX   2400
1145 #define KSZ9131_SKEW_4BIT_MAX   800
1146 #define KSZ9131_OFFSET          700
1147 #define KSZ9131_STEP            100
1148
1149 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1150                                        struct device_node *of_node,
1151                                        u16 reg, size_t field_sz,
1152                                        char *field[], u8 numfields)
1153 {
1154         int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1155                       -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1156         int skewval, skewmax = 0;
1157         int matches = 0;
1158         u16 maxval;
1159         u16 newval;
1160         u16 mask;
1161         int i;
1162
1163         /* psec properties in dts should mean x pico seconds */
1164         if (field_sz == 5)
1165                 skewmax = KSZ9131_SKEW_5BIT_MAX;
1166         else
1167                 skewmax = KSZ9131_SKEW_4BIT_MAX;
1168
1169         for (i = 0; i < numfields; i++)
1170                 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1171                         if (skewval < -KSZ9131_OFFSET)
1172                                 skewval = -KSZ9131_OFFSET;
1173                         else if (skewval > skewmax)
1174                                 skewval = skewmax;
1175
1176                         val[i] = skewval + KSZ9131_OFFSET;
1177                         matches++;
1178                 }
1179
1180         if (!matches)
1181                 return 0;
1182
1183         if (matches < numfields)
1184                 newval = phy_read_mmd(phydev, 2, reg);
1185         else
1186                 newval = 0;
1187
1188         maxval = (field_sz == 4) ? 0xf : 0x1f;
1189         for (i = 0; i < numfields; i++)
1190                 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1191                         mask = 0xffff;
1192                         mask ^= maxval << (field_sz * i);
1193                         newval = (newval & mask) |
1194                                 (((val[i] / KSZ9131_STEP) & maxval)
1195                                         << (field_sz * i));
1196                 }
1197
1198         return phy_write_mmd(phydev, 2, reg, newval);
1199 }
1200
1201 #define KSZ9131RN_MMD_COMMON_CTRL_REG   2
1202 #define KSZ9131RN_RXC_DLL_CTRL          76
1203 #define KSZ9131RN_TXC_DLL_CTRL          77
1204 #define KSZ9131RN_DLL_ENABLE_DELAY      0
1205
1206 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1207 {
1208         const struct kszphy_type *type = phydev->drv->driver_data;
1209         u16 rxcdll_val, txcdll_val;
1210         int ret;
1211
1212         switch (phydev->interface) {
1213         case PHY_INTERFACE_MODE_RGMII:
1214                 rxcdll_val = type->disable_dll_rx_bit;
1215                 txcdll_val = type->disable_dll_tx_bit;
1216                 break;
1217         case PHY_INTERFACE_MODE_RGMII_ID:
1218                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1219                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1220                 break;
1221         case PHY_INTERFACE_MODE_RGMII_RXID:
1222                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1223                 txcdll_val = type->disable_dll_tx_bit;
1224                 break;
1225         case PHY_INTERFACE_MODE_RGMII_TXID:
1226                 rxcdll_val = type->disable_dll_rx_bit;
1227                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1228                 break;
1229         default:
1230                 return 0;
1231         }
1232
1233         ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1234                              KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1235                              rxcdll_val);
1236         if (ret < 0)
1237                 return ret;
1238
1239         return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1240                               KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1241                               txcdll_val);
1242 }
1243
1244 /* Silicon Errata DS80000693B
1245  *
1246  * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1247  * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1248  * according to the datasheet (off if there is no link).
1249  */
1250 static int ksz9131_led_errata(struct phy_device *phydev)
1251 {
1252         int reg;
1253
1254         reg = phy_read_mmd(phydev, 2, 0);
1255         if (reg < 0)
1256                 return reg;
1257
1258         if (!(reg & BIT(4)))
1259                 return 0;
1260
1261         return phy_set_bits(phydev, 0x1e, BIT(9));
1262 }
1263
1264 static int ksz9131_config_init(struct phy_device *phydev)
1265 {
1266         struct device_node *of_node;
1267         char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1268         char *rx_data_skews[4] = {
1269                 "rxd0-skew-psec", "rxd1-skew-psec",
1270                 "rxd2-skew-psec", "rxd3-skew-psec"
1271         };
1272         char *tx_data_skews[4] = {
1273                 "txd0-skew-psec", "txd1-skew-psec",
1274                 "txd2-skew-psec", "txd3-skew-psec"
1275         };
1276         char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1277         const struct device *dev_walker;
1278         int ret;
1279
1280         dev_walker = &phydev->mdio.dev;
1281         do {
1282                 of_node = dev_walker->of_node;
1283                 dev_walker = dev_walker->parent;
1284         } while (!of_node && dev_walker);
1285
1286         if (!of_node)
1287                 return 0;
1288
1289         if (phy_interface_is_rgmii(phydev)) {
1290                 ret = ksz9131_config_rgmii_delay(phydev);
1291                 if (ret < 0)
1292                         return ret;
1293         }
1294
1295         ret = ksz9131_of_load_skew_values(phydev, of_node,
1296                                           MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1297                                           clk_skews, 2);
1298         if (ret < 0)
1299                 return ret;
1300
1301         ret = ksz9131_of_load_skew_values(phydev, of_node,
1302                                           MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1303                                           control_skews, 2);
1304         if (ret < 0)
1305                 return ret;
1306
1307         ret = ksz9131_of_load_skew_values(phydev, of_node,
1308                                           MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1309                                           rx_data_skews, 4);
1310         if (ret < 0)
1311                 return ret;
1312
1313         ret = ksz9131_of_load_skew_values(phydev, of_node,
1314                                           MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1315                                           tx_data_skews, 4);
1316         if (ret < 0)
1317                 return ret;
1318
1319         ret = ksz9131_led_errata(phydev);
1320         if (ret < 0)
1321                 return ret;
1322
1323         return 0;
1324 }
1325
1326 #define MII_KSZ9131_AUTO_MDIX           0x1C
1327 #define MII_KSZ9131_AUTO_MDI_SET        BIT(7)
1328 #define MII_KSZ9131_AUTO_MDIX_SWAP_OFF  BIT(6)
1329
1330 static int ksz9131_mdix_update(struct phy_device *phydev)
1331 {
1332         int ret;
1333
1334         ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
1335         if (ret < 0)
1336                 return ret;
1337
1338         if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) {
1339                 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1340                         phydev->mdix_ctrl = ETH_TP_MDI;
1341                 else
1342                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1343         } else {
1344                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1345         }
1346
1347         if (ret & MII_KSZ9131_AUTO_MDI_SET)
1348                 phydev->mdix = ETH_TP_MDI;
1349         else
1350                 phydev->mdix = ETH_TP_MDI_X;
1351
1352         return 0;
1353 }
1354
1355 static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1356 {
1357         u16 val;
1358
1359         switch (ctrl) {
1360         case ETH_TP_MDI:
1361                 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1362                       MII_KSZ9131_AUTO_MDI_SET;
1363                 break;
1364         case ETH_TP_MDI_X:
1365                 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1366                 break;
1367         case ETH_TP_MDI_AUTO:
1368                 val = 0;
1369                 break;
1370         default:
1371                 return 0;
1372         }
1373
1374         return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1375                           MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1376                           MII_KSZ9131_AUTO_MDI_SET, val);
1377 }
1378
1379 static int ksz9131_read_status(struct phy_device *phydev)
1380 {
1381         int ret;
1382
1383         ret = ksz9131_mdix_update(phydev);
1384         if (ret < 0)
1385                 return ret;
1386
1387         return genphy_read_status(phydev);
1388 }
1389
1390 static int ksz9131_config_aneg(struct phy_device *phydev)
1391 {
1392         int ret;
1393
1394         ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1395         if (ret)
1396                 return ret;
1397
1398         return genphy_config_aneg(phydev);
1399 }
1400
1401 static int ksz9477_get_features(struct phy_device *phydev)
1402 {
1403         int ret;
1404
1405         ret = genphy_read_abilities(phydev);
1406         if (ret)
1407                 return ret;
1408
1409         /* The "EEE control and capability 1" (Register 3.20) seems to be
1410          * influenced by the "EEE advertisement 1" (Register 7.60). Changes
1411          * on the 7.60 will affect 3.20. So, we need to construct our own list
1412          * of caps.
1413          * KSZ8563R should have 100BaseTX/Full only.
1414          */
1415         linkmode_and(phydev->supported_eee, phydev->supported,
1416                      PHY_EEE_CAP1_FEATURES);
1417
1418         return 0;
1419 }
1420
1421 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
1422 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
1423 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
1424 static int ksz8873mll_read_status(struct phy_device *phydev)
1425 {
1426         int regval;
1427
1428         /* dummy read */
1429         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1430
1431         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1432
1433         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1434                 phydev->duplex = DUPLEX_HALF;
1435         else
1436                 phydev->duplex = DUPLEX_FULL;
1437
1438         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1439                 phydev->speed = SPEED_10;
1440         else
1441                 phydev->speed = SPEED_100;
1442
1443         phydev->link = 1;
1444         phydev->pause = phydev->asym_pause = 0;
1445
1446         return 0;
1447 }
1448
1449 static int ksz9031_get_features(struct phy_device *phydev)
1450 {
1451         int ret;
1452
1453         ret = genphy_read_abilities(phydev);
1454         if (ret < 0)
1455                 return ret;
1456
1457         /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1458          * Whenever the device's Asymmetric Pause capability is set to 1,
1459          * link-up may fail after a link-up to link-down transition.
1460          *
1461          * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1462          *
1463          * Workaround:
1464          * Do not enable the Asymmetric Pause capability bit.
1465          */
1466         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1467
1468         /* We force setting the Pause capability as the core will force the
1469          * Asymmetric Pause capability to 1 otherwise.
1470          */
1471         linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1472
1473         return 0;
1474 }
1475
1476 static int ksz9031_read_status(struct phy_device *phydev)
1477 {
1478         int err;
1479         int regval;
1480
1481         err = genphy_read_status(phydev);
1482         if (err)
1483                 return err;
1484
1485         /* Make sure the PHY is not broken. Read idle error count,
1486          * and reset the PHY if it is maxed out.
1487          */
1488         regval = phy_read(phydev, MII_STAT1000);
1489         if ((regval & 0xFF) == 0xFF) {
1490                 phy_init_hw(phydev);
1491                 phydev->link = 0;
1492                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1493                         phydev->drv->config_intr(phydev);
1494                 return genphy_config_aneg(phydev);
1495         }
1496
1497         return 0;
1498 }
1499
1500 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1501 {
1502         struct kszphy_priv *priv = phydev->priv;
1503         int ret;
1504
1505         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1506          * Prior to running the cable diagnostics, Auto-negotiation should
1507          * be disabled, full duplex set and the link speed set to 1000Mbps
1508          * via the Basic Control Register.
1509          */
1510         ret = phy_modify(phydev, MII_BMCR,
1511                          BMCR_SPEED1000 | BMCR_FULLDPLX |
1512                          BMCR_ANENABLE | BMCR_SPEED100,
1513                          BMCR_SPEED1000 | BMCR_FULLDPLX);
1514         if (ret)
1515                 return ret;
1516
1517         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1518          * The Master-Slave configuration should be set to Slave by writing
1519          * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1520          * Register.
1521          */
1522         ret = phy_read(phydev, MII_CTRL1000);
1523         if (ret < 0)
1524                 return ret;
1525
1526         /* Cache these bits, they need to be restored once LinkMD finishes. */
1527         priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1528         ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1529         ret |= CTL1000_ENABLE_MASTER;
1530
1531         return phy_write(phydev, MII_CTRL1000, ret);
1532 }
1533
1534 static int ksz9x31_cable_test_result_trans(u16 status)
1535 {
1536         switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1537         case KSZ9x31_LMD_VCT_ST_NORMAL:
1538                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1539         case KSZ9x31_LMD_VCT_ST_OPEN:
1540                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1541         case KSZ9x31_LMD_VCT_ST_SHORT:
1542                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1543         case KSZ9x31_LMD_VCT_ST_FAIL:
1544                 fallthrough;
1545         default:
1546                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1547         }
1548 }
1549
1550 static bool ksz9x31_cable_test_failed(u16 status)
1551 {
1552         int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1553
1554         return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1555 }
1556
1557 static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1558 {
1559         switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1560         case KSZ9x31_LMD_VCT_ST_OPEN:
1561                 fallthrough;
1562         case KSZ9x31_LMD_VCT_ST_SHORT:
1563                 return true;
1564         }
1565         return false;
1566 }
1567
1568 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1569 {
1570         int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1571
1572         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1573          *
1574          * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1575          */
1576         if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1577                 dt = clamp(dt - 22, 0, 255);
1578
1579         return (dt * 400) / 10;
1580 }
1581
1582 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1583 {
1584         int val, ret;
1585
1586         ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1587                                     !(val & KSZ9x31_LMD_VCT_EN),
1588                                     30000, 100000, true);
1589
1590         return ret < 0 ? ret : 0;
1591 }
1592
1593 static int ksz9x31_cable_test_get_pair(int pair)
1594 {
1595         static const int ethtool_pair[] = {
1596                 ETHTOOL_A_CABLE_PAIR_A,
1597                 ETHTOOL_A_CABLE_PAIR_B,
1598                 ETHTOOL_A_CABLE_PAIR_C,
1599                 ETHTOOL_A_CABLE_PAIR_D,
1600         };
1601
1602         return ethtool_pair[pair];
1603 }
1604
1605 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1606 {
1607         int ret, val;
1608
1609         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1610          * To test each individual cable pair, set the cable pair in the Cable
1611          * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1612          * Diagnostic Register, along with setting the Cable Diagnostics Test
1613          * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1614          * will self clear when the test is concluded.
1615          */
1616         ret = phy_write(phydev, KSZ9x31_LMD,
1617                         KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1618         if (ret)
1619                 return ret;
1620
1621         ret = ksz9x31_cable_test_wait_for_completion(phydev);
1622         if (ret)
1623                 return ret;
1624
1625         val = phy_read(phydev, KSZ9x31_LMD);
1626         if (val < 0)
1627                 return val;
1628
1629         if (ksz9x31_cable_test_failed(val))
1630                 return -EAGAIN;
1631
1632         ret = ethnl_cable_test_result(phydev,
1633                                       ksz9x31_cable_test_get_pair(pair),
1634                                       ksz9x31_cable_test_result_trans(val));
1635         if (ret)
1636                 return ret;
1637
1638         if (!ksz9x31_cable_test_fault_length_valid(val))
1639                 return 0;
1640
1641         return ethnl_cable_test_fault_length(phydev,
1642                                              ksz9x31_cable_test_get_pair(pair),
1643                                              ksz9x31_cable_test_fault_length(phydev, val));
1644 }
1645
1646 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1647                                          bool *finished)
1648 {
1649         struct kszphy_priv *priv = phydev->priv;
1650         unsigned long pair_mask = 0xf;
1651         int retries = 20;
1652         int pair, ret, rv;
1653
1654         *finished = false;
1655
1656         /* Try harder if link partner is active */
1657         while (pair_mask && retries--) {
1658                 for_each_set_bit(pair, &pair_mask, 4) {
1659                         ret = ksz9x31_cable_test_one_pair(phydev, pair);
1660                         if (ret == -EAGAIN)
1661                                 continue;
1662                         if (ret < 0)
1663                                 return ret;
1664                         clear_bit(pair, &pair_mask);
1665                 }
1666                 /* If link partner is in autonegotiation mode it will send 2ms
1667                  * of FLPs with at least 6ms of silence.
1668                  * Add 2ms sleep to have better chances to hit this silence.
1669                  */
1670                 if (pair_mask)
1671                         usleep_range(2000, 3000);
1672         }
1673
1674         /* Report remaining unfinished pair result as unknown. */
1675         for_each_set_bit(pair, &pair_mask, 4) {
1676                 ret = ethnl_cable_test_result(phydev,
1677                                               ksz9x31_cable_test_get_pair(pair),
1678                                               ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1679         }
1680
1681         *finished = true;
1682
1683         /* Restore cached bits from before LinkMD got started. */
1684         rv = phy_modify(phydev, MII_CTRL1000,
1685                         CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1686                         priv->vct_ctrl1000);
1687         if (rv)
1688                 return rv;
1689
1690         return ret;
1691 }
1692
1693 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1694 {
1695         return 0;
1696 }
1697
1698 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1699 {
1700         u16 val;
1701
1702         switch (ctrl) {
1703         case ETH_TP_MDI:
1704                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1705                 break;
1706         case ETH_TP_MDI_X:
1707                 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1708                  * counter intuitive, the "-X" in "1 = Force MDI" in the data
1709                  * sheet seems to be missing:
1710                  * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1711                  * 0 = Normal operation (transmit on TX+/TX- pins)
1712                  */
1713                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1714                 break;
1715         case ETH_TP_MDI_AUTO:
1716                 val = 0;
1717                 break;
1718         default:
1719                 return 0;
1720         }
1721
1722         return phy_modify(phydev, MII_BMCR,
1723                           KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1724                           KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1725                           KSZ886X_BMCR_HP_MDIX | val);
1726 }
1727
1728 static int ksz886x_config_aneg(struct phy_device *phydev)
1729 {
1730         int ret;
1731
1732         ret = genphy_config_aneg(phydev);
1733         if (ret)
1734                 return ret;
1735
1736         /* The MDI-X configuration is automatically changed by the PHY after
1737          * switching from autoneg off to on. So, take MDI-X configuration under
1738          * own control and set it after autoneg configuration was done.
1739          */
1740         return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1741 }
1742
1743 static int ksz886x_mdix_update(struct phy_device *phydev)
1744 {
1745         int ret;
1746
1747         ret = phy_read(phydev, MII_BMCR);
1748         if (ret < 0)
1749                 return ret;
1750
1751         if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1752                 if (ret & KSZ886X_BMCR_FORCE_MDI)
1753                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1754                 else
1755                         phydev->mdix_ctrl = ETH_TP_MDI;
1756         } else {
1757                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1758         }
1759
1760         ret = phy_read(phydev, MII_KSZPHY_CTRL);
1761         if (ret < 0)
1762                 return ret;
1763
1764         /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1765         if (ret & KSZ886X_CTRL_MDIX_STAT)
1766                 phydev->mdix = ETH_TP_MDI_X;
1767         else
1768                 phydev->mdix = ETH_TP_MDI;
1769
1770         return 0;
1771 }
1772
1773 static int ksz886x_read_status(struct phy_device *phydev)
1774 {
1775         int ret;
1776
1777         ret = ksz886x_mdix_update(phydev);
1778         if (ret < 0)
1779                 return ret;
1780
1781         return genphy_read_status(phydev);
1782 }
1783
1784 struct ksz9477_errata_write {
1785         u8 dev_addr;
1786         u8 reg_addr;
1787         u16 val;
1788 };
1789
1790 static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1791          /* Register settings are needed to improve PHY receive performance */
1792         {0x01, 0x6f, 0xdd0b},
1793         {0x01, 0x8f, 0x6032},
1794         {0x01, 0x9d, 0x248c},
1795         {0x01, 0x75, 0x0060},
1796         {0x01, 0xd3, 0x7777},
1797         {0x1c, 0x06, 0x3008},
1798         {0x1c, 0x08, 0x2000},
1799
1800         /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1801         {0x1c, 0x04, 0x00d0},
1802
1803         /* Register settings are required to meet data sheet supply current specifications */
1804         {0x1c, 0x13, 0x6eff},
1805         {0x1c, 0x14, 0xe6ff},
1806         {0x1c, 0x15, 0x6eff},
1807         {0x1c, 0x16, 0xe6ff},
1808         {0x1c, 0x17, 0x00ff},
1809         {0x1c, 0x18, 0x43ff},
1810         {0x1c, 0x19, 0xc3ff},
1811         {0x1c, 0x1a, 0x6fff},
1812         {0x1c, 0x1b, 0x07ff},
1813         {0x1c, 0x1c, 0x0fff},
1814         {0x1c, 0x1d, 0xe7ff},
1815         {0x1c, 0x1e, 0xefff},
1816         {0x1c, 0x20, 0xeeee},
1817 };
1818
1819 static int ksz9477_config_init(struct phy_device *phydev)
1820 {
1821         int err;
1822         int i;
1823
1824         /* Apply PHY settings to address errata listed in
1825          * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1826          * Silicon Errata and Data Sheet Clarification documents.
1827          *
1828          * Document notes: Before configuring the PHY MMD registers, it is
1829          * necessary to set the PHY to 100 Mbps speed with auto-negotiation
1830          * disabled by writing to register 0xN100-0xN101. After writing the
1831          * MMD registers, and after all errata workarounds that involve PHY
1832          * register settings, write register 0xN100-0xN101 again to enable
1833          * and restart auto-negotiation.
1834          */
1835         err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
1836         if (err)
1837                 return err;
1838
1839         for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
1840                 const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
1841
1842                 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1843                 if (err)
1844                         return err;
1845         }
1846
1847         /* According to KSZ9477 Errata DS80000754C (Module 4) all EEE modes
1848          * in this switch shall be regarded as broken.
1849          */
1850         if (phydev->dev_flags & MICREL_NO_EEE)
1851                 phydev->eee_broken_modes = -1;
1852
1853         err = genphy_restart_aneg(phydev);
1854         if (err)
1855                 return err;
1856
1857         return kszphy_config_init(phydev);
1858 }
1859
1860 static int kszphy_get_sset_count(struct phy_device *phydev)
1861 {
1862         return ARRAY_SIZE(kszphy_hw_stats);
1863 }
1864
1865 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1866 {
1867         int i;
1868
1869         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1870                 strscpy(data + i * ETH_GSTRING_LEN,
1871                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1872         }
1873 }
1874
1875 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1876 {
1877         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1878         struct kszphy_priv *priv = phydev->priv;
1879         int val;
1880         u64 ret;
1881
1882         val = phy_read(phydev, stat.reg);
1883         if (val < 0) {
1884                 ret = U64_MAX;
1885         } else {
1886                 val = val & ((1 << stat.bits) - 1);
1887                 priv->stats[i] += val;
1888                 ret = priv->stats[i];
1889         }
1890
1891         return ret;
1892 }
1893
1894 static void kszphy_get_stats(struct phy_device *phydev,
1895                              struct ethtool_stats *stats, u64 *data)
1896 {
1897         int i;
1898
1899         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1900                 data[i] = kszphy_get_stat(phydev, i);
1901 }
1902
1903 static int kszphy_suspend(struct phy_device *phydev)
1904 {
1905         /* Disable PHY Interrupts */
1906         if (phy_interrupt_is_valid(phydev)) {
1907                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1908                 if (phydev->drv->config_intr)
1909                         phydev->drv->config_intr(phydev);
1910         }
1911
1912         return genphy_suspend(phydev);
1913 }
1914
1915 static void kszphy_parse_led_mode(struct phy_device *phydev)
1916 {
1917         const struct kszphy_type *type = phydev->drv->driver_data;
1918         const struct device_node *np = phydev->mdio.dev.of_node;
1919         struct kszphy_priv *priv = phydev->priv;
1920         int ret;
1921
1922         if (type && type->led_mode_reg) {
1923                 ret = of_property_read_u32(np, "micrel,led-mode",
1924                                            &priv->led_mode);
1925
1926                 if (ret)
1927                         priv->led_mode = -1;
1928
1929                 if (priv->led_mode > 3) {
1930                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
1931                                    priv->led_mode);
1932                         priv->led_mode = -1;
1933                 }
1934         } else {
1935                 priv->led_mode = -1;
1936         }
1937 }
1938
1939 static int kszphy_resume(struct phy_device *phydev)
1940 {
1941         int ret;
1942
1943         genphy_resume(phydev);
1944
1945         /* After switching from power-down to normal mode, an internal global
1946          * reset is automatically generated. Wait a minimum of 1 ms before
1947          * read/write access to the PHY registers.
1948          */
1949         usleep_range(1000, 2000);
1950
1951         ret = kszphy_config_reset(phydev);
1952         if (ret)
1953                 return ret;
1954
1955         /* Enable PHY Interrupts */
1956         if (phy_interrupt_is_valid(phydev)) {
1957                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1958                 if (phydev->drv->config_intr)
1959                         phydev->drv->config_intr(phydev);
1960         }
1961
1962         return 0;
1963 }
1964
1965 static int kszphy_probe(struct phy_device *phydev)
1966 {
1967         const struct kszphy_type *type = phydev->drv->driver_data;
1968         const struct device_node *np = phydev->mdio.dev.of_node;
1969         struct kszphy_priv *priv;
1970         struct clk *clk;
1971
1972         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1973         if (!priv)
1974                 return -ENOMEM;
1975
1976         phydev->priv = priv;
1977
1978         priv->type = type;
1979
1980         kszphy_parse_led_mode(phydev);
1981
1982         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1983         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1984         if (!IS_ERR_OR_NULL(clk)) {
1985                 unsigned long rate = clk_get_rate(clk);
1986                 bool rmii_ref_clk_sel_25_mhz;
1987
1988                 if (type)
1989                         priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1990                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1991                                 "micrel,rmii-reference-clock-select-25-mhz");
1992
1993                 if (rate > 24500000 && rate < 25500000) {
1994                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1995                 } else if (rate > 49500000 && rate < 50500000) {
1996                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1997                 } else {
1998                         phydev_err(phydev, "Clock rate out of range: %ld\n",
1999                                    rate);
2000                         return -EINVAL;
2001                 }
2002         }
2003
2004         if (ksz8041_fiber_mode(phydev))
2005                 phydev->port = PORT_FIBRE;
2006
2007         /* Support legacy board-file configuration */
2008         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2009                 priv->rmii_ref_clk_sel = true;
2010                 priv->rmii_ref_clk_sel_val = true;
2011         }
2012
2013         return 0;
2014 }
2015
2016 static int lan8814_cable_test_start(struct phy_device *phydev)
2017 {
2018         /* If autoneg is enabled, we won't be able to test cross pair
2019          * short. In this case, the PHY will "detect" a link and
2020          * confuse the internal state machine - disable auto neg here.
2021          * Set the speed to 1000mbit and full duplex.
2022          */
2023         return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2024                           BMCR_SPEED1000 | BMCR_FULLDPLX);
2025 }
2026
2027 static int ksz886x_cable_test_start(struct phy_device *phydev)
2028 {
2029         if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2030                 return -EOPNOTSUPP;
2031
2032         /* If autoneg is enabled, we won't be able to test cross pair
2033          * short. In this case, the PHY will "detect" a link and
2034          * confuse the internal state machine - disable auto neg here.
2035          * If autoneg is disabled, we should set the speed to 10mbit.
2036          */
2037         return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2038 }
2039
2040 static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2041 {
2042         switch (FIELD_GET(mask, status)) {
2043         case KSZ8081_LMD_STAT_NORMAL:
2044                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2045         case KSZ8081_LMD_STAT_SHORT:
2046                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2047         case KSZ8081_LMD_STAT_OPEN:
2048                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2049         case KSZ8081_LMD_STAT_FAIL:
2050                 fallthrough;
2051         default:
2052                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2053         }
2054 }
2055
2056 static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2057 {
2058         return FIELD_GET(mask, status) ==
2059                 KSZ8081_LMD_STAT_FAIL;
2060 }
2061
2062 static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2063 {
2064         switch (FIELD_GET(mask, status)) {
2065         case KSZ8081_LMD_STAT_OPEN:
2066                 fallthrough;
2067         case KSZ8081_LMD_STAT_SHORT:
2068                 return true;
2069         }
2070         return false;
2071 }
2072
2073 static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2074                                                            u16 status, u16 data_mask)
2075 {
2076         int dt;
2077
2078         /* According to the data sheet the distance to the fault is
2079          * DELTA_TIME * 0.4 meters for ksz phys.
2080          * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2081          */
2082         dt = FIELD_GET(data_mask, status);
2083
2084         if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2085                 return ((dt - 22) * 800) / 10;
2086         else
2087                 return (dt * 400) / 10;
2088 }
2089
2090 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2091 {
2092         const struct kszphy_type *type = phydev->drv->driver_data;
2093         int val, ret;
2094
2095         ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2096                                     !(val & KSZ8081_LMD_ENABLE_TEST),
2097                                     30000, 100000, true);
2098
2099         return ret < 0 ? ret : 0;
2100 }
2101
2102 static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2103 {
2104         static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2105                                             ETHTOOL_A_CABLE_PAIR_B,
2106                                             ETHTOOL_A_CABLE_PAIR_C,
2107                                             ETHTOOL_A_CABLE_PAIR_D,
2108                                           };
2109         u32 fault_length;
2110         int ret;
2111         int val;
2112
2113         val = KSZ8081_LMD_ENABLE_TEST;
2114         val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2115
2116         ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2117         if (ret < 0)
2118                 return ret;
2119
2120         ret = ksz886x_cable_test_wait_for_completion(phydev);
2121         if (ret)
2122                 return ret;
2123
2124         val = phy_read(phydev, LAN8814_CABLE_DIAG);
2125         if (val < 0)
2126                 return val;
2127
2128         if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2129                 return -EAGAIN;
2130
2131         ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2132                                       ksz886x_cable_test_result_trans(val,
2133                                                                       LAN8814_CABLE_DIAG_STAT_MASK
2134                                                                       ));
2135         if (ret)
2136                 return ret;
2137
2138         if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2139                 return 0;
2140
2141         fault_length = ksz886x_cable_test_fault_length(phydev, val,
2142                                                        LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2143
2144         return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2145 }
2146
2147 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2148 {
2149         static const int ethtool_pair[] = {
2150                 ETHTOOL_A_CABLE_PAIR_A,
2151                 ETHTOOL_A_CABLE_PAIR_B,
2152         };
2153         int ret, val, mdix;
2154         u32 fault_length;
2155
2156         /* There is no way to choice the pair, like we do one ksz9031.
2157          * We can workaround this limitation by using the MDI-X functionality.
2158          */
2159         if (pair == 0)
2160                 mdix = ETH_TP_MDI;
2161         else
2162                 mdix = ETH_TP_MDI_X;
2163
2164         switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2165         case PHY_ID_KSZ8081:
2166                 ret = ksz8081_config_mdix(phydev, mdix);
2167                 break;
2168         case PHY_ID_KSZ886X:
2169                 ret = ksz886x_config_mdix(phydev, mdix);
2170                 break;
2171         default:
2172                 ret = -ENODEV;
2173         }
2174
2175         if (ret)
2176                 return ret;
2177
2178         /* Now we are ready to fire. This command will send a 100ns pulse
2179          * to the pair.
2180          */
2181         ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2182         if (ret)
2183                 return ret;
2184
2185         ret = ksz886x_cable_test_wait_for_completion(phydev);
2186         if (ret)
2187                 return ret;
2188
2189         val = phy_read(phydev, KSZ8081_LMD);
2190         if (val < 0)
2191                 return val;
2192
2193         if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2194                 return -EAGAIN;
2195
2196         ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2197                                       ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2198         if (ret)
2199                 return ret;
2200
2201         if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2202                 return 0;
2203
2204         fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2205
2206         return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2207 }
2208
2209 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2210                                          bool *finished)
2211 {
2212         const struct kszphy_type *type = phydev->drv->driver_data;
2213         unsigned long pair_mask = type->pair_mask;
2214         int retries = 20;
2215         int ret = 0;
2216         int pair;
2217
2218         *finished = false;
2219
2220         /* Try harder if link partner is active */
2221         while (pair_mask && retries--) {
2222                 for_each_set_bit(pair, &pair_mask, 4) {
2223                         if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2224                                 ret = lan8814_cable_test_one_pair(phydev, pair);
2225                         else
2226                                 ret = ksz886x_cable_test_one_pair(phydev, pair);
2227                         if (ret == -EAGAIN)
2228                                 continue;
2229                         if (ret < 0)
2230                                 return ret;
2231                         clear_bit(pair, &pair_mask);
2232                 }
2233                 /* If link partner is in autonegotiation mode it will send 2ms
2234                  * of FLPs with at least 6ms of silence.
2235                  * Add 2ms sleep to have better chances to hit this silence.
2236                  */
2237                 if (pair_mask)
2238                         msleep(2);
2239         }
2240
2241         *finished = true;
2242
2243         return ret;
2244 }
2245
2246 #define LAN_EXT_PAGE_ACCESS_CONTROL                     0x16
2247 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA                0x17
2248 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC                0x4000
2249
2250 #define LAN8814_QSGMII_SOFT_RESET                       0x43
2251 #define LAN8814_QSGMII_SOFT_RESET_BIT                   BIT(0)
2252 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG                0x13
2253 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA       BIT(3)
2254 #define LAN8814_ALIGN_SWAP                              0x4a
2255 #define LAN8814_ALIGN_TX_A_B_SWAP                       0x1
2256 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
2257
2258 #define LAN8804_ALIGN_SWAP                              0x4a
2259 #define LAN8804_ALIGN_TX_A_B_SWAP                       0x1
2260 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
2261 #define LAN8814_CLOCK_MANAGEMENT                        0xd
2262 #define LAN8814_LINK_QUALITY                            0x8e
2263
2264 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2265 {
2266         int data;
2267
2268         phy_lock_mdio_bus(phydev);
2269         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2270         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2271         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2272                     (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2273         data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2274         phy_unlock_mdio_bus(phydev);
2275
2276         return data;
2277 }
2278
2279 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2280                                  u16 val)
2281 {
2282         phy_lock_mdio_bus(phydev);
2283         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2284         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2285         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2286                     page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2287
2288         val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2289         if (val != 0)
2290                 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2291                            val);
2292         phy_unlock_mdio_bus(phydev);
2293         return val;
2294 }
2295
2296 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2297 {
2298         u16 val = 0;
2299
2300         if (enable)
2301                 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2302                       PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2303                       PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2304                       PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2305
2306         return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2307 }
2308
2309 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2310                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2311 {
2312         *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2313         *seconds = (*seconds << 16) |
2314                    lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2315
2316         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2317         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2318                         lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2319
2320         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2321 }
2322
2323 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2324                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2325 {
2326         *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2327         *seconds = *seconds << 16 |
2328                    lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2329
2330         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2331         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2332                         lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2333
2334         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2335 }
2336
2337 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2338 {
2339         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2340         struct phy_device *phydev = ptp_priv->phydev;
2341         struct lan8814_shared_priv *shared = phydev->shared->priv;
2342
2343         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2344                                 SOF_TIMESTAMPING_RX_HARDWARE |
2345                                 SOF_TIMESTAMPING_RAW_HARDWARE;
2346
2347         info->phc_index = ptp_clock_index(shared->ptp_clock);
2348
2349         info->tx_types =
2350                 (1 << HWTSTAMP_TX_OFF) |
2351                 (1 << HWTSTAMP_TX_ON) |
2352                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2353
2354         info->rx_filters =
2355                 (1 << HWTSTAMP_FILTER_NONE) |
2356                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2357                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2358                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2359                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2360
2361         return 0;
2362 }
2363
2364 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2365 {
2366         int i;
2367
2368         for (i = 0; i < FIFO_SIZE; ++i)
2369                 lanphy_read_page_reg(phydev, 5,
2370                                      egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2371
2372         /* Read to clear overflow status bit */
2373         lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2374 }
2375
2376 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
2377 {
2378         struct kszphy_ptp_priv *ptp_priv =
2379                           container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2380         struct phy_device *phydev = ptp_priv->phydev;
2381         struct lan8814_shared_priv *shared = phydev->shared->priv;
2382         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2383         struct hwtstamp_config config;
2384         int txcfg = 0, rxcfg = 0;
2385         int pkt_ts_enable;
2386
2387         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2388                 return -EFAULT;
2389
2390         ptp_priv->hwts_tx_type = config.tx_type;
2391         ptp_priv->rx_filter = config.rx_filter;
2392
2393         switch (config.rx_filter) {
2394         case HWTSTAMP_FILTER_NONE:
2395                 ptp_priv->layer = 0;
2396                 ptp_priv->version = 0;
2397                 break;
2398         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2399         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2400         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2401                 ptp_priv->layer = PTP_CLASS_L4;
2402                 ptp_priv->version = PTP_CLASS_V2;
2403                 break;
2404         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2405         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2406         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2407                 ptp_priv->layer = PTP_CLASS_L2;
2408                 ptp_priv->version = PTP_CLASS_V2;
2409                 break;
2410         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2411         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2412         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2413                 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2414                 ptp_priv->version = PTP_CLASS_V2;
2415                 break;
2416         default:
2417                 return -ERANGE;
2418         }
2419
2420         if (ptp_priv->layer & PTP_CLASS_L2) {
2421                 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2422                 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2423         } else if (ptp_priv->layer & PTP_CLASS_L4) {
2424                 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2425                 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2426         }
2427         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2428         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2429
2430         pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2431                         PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2432         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2433         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2434
2435         if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
2436                 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2437                                       PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2438
2439         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2440                 lan8814_config_ts_intr(ptp_priv->phydev, true);
2441         else
2442                 lan8814_config_ts_intr(ptp_priv->phydev, false);
2443
2444         mutex_lock(&shared->shared_lock);
2445         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2446                 shared->ref++;
2447         else
2448                 shared->ref--;
2449
2450         if (shared->ref)
2451                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2452                                       PTP_CMD_CTL_PTP_ENABLE_);
2453         else
2454                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2455                                       PTP_CMD_CTL_PTP_DISABLE_);
2456         mutex_unlock(&shared->shared_lock);
2457
2458         /* In case of multiple starts and stops, these needs to be cleared */
2459         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2460                 list_del(&rx_ts->list);
2461                 kfree(rx_ts);
2462         }
2463         skb_queue_purge(&ptp_priv->rx_queue);
2464         skb_queue_purge(&ptp_priv->tx_queue);
2465
2466         lan8814_flush_fifo(ptp_priv->phydev, false);
2467         lan8814_flush_fifo(ptp_priv->phydev, true);
2468
2469         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
2470 }
2471
2472 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2473                              struct sk_buff *skb, int type)
2474 {
2475         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2476
2477         switch (ptp_priv->hwts_tx_type) {
2478         case HWTSTAMP_TX_ONESTEP_SYNC:
2479                 if (ptp_msg_is_sync(skb, type)) {
2480                         kfree_skb(skb);
2481                         return;
2482                 }
2483                 fallthrough;
2484         case HWTSTAMP_TX_ON:
2485                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2486                 skb_queue_tail(&ptp_priv->tx_queue, skb);
2487                 break;
2488         case HWTSTAMP_TX_OFF:
2489         default:
2490                 kfree_skb(skb);
2491                 break;
2492         }
2493 }
2494
2495 static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2496 {
2497         struct ptp_header *ptp_header;
2498         u32 type;
2499
2500         skb_push(skb, ETH_HLEN);
2501         type = ptp_classify_raw(skb);
2502         ptp_header = ptp_parse_header(skb, type);
2503         skb_pull_inline(skb, ETH_HLEN);
2504
2505         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2506 }
2507
2508 static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2509                                  struct sk_buff *skb)
2510 {
2511         struct skb_shared_hwtstamps *shhwtstamps;
2512         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2513         unsigned long flags;
2514         bool ret = false;
2515         u16 skb_sig;
2516
2517         lan8814_get_sig_rx(skb, &skb_sig);
2518
2519         /* Iterate over all RX timestamps and match it with the received skbs */
2520         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2521         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2522                 /* Check if we found the signature we were looking for. */
2523                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2524                         continue;
2525
2526                 shhwtstamps = skb_hwtstamps(skb);
2527                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2528                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2529                                                   rx_ts->nsec);
2530                 list_del(&rx_ts->list);
2531                 kfree(rx_ts);
2532
2533                 ret = true;
2534                 break;
2535         }
2536         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2537
2538         if (ret)
2539                 netif_rx(skb);
2540         return ret;
2541 }
2542
2543 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2544 {
2545         struct kszphy_ptp_priv *ptp_priv =
2546                         container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2547
2548         if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2549             type == PTP_CLASS_NONE)
2550                 return false;
2551
2552         if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2553                 return false;
2554
2555         /* If we failed to match then add it to the queue for when the timestamp
2556          * will come
2557          */
2558         if (!lan8814_match_rx_skb(ptp_priv, skb))
2559                 skb_queue_tail(&ptp_priv->rx_queue, skb);
2560
2561         return true;
2562 }
2563
2564 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2565                                   u32 seconds, u32 nano_seconds)
2566 {
2567         u32 sec_low, sec_high, nsec_low, nsec_high;
2568
2569         sec_low = seconds & 0xffff;
2570         sec_high = (seconds >> 16) & 0xffff;
2571         nsec_low = nano_seconds & 0xffff;
2572         nsec_high = (nano_seconds >> 16) & 0x3fff;
2573
2574         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2575         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2576         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2577         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2578
2579         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2580 }
2581
2582 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2583                                   u32 *seconds, u32 *nano_seconds)
2584 {
2585         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2586
2587         *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2588         *seconds = (*seconds << 16) |
2589                    lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2590
2591         *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2592         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2593                         lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2594 }
2595
2596 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2597                                    struct timespec64 *ts)
2598 {
2599         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2600                                                           ptp_clock_info);
2601         struct phy_device *phydev = shared->phydev;
2602         u32 nano_seconds;
2603         u32 seconds;
2604
2605         mutex_lock(&shared->shared_lock);
2606         lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2607         mutex_unlock(&shared->shared_lock);
2608         ts->tv_sec = seconds;
2609         ts->tv_nsec = nano_seconds;
2610
2611         return 0;
2612 }
2613
2614 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2615                                    const struct timespec64 *ts)
2616 {
2617         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2618                                                           ptp_clock_info);
2619         struct phy_device *phydev = shared->phydev;
2620
2621         mutex_lock(&shared->shared_lock);
2622         lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2623         mutex_unlock(&shared->shared_lock);
2624
2625         return 0;
2626 }
2627
2628 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2629                                    s64 time_step_ns)
2630 {
2631         u32 nano_seconds_step;
2632         u64 abs_time_step_ns;
2633         u32 unsigned_seconds;
2634         u32 nano_seconds;
2635         u32 remainder;
2636         s32 seconds;
2637
2638         if (time_step_ns >  15000000000LL) {
2639                 /* convert to clock set */
2640                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2641                 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2642                                                 &remainder);
2643                 nano_seconds += remainder;
2644                 if (nano_seconds >= 1000000000) {
2645                         unsigned_seconds++;
2646                         nano_seconds -= 1000000000;
2647                 }
2648                 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2649                 return;
2650         } else if (time_step_ns < -15000000000LL) {
2651                 /* convert to clock set */
2652                 time_step_ns = -time_step_ns;
2653
2654                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2655                 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2656                                                 &remainder);
2657                 nano_seconds_step = remainder;
2658                 if (nano_seconds < nano_seconds_step) {
2659                         unsigned_seconds--;
2660                         nano_seconds += 1000000000;
2661                 }
2662                 nano_seconds -= nano_seconds_step;
2663                 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2664                                       nano_seconds);
2665                 return;
2666         }
2667
2668         /* do clock step */
2669         if (time_step_ns >= 0) {
2670                 abs_time_step_ns = (u64)time_step_ns;
2671                 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2672                                            &remainder);
2673                 nano_seconds = remainder;
2674         } else {
2675                 abs_time_step_ns = (u64)(-time_step_ns);
2676                 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2677                             &remainder));
2678                 nano_seconds = remainder;
2679                 if (nano_seconds > 0) {
2680                         /* subtracting nano seconds is not allowed
2681                          * convert to subtracting from seconds,
2682                          * and adding to nanoseconds
2683                          */
2684                         seconds--;
2685                         nano_seconds = (1000000000 - nano_seconds);
2686                 }
2687         }
2688
2689         if (nano_seconds > 0) {
2690                 /* add 8 ns to cover the likely normal increment */
2691                 nano_seconds += 8;
2692         }
2693
2694         if (nano_seconds >= 1000000000) {
2695                 /* carry into seconds */
2696                 seconds++;
2697                 nano_seconds -= 1000000000;
2698         }
2699
2700         while (seconds) {
2701                 if (seconds > 0) {
2702                         u32 adjustment_value = (u32)seconds;
2703                         u16 adjustment_value_lo, adjustment_value_hi;
2704
2705                         if (adjustment_value > 0xF)
2706                                 adjustment_value = 0xF;
2707
2708                         adjustment_value_lo = adjustment_value & 0xffff;
2709                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2710
2711                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2712                                               adjustment_value_lo);
2713                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2714                                               PTP_LTC_STEP_ADJ_DIR_ |
2715                                               adjustment_value_hi);
2716                         seconds -= ((s32)adjustment_value);
2717                 } else {
2718                         u32 adjustment_value = (u32)(-seconds);
2719                         u16 adjustment_value_lo, adjustment_value_hi;
2720
2721                         if (adjustment_value > 0xF)
2722                                 adjustment_value = 0xF;
2723
2724                         adjustment_value_lo = adjustment_value & 0xffff;
2725                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2726
2727                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2728                                               adjustment_value_lo);
2729                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2730                                               adjustment_value_hi);
2731                         seconds += ((s32)adjustment_value);
2732                 }
2733                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2734                                       PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2735         }
2736         if (nano_seconds) {
2737                 u16 nano_seconds_lo;
2738                 u16 nano_seconds_hi;
2739
2740                 nano_seconds_lo = nano_seconds & 0xffff;
2741                 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2742
2743                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2744                                       nano_seconds_lo);
2745                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2746                                       PTP_LTC_STEP_ADJ_DIR_ |
2747                                       nano_seconds_hi);
2748                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2749                                       PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2750         }
2751 }
2752
2753 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2754 {
2755         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2756                                                           ptp_clock_info);
2757         struct phy_device *phydev = shared->phydev;
2758
2759         mutex_lock(&shared->shared_lock);
2760         lan8814_ptp_clock_step(phydev, delta);
2761         mutex_unlock(&shared->shared_lock);
2762
2763         return 0;
2764 }
2765
2766 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2767 {
2768         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2769                                                           ptp_clock_info);
2770         struct phy_device *phydev = shared->phydev;
2771         u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2772         bool positive = true;
2773         u32 kszphy_rate_adj;
2774
2775         if (scaled_ppm < 0) {
2776                 scaled_ppm = -scaled_ppm;
2777                 positive = false;
2778         }
2779
2780         kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2781         kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2782
2783         kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2784         kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2785
2786         if (positive)
2787                 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2788
2789         mutex_lock(&shared->shared_lock);
2790         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2791         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2792         mutex_unlock(&shared->shared_lock);
2793
2794         return 0;
2795 }
2796
2797 static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2798 {
2799         struct ptp_header *ptp_header;
2800         u32 type;
2801
2802         type = ptp_classify_raw(skb);
2803         ptp_header = ptp_parse_header(skb, type);
2804
2805         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2806 }
2807
2808 static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
2809                                  u32 seconds, u32 nsec, u16 seq_id)
2810 {
2811         struct skb_shared_hwtstamps shhwtstamps;
2812         struct sk_buff *skb, *skb_tmp;
2813         unsigned long flags;
2814         bool ret = false;
2815         u16 skb_sig;
2816
2817         spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2818         skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2819                 lan8814_get_sig_tx(skb, &skb_sig);
2820
2821                 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2822                         continue;
2823
2824                 __skb_unlink(skb, &ptp_priv->tx_queue);
2825                 ret = true;
2826                 break;
2827         }
2828         spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2829
2830         if (ret) {
2831                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2832                 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2833                 skb_complete_tx_timestamp(skb, &shhwtstamps);
2834         }
2835 }
2836
2837 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2838 {
2839         struct phy_device *phydev = ptp_priv->phydev;
2840         u32 seconds, nsec;
2841         u16 seq_id;
2842
2843         lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2844         lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
2845 }
2846
2847 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2848 {
2849         struct phy_device *phydev = ptp_priv->phydev;
2850         u32 reg;
2851
2852         do {
2853                 lan8814_dequeue_tx_skb(ptp_priv);
2854
2855                 /* If other timestamps are available in the FIFO,
2856                  * process them.
2857                  */
2858                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2859         } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2860 }
2861
2862 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2863                               struct lan8814_ptp_rx_ts *rx_ts)
2864 {
2865         struct skb_shared_hwtstamps *shhwtstamps;
2866         struct sk_buff *skb, *skb_tmp;
2867         unsigned long flags;
2868         bool ret = false;
2869         u16 skb_sig;
2870
2871         spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2872         skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2873                 lan8814_get_sig_rx(skb, &skb_sig);
2874
2875                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2876                         continue;
2877
2878                 __skb_unlink(skb, &ptp_priv->rx_queue);
2879
2880                 ret = true;
2881                 break;
2882         }
2883         spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2884
2885         if (ret) {
2886                 shhwtstamps = skb_hwtstamps(skb);
2887                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2888                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2889                 netif_rx(skb);
2890         }
2891
2892         return ret;
2893 }
2894
2895 static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2896                                 struct lan8814_ptp_rx_ts *rx_ts)
2897 {
2898         unsigned long flags;
2899
2900         /* If we failed to match the skb add it to the queue for when
2901          * the frame will come
2902          */
2903         if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2904                 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2905                 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2906                 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2907         } else {
2908                 kfree(rx_ts);
2909         }
2910 }
2911
2912 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2913 {
2914         struct phy_device *phydev = ptp_priv->phydev;
2915         struct lan8814_ptp_rx_ts *rx_ts;
2916         u32 reg;
2917
2918         do {
2919                 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2920                 if (!rx_ts)
2921                         return;
2922
2923                 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2924                                       &rx_ts->seq_id);
2925                 lan8814_match_rx_ts(ptp_priv, rx_ts);
2926
2927                 /* If other timestamps are available in the FIFO,
2928                  * process them.
2929                  */
2930                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2931         } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2932 }
2933
2934 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
2935 {
2936         struct kszphy_priv *priv = phydev->priv;
2937         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2938
2939         if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2940                 lan8814_get_tx_ts(ptp_priv);
2941
2942         if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2943                 lan8814_get_rx_ts(ptp_priv);
2944
2945         if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2946                 lan8814_flush_fifo(phydev, true);
2947                 skb_queue_purge(&ptp_priv->tx_queue);
2948         }
2949
2950         if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2951                 lan8814_flush_fifo(phydev, false);
2952                 skb_queue_purge(&ptp_priv->rx_queue);
2953         }
2954 }
2955
2956 static int lan8804_config_init(struct phy_device *phydev)
2957 {
2958         int val;
2959
2960         /* MDI-X setting for swap A,B transmit */
2961         val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2962         val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2963         val |= LAN8804_ALIGN_TX_A_B_SWAP;
2964         lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2965
2966         /* Make sure that the PHY will not stop generating the clock when the
2967          * link partner goes down
2968          */
2969         lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2970         lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2971
2972         return 0;
2973 }
2974
2975 static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
2976 {
2977         int status;
2978
2979         status = phy_read(phydev, LAN8814_INTS);
2980         if (status < 0) {
2981                 phy_error(phydev);
2982                 return IRQ_NONE;
2983         }
2984
2985         if (status > 0)
2986                 phy_trigger_machine(phydev);
2987
2988         return IRQ_HANDLED;
2989 }
2990
2991 #define LAN8804_OUTPUT_CONTROL                  25
2992 #define LAN8804_OUTPUT_CONTROL_INTR_BUFFER      BIT(14)
2993 #define LAN8804_CONTROL                         31
2994 #define LAN8804_CONTROL_INTR_POLARITY           BIT(14)
2995
2996 static int lan8804_config_intr(struct phy_device *phydev)
2997 {
2998         int err;
2999
3000         /* This is an internal PHY of lan966x and is not possible to change the
3001          * polarity on the GIC found in lan966x, therefore change the polarity
3002          * of the interrupt in the PHY from being active low instead of active
3003          * high.
3004          */
3005         phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3006
3007         /* By default interrupt buffer is open-drain in which case the interrupt
3008          * can be active only low. Therefore change the interrupt buffer to be
3009          * push-pull to be able to change interrupt polarity
3010          */
3011         phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3012                   LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3013
3014         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3015                 err = phy_read(phydev, LAN8814_INTS);
3016                 if (err < 0)
3017                         return err;
3018
3019                 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3020                 if (err)
3021                         return err;
3022         } else {
3023                 err = phy_write(phydev, LAN8814_INTC, 0);
3024                 if (err)
3025                         return err;
3026
3027                 err = phy_read(phydev, LAN8814_INTS);
3028                 if (err < 0)
3029                         return err;
3030         }
3031
3032         return 0;
3033 }
3034
3035 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3036 {
3037         int ret = IRQ_NONE;
3038         int irq_status;
3039
3040         irq_status = phy_read(phydev, LAN8814_INTS);
3041         if (irq_status < 0) {
3042                 phy_error(phydev);
3043                 return IRQ_NONE;
3044         }
3045
3046         if (irq_status & LAN8814_INT_LINK) {
3047                 phy_trigger_machine(phydev);
3048                 ret = IRQ_HANDLED;
3049         }
3050
3051         while (true) {
3052                 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3053                 if (!irq_status)
3054                         break;
3055
3056                 lan8814_handle_ptp_interrupt(phydev, irq_status);
3057                 ret = IRQ_HANDLED;
3058         }
3059
3060         return ret;
3061 }
3062
3063 static int lan8814_ack_interrupt(struct phy_device *phydev)
3064 {
3065         /* bit[12..0] int status, which is a read and clear register. */
3066         int rc;
3067
3068         rc = phy_read(phydev, LAN8814_INTS);
3069
3070         return (rc < 0) ? rc : 0;
3071 }
3072
3073 static int lan8814_config_intr(struct phy_device *phydev)
3074 {
3075         int err;
3076
3077         lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3078                               LAN8814_INTR_CTRL_REG_POLARITY |
3079                               LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3080
3081         /* enable / disable interrupts */
3082         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3083                 err = lan8814_ack_interrupt(phydev);
3084                 if (err)
3085                         return err;
3086
3087                 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3088         } else {
3089                 err = phy_write(phydev, LAN8814_INTC, 0);
3090                 if (err)
3091                         return err;
3092
3093                 err = lan8814_ack_interrupt(phydev);
3094         }
3095
3096         return err;
3097 }
3098
3099 static void lan8814_ptp_init(struct phy_device *phydev)
3100 {
3101         struct kszphy_priv *priv = phydev->priv;
3102         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3103         u32 temp;
3104
3105         if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3106             !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3107                 return;
3108
3109         lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3110
3111         temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3112         temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3113         lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3114
3115         temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3116         temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3117         lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3118
3119         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3120         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3121
3122         /* Removing default registers configs related to L2 and IP */
3123         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3124         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3125         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3126         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3127
3128         skb_queue_head_init(&ptp_priv->tx_queue);
3129         skb_queue_head_init(&ptp_priv->rx_queue);
3130         INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3131         spin_lock_init(&ptp_priv->rx_ts_lock);
3132
3133         ptp_priv->phydev = phydev;
3134
3135         ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3136         ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3137         ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3138         ptp_priv->mii_ts.ts_info  = lan8814_ts_info;
3139
3140         phydev->mii_ts = &ptp_priv->mii_ts;
3141 }
3142
3143 static int lan8814_ptp_probe_once(struct phy_device *phydev)
3144 {
3145         struct lan8814_shared_priv *shared = phydev->shared->priv;
3146
3147         /* Initialise shared lock for clock*/
3148         mutex_init(&shared->shared_lock);
3149
3150         shared->ptp_clock_info.owner = THIS_MODULE;
3151         snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3152         shared->ptp_clock_info.max_adj = 31249999;
3153         shared->ptp_clock_info.n_alarm = 0;
3154         shared->ptp_clock_info.n_ext_ts = 0;
3155         shared->ptp_clock_info.n_pins = 0;
3156         shared->ptp_clock_info.pps = 0;
3157         shared->ptp_clock_info.pin_config = NULL;
3158         shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3159         shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3160         shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3161         shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3162         shared->ptp_clock_info.getcrosststamp = NULL;
3163
3164         shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3165                                                &phydev->mdio.dev);
3166         if (IS_ERR(shared->ptp_clock)) {
3167                 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3168                            PTR_ERR(shared->ptp_clock));
3169                 return -EINVAL;
3170         }
3171
3172         /* Check if PHC support is missing at the configuration level */
3173         if (!shared->ptp_clock)
3174                 return 0;
3175
3176         phydev_dbg(phydev, "successfully registered ptp clock\n");
3177
3178         shared->phydev = phydev;
3179
3180         /* The EP.4 is shared between all the PHYs in the package and also it
3181          * can be accessed by any of the PHYs
3182          */
3183         lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3184         lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3185                               PTP_OPERATING_MODE_STANDALONE_);
3186
3187         return 0;
3188 }
3189
3190 static void lan8814_setup_led(struct phy_device *phydev, int val)
3191 {
3192         int temp;
3193
3194         temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3195
3196         if (val)
3197                 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3198         else
3199                 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3200
3201         lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3202 }
3203
3204 static int lan8814_config_init(struct phy_device *phydev)
3205 {
3206         struct kszphy_priv *lan8814 = phydev->priv;
3207         int val;
3208
3209         /* Reset the PHY */
3210         val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3211         val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3212         lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3213
3214         /* Disable ANEG with QSGMII PCS Host side */
3215         val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3216         val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3217         lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3218
3219         /* MDI-X setting for swap A,B transmit */
3220         val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3221         val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3222         val |= LAN8814_ALIGN_TX_A_B_SWAP;
3223         lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3224
3225         if (lan8814->led_mode >= 0)
3226                 lan8814_setup_led(phydev, lan8814->led_mode);
3227
3228         return 0;
3229 }
3230
3231 /* It is expected that there will not be any 'lan8814_take_coma_mode'
3232  * function called in suspend. Because the GPIO line can be shared, so if one of
3233  * the phys goes back in coma mode, then all the other PHYs will go, which is
3234  * wrong.
3235  */
3236 static int lan8814_release_coma_mode(struct phy_device *phydev)
3237 {
3238         struct gpio_desc *gpiod;
3239
3240         gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3241                                         GPIOD_OUT_HIGH_OPEN_DRAIN |
3242                                         GPIOD_FLAGS_BIT_NONEXCLUSIVE);
3243         if (IS_ERR(gpiod))
3244                 return PTR_ERR(gpiod);
3245
3246         gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
3247         gpiod_set_value_cansleep(gpiod, 0);
3248
3249         return 0;
3250 }
3251
3252 static int lan8814_probe(struct phy_device *phydev)
3253 {
3254         const struct kszphy_type *type = phydev->drv->driver_data;
3255         struct kszphy_priv *priv;
3256         u16 addr;
3257         int err;
3258
3259         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3260         if (!priv)
3261                 return -ENOMEM;
3262
3263         phydev->priv = priv;
3264
3265         priv->type = type;
3266
3267         kszphy_parse_led_mode(phydev);
3268
3269         /* Strap-in value for PHY address, below register read gives starting
3270          * phy address value
3271          */
3272         addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
3273         devm_phy_package_join(&phydev->mdio.dev, phydev,
3274                               addr, sizeof(struct lan8814_shared_priv));
3275
3276         if (phy_package_init_once(phydev)) {
3277                 err = lan8814_release_coma_mode(phydev);
3278                 if (err)
3279                         return err;
3280
3281                 err = lan8814_ptp_probe_once(phydev);
3282                 if (err)
3283                         return err;
3284         }
3285
3286         lan8814_ptp_init(phydev);
3287
3288         return 0;
3289 }
3290
3291 #define LAN8841_MMD_TIMER_REG                   0
3292 #define LAN8841_MMD0_REGISTER_17                17
3293 #define LAN8841_MMD0_REGISTER_17_DROP_OPT(x)    ((x) & 0x3)
3294 #define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS        BIT(3)
3295 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG   2
3296 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK   BIT(14)
3297 #define LAN8841_MMD_ANALOG_REG                  28
3298 #define LAN8841_ANALOG_CONTROL_1                1
3299 #define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x)    (((x) & 0x3) << 5)
3300 #define LAN8841_ANALOG_CONTROL_10               13
3301 #define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x)    ((x) & 0x3)
3302 #define LAN8841_ANALOG_CONTROL_11               14
3303 #define LAN8841_ANALOG_CONTROL_11_LDO_REF(x)    (((x) & 0x7) << 12)
3304 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
3305 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
3306 #define LAN8841_BTRX_POWER_DOWN                 70
3307 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A      BIT(0)
3308 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A       BIT(1)
3309 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B      BIT(2)
3310 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B       BIT(3)
3311 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C       BIT(5)
3312 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D       BIT(7)
3313 #define LAN8841_ADC_CHANNEL_MASK                198
3314 #define LAN8841_PTP_RX_PARSE_L2_ADDR_EN         370
3315 #define LAN8841_PTP_RX_PARSE_IP_ADDR_EN         371
3316 #define LAN8841_PTP_TX_PARSE_L2_ADDR_EN         434
3317 #define LAN8841_PTP_TX_PARSE_IP_ADDR_EN         435
3318 #define LAN8841_PTP_CMD_CTL                     256
3319 #define LAN8841_PTP_CMD_CTL_PTP_ENABLE          BIT(2)
3320 #define LAN8841_PTP_CMD_CTL_PTP_DISABLE         BIT(1)
3321 #define LAN8841_PTP_CMD_CTL_PTP_RESET           BIT(0)
3322 #define LAN8841_PTP_RX_PARSE_CONFIG             368
3323 #define LAN8841_PTP_TX_PARSE_CONFIG             432
3324 #define LAN8841_PTP_RX_MODE                     381
3325 #define LAN8841_PTP_INSERT_TS_EN                BIT(0)
3326 #define LAN8841_PTP_INSERT_TS_32BIT             BIT(1)
3327
3328 static int lan8841_config_init(struct phy_device *phydev)
3329 {
3330         int ret;
3331
3332         ret = ksz9131_config_init(phydev);
3333         if (ret)
3334                 return ret;
3335
3336         /* Initialize the HW by resetting everything */
3337         phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3338                        LAN8841_PTP_CMD_CTL,
3339                        LAN8841_PTP_CMD_CTL_PTP_RESET,
3340                        LAN8841_PTP_CMD_CTL_PTP_RESET);
3341
3342         phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3343                        LAN8841_PTP_CMD_CTL,
3344                        LAN8841_PTP_CMD_CTL_PTP_ENABLE,
3345                        LAN8841_PTP_CMD_CTL_PTP_ENABLE);
3346
3347         /* Don't process any frames */
3348         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3349                       LAN8841_PTP_RX_PARSE_CONFIG, 0);
3350         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3351                       LAN8841_PTP_TX_PARSE_CONFIG, 0);
3352         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3353                       LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
3354         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3355                       LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
3356         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3357                       LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
3358         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3359                       LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
3360
3361         /* 100BT Clause 40 improvenent errata */
3362         phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3363                       LAN8841_ANALOG_CONTROL_1,
3364                       LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
3365         phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3366                       LAN8841_ANALOG_CONTROL_10,
3367                       LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
3368
3369         /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
3370          * Magnetics
3371          */
3372         ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3373                            LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
3374         if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
3375                 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3376                               LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
3377                               LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
3378                 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3379                               LAN8841_BTRX_POWER_DOWN,
3380                               LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
3381                               LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
3382                               LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
3383                               LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
3384                               LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
3385                               LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
3386         }
3387
3388         /* LDO Adjustment errata */
3389         phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3390                       LAN8841_ANALOG_CONTROL_11,
3391                       LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
3392
3393         /* 100BT RGMII latency tuning errata */
3394         phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
3395                       LAN8841_ADC_CHANNEL_MASK, 0x0);
3396         phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
3397                       LAN8841_MMD0_REGISTER_17,
3398                       LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
3399                       LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
3400
3401         return 0;
3402 }
3403
3404 #define LAN8841_OUTPUT_CTRL                     25
3405 #define LAN8841_OUTPUT_CTRL_INT_BUFFER          BIT(14)
3406 #define LAN8841_INT_PTP                         BIT(9)
3407
3408 static int lan8841_config_intr(struct phy_device *phydev)
3409 {
3410         int err;
3411
3412         phy_modify(phydev, LAN8841_OUTPUT_CTRL,
3413                    LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
3414
3415         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3416                 err = phy_read(phydev, LAN8814_INTS);
3417                 if (err)
3418                         return err;
3419
3420                 /* Enable / disable interrupts. It is OK to enable PTP interrupt
3421                  * even if it PTP is not enabled. Because the underneath blocks
3422                  * will not enable the PTP so we will never get the PTP
3423                  * interrupt.
3424                  */
3425                 err = phy_write(phydev, LAN8814_INTC,
3426                                 LAN8814_INT_LINK | LAN8841_INT_PTP);
3427         } else {
3428                 err = phy_write(phydev, LAN8814_INTC, 0);
3429                 if (err)
3430                         return err;
3431
3432                 err = phy_read(phydev, LAN8814_INTS);
3433         }
3434
3435         return err;
3436 }
3437
3438 #define LAN8841_PTP_TX_EGRESS_SEC_LO                    453
3439 #define LAN8841_PTP_TX_EGRESS_SEC_HI                    452
3440 #define LAN8841_PTP_TX_EGRESS_NS_LO                     451
3441 #define LAN8841_PTP_TX_EGRESS_NS_HI                     450
3442 #define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID             BIT(15)
3443 #define LAN8841_PTP_TX_MSG_HEADER2                      455
3444
3445 static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
3446                                   u32 *sec, u32 *nsec, u16 *seq)
3447 {
3448         struct phy_device *phydev = ptp_priv->phydev;
3449
3450         *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
3451         if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
3452                 return false;
3453
3454         *nsec = ((*nsec & 0x3fff) << 16);
3455         *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
3456
3457         *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
3458         *sec = *sec << 16;
3459         *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
3460
3461         *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3462
3463         return true;
3464 }
3465
3466 static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3467 {
3468         u32 sec, nsec;
3469         u16 seq;
3470
3471         while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))
3472                 lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);
3473 }
3474
3475 #define LAN8841_PTP_INT_STS                     259
3476 #define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
3477 #define LAN8841_PTP_INT_STS_PTP_TX_TS_INT       BIT(12)
3478 #define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT    BIT(2)
3479
3480 static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
3481 {
3482         struct phy_device *phydev = ptp_priv->phydev;
3483         int i;
3484
3485         for (i = 0; i < FIFO_SIZE; ++i)
3486                 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3487
3488         phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3489 }
3490
3491 #define LAN8841_PTP_GPIO_CAP_STS                        506
3492 #define LAN8841_PTP_GPIO_SEL                            327
3493 #define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio)             ((gpio) << 8)
3494 #define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP              498
3495 #define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP              499
3496 #define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP               500
3497 #define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP               501
3498 #define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP              502
3499 #define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP              503
3500 #define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP               504
3501 #define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP               505
3502
3503 static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
3504 {
3505         struct phy_device *phydev = ptp_priv->phydev;
3506         struct ptp_clock_event ptp_event = {0};
3507         int pin, ret, tmp;
3508         s32 sec, nsec;
3509
3510         pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);
3511         if (pin == -1)
3512                 return;
3513
3514         tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
3515         if (tmp < 0)
3516                 return;
3517
3518         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
3519                             LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
3520         if (ret)
3521                 return;
3522
3523         mutex_lock(&ptp_priv->ptp_lock);
3524         if (tmp & BIT(pin)) {
3525                 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
3526                 sec <<= 16;
3527                 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
3528
3529                 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3530                 nsec <<= 16;
3531                 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
3532         } else {
3533                 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
3534                 sec <<= 16;
3535                 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
3536
3537                 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3538                 nsec <<= 16;
3539                 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
3540         }
3541         mutex_unlock(&ptp_priv->ptp_lock);
3542         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
3543         if (ret)
3544                 return;
3545
3546         ptp_event.index = 0;
3547         ptp_event.timestamp = ktime_set(sec, nsec);
3548         ptp_event.type = PTP_CLOCK_EXTTS;
3549         ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);
3550 }
3551
3552 static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
3553 {
3554         struct kszphy_priv *priv = phydev->priv;
3555         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3556         u16 status;
3557
3558         do {
3559                 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3560
3561                 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
3562                         lan8841_ptp_process_tx_ts(ptp_priv);
3563
3564                 if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
3565                         lan8841_gpio_process_cap(ptp_priv);
3566
3567                 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
3568                         lan8841_ptp_flush_fifo(ptp_priv);
3569                         skb_queue_purge(&ptp_priv->tx_queue);
3570                 }
3571
3572         } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
3573                            LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
3574                            LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
3575 }
3576
3577 #define LAN8841_INTS_PTP                BIT(9)
3578
3579 static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
3580 {
3581         irqreturn_t ret = IRQ_NONE;
3582         int irq_status;
3583
3584         irq_status = phy_read(phydev, LAN8814_INTS);
3585         if (irq_status < 0) {
3586                 phy_error(phydev);
3587                 return IRQ_NONE;
3588         }
3589
3590         if (irq_status & LAN8814_INT_LINK) {
3591                 phy_trigger_machine(phydev);
3592                 ret = IRQ_HANDLED;
3593         }
3594
3595         if (irq_status & LAN8841_INTS_PTP) {
3596                 lan8841_handle_ptp_interrupt(phydev);
3597                 ret = IRQ_HANDLED;
3598         }
3599
3600         return ret;
3601 }
3602
3603 static int lan8841_ts_info(struct mii_timestamper *mii_ts,
3604                            struct ethtool_ts_info *info)
3605 {
3606         struct kszphy_ptp_priv *ptp_priv;
3607
3608         ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3609
3610         info->phc_index = ptp_priv->ptp_clock ?
3611                                 ptp_clock_index(ptp_priv->ptp_clock) : -1;
3612         if (info->phc_index == -1) {
3613                 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
3614                                          SOF_TIMESTAMPING_RX_SOFTWARE |
3615                                          SOF_TIMESTAMPING_SOFTWARE;
3616                 return 0;
3617         }
3618
3619         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
3620                                 SOF_TIMESTAMPING_RX_HARDWARE |
3621                                 SOF_TIMESTAMPING_RAW_HARDWARE;
3622
3623         info->tx_types = (1 << HWTSTAMP_TX_OFF) |
3624                          (1 << HWTSTAMP_TX_ON) |
3625                          (1 << HWTSTAMP_TX_ONESTEP_SYNC);
3626
3627         info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3628                            (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3629                            (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3630                            (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3631
3632         return 0;
3633 }
3634
3635 #define LAN8841_PTP_INT_EN                      260
3636 #define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN   BIT(13)
3637 #define LAN8841_PTP_INT_EN_PTP_TX_TS_EN         BIT(12)
3638
3639 static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
3640                                           bool enable)
3641 {
3642         struct phy_device *phydev = ptp_priv->phydev;
3643
3644         if (enable) {
3645                 /* Enable interrupts on the TX side */
3646                 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3647                                LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3648                                LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
3649                                LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3650                                LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
3651
3652                 /* Enable the modification of the frame on RX side,
3653                  * this will add the ns and 2 bits of sec in the reserved field
3654                  * of the PTP header
3655                  */
3656                 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3657                                LAN8841_PTP_RX_MODE,
3658                                LAN8841_PTP_INSERT_TS_EN |
3659                                LAN8841_PTP_INSERT_TS_32BIT,
3660                                LAN8841_PTP_INSERT_TS_EN |
3661                                LAN8841_PTP_INSERT_TS_32BIT);
3662
3663                 ptp_schedule_worker(ptp_priv->ptp_clock, 0);
3664         } else {
3665                 /* Disable interrupts on the TX side */
3666                 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3667                                LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3668                                LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);
3669
3670                 /* Disable modification of the RX frames */
3671                 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3672                                LAN8841_PTP_RX_MODE,
3673                                LAN8841_PTP_INSERT_TS_EN |
3674                                LAN8841_PTP_INSERT_TS_32BIT, 0);
3675
3676                 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
3677         }
3678 }
3679
3680 #define LAN8841_PTP_RX_TIMESTAMP_EN             379
3681 #define LAN8841_PTP_TX_TIMESTAMP_EN             443
3682 #define LAN8841_PTP_TX_MOD                      445
3683
3684 static int lan8841_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
3685 {
3686         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3687         struct phy_device *phydev = ptp_priv->phydev;
3688         struct hwtstamp_config config;
3689         int txcfg = 0, rxcfg = 0;
3690         int pkt_ts_enable;
3691
3692         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3693                 return -EFAULT;
3694
3695         ptp_priv->hwts_tx_type = config.tx_type;
3696         ptp_priv->rx_filter = config.rx_filter;
3697
3698         switch (config.rx_filter) {
3699         case HWTSTAMP_FILTER_NONE:
3700                 ptp_priv->layer = 0;
3701                 ptp_priv->version = 0;
3702                 break;
3703         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3704         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3705         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3706                 ptp_priv->layer = PTP_CLASS_L4;
3707                 ptp_priv->version = PTP_CLASS_V2;
3708                 break;
3709         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3710         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3711         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3712                 ptp_priv->layer = PTP_CLASS_L2;
3713                 ptp_priv->version = PTP_CLASS_V2;
3714                 break;
3715         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3716         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3717         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3718                 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
3719                 ptp_priv->version = PTP_CLASS_V2;
3720                 break;
3721         default:
3722                 return -ERANGE;
3723         }
3724
3725         /* Setup parsing of the frames and enable the timestamping for ptp
3726          * frames
3727          */
3728         if (ptp_priv->layer & PTP_CLASS_L2) {
3729                 rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
3730                 txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
3731         } else if (ptp_priv->layer & PTP_CLASS_L4) {
3732                 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
3733                 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
3734         }
3735
3736         phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
3737         phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
3738
3739         pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
3740                         PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
3741         phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
3742         phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
3743
3744         /* Enable / disable of the TX timestamp in the SYNC frames */
3745         phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
3746                        PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3747                        ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
3748                                 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
3749
3750         /* Now enable/disable the timestamping */
3751         lan8841_ptp_enable_processing(ptp_priv,
3752                                       config.rx_filter != HWTSTAMP_FILTER_NONE);
3753
3754         skb_queue_purge(&ptp_priv->tx_queue);
3755
3756         lan8841_ptp_flush_fifo(ptp_priv);
3757
3758         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
3759 }
3760
3761 static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
3762                              struct sk_buff *skb, int type)
3763 {
3764         struct kszphy_ptp_priv *ptp_priv =
3765                         container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3766         struct ptp_header *header = ptp_parse_header(skb, type);
3767         struct skb_shared_hwtstamps *shhwtstamps;
3768         struct timespec64 ts;
3769         unsigned long flags;
3770         u32 ts_header;
3771
3772         if (!header)
3773                 return false;
3774
3775         if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
3776             type == PTP_CLASS_NONE)
3777                 return false;
3778
3779         if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
3780                 return false;
3781
3782         spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3783         ts.tv_sec = ptp_priv->seconds;
3784         spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3785         ts_header = __be32_to_cpu(header->reserved2);
3786
3787         shhwtstamps = skb_hwtstamps(skb);
3788         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3789
3790         /* Check for any wrap arounds for the second part */
3791         if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
3792                 ts.tv_sec -= GENMASK(1, 0) + 1;
3793         else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
3794                 ts.tv_sec += 1;
3795
3796         shhwtstamps->hwtstamp =
3797                 ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
3798                           ts_header & GENMASK(29, 0));
3799         header->reserved2 = 0;
3800
3801         netif_rx(skb);
3802
3803         return true;
3804 }
3805
3806 #define LAN8841_EVENT_A         0
3807 #define LAN8841_EVENT_B         1
3808 #define LAN8841_PTP_LTC_TARGET_SEC_HI(event)    ((event) == LAN8841_EVENT_A ? 278 : 288)
3809 #define LAN8841_PTP_LTC_TARGET_SEC_LO(event)    ((event) == LAN8841_EVENT_A ? 279 : 289)
3810 #define LAN8841_PTP_LTC_TARGET_NS_HI(event)     ((event) == LAN8841_EVENT_A ? 280 : 290)
3811 #define LAN8841_PTP_LTC_TARGET_NS_LO(event)     ((event) == LAN8841_EVENT_A ? 281 : 291)
3812
3813 static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
3814                                   s64 sec, u32 nsec)
3815 {
3816         struct phy_device *phydev = ptp_priv->phydev;
3817         int ret;
3818
3819         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
3820                             upper_16_bits(sec));
3821         if (ret)
3822                 return ret;
3823
3824         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
3825                             lower_16_bits(sec));
3826         if (ret)
3827                 return ret;
3828
3829         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
3830                             upper_16_bits(nsec));
3831         if (ret)
3832                 return ret;
3833
3834         return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
3835                             lower_16_bits(nsec));
3836 }
3837
3838 #define LAN8841_BUFFER_TIME     2
3839
3840 static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
3841                                      const struct timespec64 *ts)
3842 {
3843         return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
3844                                       ts->tv_sec + LAN8841_BUFFER_TIME, 0);
3845 }
3846
3847 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event)     ((event) == LAN8841_EVENT_A ? 282 : 292)
3848 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event)     ((event) == LAN8841_EVENT_A ? 283 : 293)
3849 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event)      ((event) == LAN8841_EVENT_A ? 284 : 294)
3850 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event)      ((event) == LAN8841_EVENT_A ? 285 : 295)
3851
3852 static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
3853                                   s64 sec, u32 nsec)
3854 {
3855         struct phy_device *phydev = ptp_priv->phydev;
3856         int ret;
3857
3858         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
3859                             upper_16_bits(sec));
3860         if (ret)
3861                 return ret;
3862
3863         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
3864                             lower_16_bits(sec));
3865         if (ret)
3866                 return ret;
3867
3868         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
3869                             upper_16_bits(nsec));
3870         if (ret)
3871                 return ret;
3872
3873         return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
3874                              lower_16_bits(nsec));
3875 }
3876
3877 #define LAN8841_PTP_LTC_SET_SEC_HI      262
3878 #define LAN8841_PTP_LTC_SET_SEC_MID     263
3879 #define LAN8841_PTP_LTC_SET_SEC_LO      264
3880 #define LAN8841_PTP_LTC_SET_NS_HI       265
3881 #define LAN8841_PTP_LTC_SET_NS_LO       266
3882 #define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD        BIT(4)
3883
3884 static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
3885                                  const struct timespec64 *ts)
3886 {
3887         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3888                                                         ptp_clock_info);
3889         struct phy_device *phydev = ptp_priv->phydev;
3890         unsigned long flags;
3891         int ret;
3892
3893         /* Set the value to be stored */
3894         mutex_lock(&ptp_priv->ptp_lock);
3895         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
3896         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
3897         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
3898         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
3899         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
3900
3901         /* Set the command to load the LTC */
3902         phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3903                       LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
3904         ret = lan8841_ptp_update_target(ptp_priv, ts);
3905         mutex_unlock(&ptp_priv->ptp_lock);
3906
3907         spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3908         ptp_priv->seconds = ts->tv_sec;
3909         spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3910
3911         return ret;
3912 }
3913
3914 #define LAN8841_PTP_LTC_RD_SEC_HI       358
3915 #define LAN8841_PTP_LTC_RD_SEC_MID      359
3916 #define LAN8841_PTP_LTC_RD_SEC_LO       360
3917 #define LAN8841_PTP_LTC_RD_NS_HI        361
3918 #define LAN8841_PTP_LTC_RD_NS_LO        362
3919 #define LAN8841_PTP_CMD_CTL_PTP_LTC_READ        BIT(3)
3920
3921 static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
3922                                  struct timespec64 *ts)
3923 {
3924         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3925                                                         ptp_clock_info);
3926         struct phy_device *phydev = ptp_priv->phydev;
3927         time64_t s;
3928         s64 ns;
3929
3930         mutex_lock(&ptp_priv->ptp_lock);
3931         /* Issue the command to read the LTC */
3932         phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3933                       LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
3934
3935         /* Read the LTC */
3936         s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
3937         s <<= 16;
3938         s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
3939         s <<= 16;
3940         s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
3941
3942         ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
3943         ns <<= 16;
3944         ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
3945         mutex_unlock(&ptp_priv->ptp_lock);
3946
3947         set_normalized_timespec64(ts, s, ns);
3948         return 0;
3949 }
3950
3951 static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
3952                                    struct timespec64 *ts)
3953 {
3954         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3955                                                         ptp_clock_info);
3956         struct phy_device *phydev = ptp_priv->phydev;
3957         time64_t s;
3958
3959         mutex_lock(&ptp_priv->ptp_lock);
3960         /* Issue the command to read the LTC */
3961         phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3962                       LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
3963
3964         /* Read the LTC */
3965         s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
3966         s <<= 16;
3967         s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
3968         s <<= 16;
3969         s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
3970         mutex_unlock(&ptp_priv->ptp_lock);
3971
3972         set_normalized_timespec64(ts, s, 0);
3973 }
3974
3975 #define LAN8841_PTP_LTC_STEP_ADJ_LO                     276
3976 #define LAN8841_PTP_LTC_STEP_ADJ_HI                     275
3977 #define LAN8841_PTP_LTC_STEP_ADJ_DIR                    BIT(15)
3978 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS        BIT(5)
3979 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS    BIT(6)
3980
3981 static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
3982 {
3983         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3984                                                         ptp_clock_info);
3985         struct phy_device *phydev = ptp_priv->phydev;
3986         struct timespec64 ts;
3987         bool add = true;
3988         u32 nsec;
3989         s32 sec;
3990         int ret;
3991
3992         /* The HW allows up to 15 sec to adjust the time, but here we limit to
3993          * 10 sec the adjustment. The reason is, in case the adjustment is 14
3994          * sec and 999999999 nsec, then we add 8ns to compansate the actual
3995          * increment so the value can be bigger than 15 sec. Therefore limit the
3996          * possible adjustments so we will not have these corner cases
3997          */
3998         if (delta > 10000000000LL || delta < -10000000000LL) {
3999                 /* The timeadjustment is too big, so fall back using set time */
4000                 u64 now;
4001
4002                 ptp->gettime64(ptp, &ts);
4003
4004                 now = ktime_to_ns(timespec64_to_ktime(ts));
4005                 ts = ns_to_timespec64(now + delta);
4006
4007                 ptp->settime64(ptp, &ts);
4008                 return 0;
4009         }
4010
4011         sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);
4012         if (delta < 0 && nsec != 0) {
4013                 /* It is not allowed to adjust low the nsec part, therefore
4014                  * subtract more from second part and add to nanosecond such
4015                  * that would roll over, so the second part will increase
4016                  */
4017                 sec--;
4018                 nsec = NSEC_PER_SEC - nsec;
4019         }
4020
4021         /* Calculate the adjustments and the direction */
4022         if (delta < 0)
4023                 add = false;
4024
4025         if (nsec > 0)
4026                 /* add 8 ns to cover the likely normal increment */
4027                 nsec += 8;
4028
4029         if (nsec >= NSEC_PER_SEC) {
4030                 /* carry into seconds */
4031                 sec++;
4032                 nsec -= NSEC_PER_SEC;
4033         }
4034
4035         mutex_lock(&ptp_priv->ptp_lock);
4036         if (sec) {
4037                 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4038                 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4039                               add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4040                 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4041                               LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4042         }
4043
4044         if (nsec) {
4045                 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4046                               nsec & 0xffff);
4047                 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4048                               (nsec >> 16) & 0x3fff);
4049                 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4050                               LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4051         }
4052         mutex_unlock(&ptp_priv->ptp_lock);
4053
4054         /* Update the target clock */
4055         ptp->gettime64(ptp, &ts);
4056         mutex_lock(&ptp_priv->ptp_lock);
4057         ret = lan8841_ptp_update_target(ptp_priv, &ts);
4058         mutex_unlock(&ptp_priv->ptp_lock);
4059
4060         return ret;
4061 }
4062
4063 #define LAN8841_PTP_LTC_RATE_ADJ_HI             269
4064 #define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR         BIT(15)
4065 #define LAN8841_PTP_LTC_RATE_ADJ_LO             270
4066
4067 static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4068 {
4069         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4070                                                         ptp_clock_info);
4071         struct phy_device *phydev = ptp_priv->phydev;
4072         bool faster = true;
4073         u32 rate;
4074
4075         if (!scaled_ppm)
4076                 return 0;
4077
4078         if (scaled_ppm < 0) {
4079                 scaled_ppm = -scaled_ppm;
4080                 faster = false;
4081         }
4082
4083         rate = LAN8814_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4084         rate += (LAN8814_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4085
4086         mutex_lock(&ptp_priv->ptp_lock);
4087         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4088                       faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4089                              : upper_16_bits(rate) & 0x3fff);
4090         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4091         mutex_unlock(&ptp_priv->ptp_lock);
4092
4093         return 0;
4094 }
4095
4096 static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4097                               enum ptp_pin_function func, unsigned int chan)
4098 {
4099         switch (func) {
4100         case PTP_PF_NONE:
4101         case PTP_PF_PEROUT:
4102         case PTP_PF_EXTTS:
4103                 break;
4104         default:
4105                 return -1;
4106         }
4107
4108         return 0;
4109 }
4110
4111 #define LAN8841_PTP_GPIO_NUM    10
4112 #define LAN8841_GPIO_EN         128
4113 #define LAN8841_GPIO_DIR        129
4114 #define LAN8841_GPIO_BUF        130
4115
4116 static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4117 {
4118         struct phy_device *phydev = ptp_priv->phydev;
4119         int ret;
4120
4121         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4122         if (ret)
4123                 return ret;
4124
4125         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4126         if (ret)
4127                 return ret;
4128
4129         return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4130 }
4131
4132 static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4133 {
4134         struct phy_device *phydev = ptp_priv->phydev;
4135         int ret;
4136
4137         ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4138         if (ret)
4139                 return ret;
4140
4141         ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4142         if (ret)
4143                 return ret;
4144
4145         return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4146 }
4147
4148 #define LAN8841_GPIO_DATA_SEL1                          131
4149 #define LAN8841_GPIO_DATA_SEL2                          132
4150 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK  GENMASK(2, 0)
4151 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A     1
4152 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B     2
4153 #define LAN8841_PTP_GENERAL_CONFIG                      257
4154 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A      BIT(1)
4155 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B      BIT(3)
4156 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK     GENMASK(7, 4)
4157 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK     GENMASK(11, 8)
4158 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A          4
4159 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B          7
4160
4161 static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4162                                     u8 event)
4163 {
4164         struct phy_device *phydev = ptp_priv->phydev;
4165         u16 tmp;
4166         int ret;
4167
4168         /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4169          * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4170          * depending on the pin, it requires to read a different register
4171          */
4172         if (pin < 5) {
4173                 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4174                 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4175         } else {
4176                 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4177                 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4178         }
4179         if (ret)
4180                 return ret;
4181
4182         /* Disable the event */
4183         if (event == LAN8841_EVENT_A)
4184                 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4185                       LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4186         else
4187                 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4188                       LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4189         return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4190 }
4191
4192 static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4193                                     u8 event, int pulse_width)
4194 {
4195         struct phy_device *phydev = ptp_priv->phydev;
4196         u16 tmp;
4197         int ret;
4198
4199         /* Enable the event */
4200         if (event == LAN8841_EVENT_A)
4201                 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4202                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4203                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
4204                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4205                                      pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
4206         else
4207                 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4208                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4209                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
4210                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4211                                      pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
4212         if (ret)
4213                 return ret;
4214
4215         /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
4216          * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4217          * depending on the pin, it requires to read a different register
4218          */
4219         if (event == LAN8841_EVENT_A)
4220                 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
4221         else
4222                 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
4223
4224         if (pin < 5)
4225                 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
4226                                        tmp << (3 * pin));
4227         else
4228                 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
4229                                        tmp << (3 * (pin - 5)));
4230
4231         return ret;
4232 }
4233
4234 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS      13
4235 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS      12
4236 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS       11
4237 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS       10
4238 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS        9
4239 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS        8
4240 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US      7
4241 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US      6
4242 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US       5
4243 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US       4
4244 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US        3
4245 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US        2
4246 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS      1
4247 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS      0
4248
4249 static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
4250                               struct ptp_clock_request *rq, int on)
4251 {
4252         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4253                                                         ptp_clock_info);
4254         struct phy_device *phydev = ptp_priv->phydev;
4255         struct timespec64 ts_on, ts_period;
4256         s64 on_nsec, period_nsec;
4257         int pulse_width;
4258         int pin;
4259         int ret;
4260
4261         if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
4262                 return -EOPNOTSUPP;
4263
4264         pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);
4265         if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4266                 return -EINVAL;
4267
4268         if (!on) {
4269                 ret = lan8841_ptp_perout_off(ptp_priv, pin);
4270                 if (ret)
4271                         return ret;
4272
4273                 return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);
4274         }
4275
4276         ts_on.tv_sec = rq->perout.on.sec;
4277         ts_on.tv_nsec = rq->perout.on.nsec;
4278         on_nsec = timespec64_to_ns(&ts_on);
4279
4280         ts_period.tv_sec = rq->perout.period.sec;
4281         ts_period.tv_nsec = rq->perout.period.nsec;
4282         period_nsec = timespec64_to_ns(&ts_period);
4283
4284         if (period_nsec < 200) {
4285                 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
4286                                     phydev_name(phydev));
4287                 return -EOPNOTSUPP;
4288         }
4289
4290         if (on_nsec >= period_nsec) {
4291                 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
4292                                     phydev_name(phydev));
4293                 return -EINVAL;
4294         }
4295
4296         switch (on_nsec) {
4297         case 200000000:
4298                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
4299                 break;
4300         case 100000000:
4301                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
4302                 break;
4303         case 50000000:
4304                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
4305                 break;
4306         case 10000000:
4307                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
4308                 break;
4309         case 5000000:
4310                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
4311                 break;
4312         case 1000000:
4313                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
4314                 break;
4315         case 500000:
4316                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
4317                 break;
4318         case 100000:
4319                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
4320                 break;
4321         case 50000:
4322                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
4323                 break;
4324         case 10000:
4325                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
4326                 break;
4327         case 5000:
4328                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
4329                 break;
4330         case 1000:
4331                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
4332                 break;
4333         case 500:
4334                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
4335                 break;
4336         case 100:
4337                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4338                 break;
4339         default:
4340                 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
4341                                     phydev_name(phydev));
4342                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4343                 break;
4344         }
4345
4346         mutex_lock(&ptp_priv->ptp_lock);
4347         ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,
4348                                      rq->perout.start.nsec);
4349         mutex_unlock(&ptp_priv->ptp_lock);
4350         if (ret)
4351                 return ret;
4352
4353         ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,
4354                                      rq->perout.period.nsec);
4355         if (ret)
4356                 return ret;
4357
4358         ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
4359                                        pulse_width);
4360         if (ret)
4361                 return ret;
4362
4363         ret = lan8841_ptp_perout_on(ptp_priv, pin);
4364         if (ret)
4365                 lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
4366
4367         return ret;
4368 }
4369
4370 #define LAN8841_PTP_GPIO_CAP_EN                 496
4371 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio)    (BIT(gpio))
4372 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio)    (BIT(gpio) << 8)
4373 #define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN      BIT(2)
4374
4375 static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
4376                                 u32 flags)
4377 {
4378         struct phy_device *phydev = ptp_priv->phydev;
4379         u16 tmp = 0;
4380         int ret;
4381
4382         /* Set GPIO to be intput */
4383         ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4384         if (ret)
4385                 return ret;
4386
4387         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4388         if (ret)
4389                 return ret;
4390
4391         /* Enable capture on the edges of the pin */
4392         if (flags & PTP_RISING_EDGE)
4393                 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
4394         if (flags & PTP_FALLING_EDGE)
4395                 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
4396         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
4397         if (ret)
4398                 return ret;
4399
4400         /* Enable interrupt */
4401         return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4402                               LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4403                               LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
4404 }
4405
4406 static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4407 {
4408         struct phy_device *phydev = ptp_priv->phydev;
4409         int ret;
4410
4411         /* Set GPIO to be output */
4412         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4413         if (ret)
4414                 return ret;
4415
4416         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4417         if (ret)
4418                 return ret;
4419
4420         /* Disable capture on both of the edges */
4421         ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
4422                              LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
4423                              LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
4424                              0);
4425         if (ret)
4426                 return ret;
4427
4428         /* Disable interrupt */
4429         return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4430                               LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4431                               0);
4432 }
4433
4434 static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
4435                              struct ptp_clock_request *rq, int on)
4436 {
4437         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4438                                                         ptp_clock_info);
4439         int pin;
4440         int ret;
4441
4442         /* Reject requests with unsupported flags */
4443         if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
4444                                 PTP_EXTTS_EDGES |
4445                                 PTP_STRICT_FLAGS))
4446                 return -EOPNOTSUPP;
4447
4448         pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
4449         if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4450                 return -EINVAL;
4451
4452         mutex_lock(&ptp_priv->ptp_lock);
4453         if (on)
4454                 ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);
4455         else
4456                 ret = lan8841_ptp_extts_off(ptp_priv, pin);
4457         mutex_unlock(&ptp_priv->ptp_lock);
4458
4459         return ret;
4460 }
4461
4462 static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
4463                               struct ptp_clock_request *rq, int on)
4464 {
4465         switch (rq->type) {
4466         case PTP_CLK_REQ_EXTTS:
4467                 return lan8841_ptp_extts(ptp, rq, on);
4468         case PTP_CLK_REQ_PEROUT:
4469                 return lan8841_ptp_perout(ptp, rq, on);
4470         default:
4471                 return -EOPNOTSUPP;
4472         }
4473
4474         return 0;
4475 }
4476
4477 static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
4478 {
4479         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4480                                                         ptp_clock_info);
4481         struct timespec64 ts;
4482         unsigned long flags;
4483
4484         lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);
4485
4486         spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4487         ptp_priv->seconds = ts.tv_sec;
4488         spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4489
4490         return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
4491 }
4492
4493 static struct ptp_clock_info lan8841_ptp_clock_info = {
4494         .owner          = THIS_MODULE,
4495         .name           = "lan8841 ptp",
4496         .max_adj        = 31249999,
4497         .gettime64      = lan8841_ptp_gettime64,
4498         .settime64      = lan8841_ptp_settime64,
4499         .adjtime        = lan8841_ptp_adjtime,
4500         .adjfine        = lan8841_ptp_adjfine,
4501         .verify         = lan8841_ptp_verify,
4502         .enable         = lan8841_ptp_enable,
4503         .do_aux_work    = lan8841_ptp_do_aux_work,
4504         .n_per_out      = LAN8841_PTP_GPIO_NUM,
4505         .n_ext_ts       = LAN8841_PTP_GPIO_NUM,
4506         .n_pins         = LAN8841_PTP_GPIO_NUM,
4507 };
4508
4509 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
4510 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
4511
4512 static int lan8841_probe(struct phy_device *phydev)
4513 {
4514         struct kszphy_ptp_priv *ptp_priv;
4515         struct kszphy_priv *priv;
4516         int err;
4517
4518         err = kszphy_probe(phydev);
4519         if (err)
4520                 return err;
4521
4522         if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4523                          LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
4524             LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
4525                 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
4526
4527         /* Register the clock */
4528         if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
4529                 return 0;
4530
4531         priv = phydev->priv;
4532         ptp_priv = &priv->ptp_priv;
4533
4534         ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
4535                                             LAN8841_PTP_GPIO_NUM,
4536                                             sizeof(*ptp_priv->pin_config),
4537                                             GFP_KERNEL);
4538         if (!ptp_priv->pin_config)
4539                 return -ENOMEM;
4540
4541         for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
4542                 struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
4543
4544                 snprintf(p->name, sizeof(p->name), "pin%d", i);
4545                 p->index = i;
4546                 p->func = PTP_PF_NONE;
4547         }
4548
4549         ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
4550         ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
4551         ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,
4552                                                  &phydev->mdio.dev);
4553         if (IS_ERR(ptp_priv->ptp_clock)) {
4554                 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
4555                            PTR_ERR(ptp_priv->ptp_clock));
4556                 return -EINVAL;
4557         }
4558
4559         if (!ptp_priv->ptp_clock)
4560                 return 0;
4561
4562         /* Initialize the SW */
4563         skb_queue_head_init(&ptp_priv->tx_queue);
4564         ptp_priv->phydev = phydev;
4565         mutex_init(&ptp_priv->ptp_lock);
4566         spin_lock_init(&ptp_priv->seconds_lock);
4567
4568         ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
4569         ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
4570         ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
4571         ptp_priv->mii_ts.ts_info = lan8841_ts_info;
4572
4573         phydev->mii_ts = &ptp_priv->mii_ts;
4574
4575         return 0;
4576 }
4577
4578 static int lan8841_suspend(struct phy_device *phydev)
4579 {
4580         struct kszphy_priv *priv = phydev->priv;
4581         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4582
4583         ptp_cancel_worker_sync(ptp_priv->ptp_clock);
4584
4585         return genphy_suspend(phydev);
4586 }
4587
4588 static struct phy_driver ksphy_driver[] = {
4589 {
4590         .phy_id         = PHY_ID_KS8737,
4591         .phy_id_mask    = MICREL_PHY_ID_MASK,
4592         .name           = "Micrel KS8737",
4593         /* PHY_BASIC_FEATURES */
4594         .driver_data    = &ks8737_type,
4595         .probe          = kszphy_probe,
4596         .config_init    = kszphy_config_init,
4597         .config_intr    = kszphy_config_intr,
4598         .handle_interrupt = kszphy_handle_interrupt,
4599         .suspend        = kszphy_suspend,
4600         .resume         = kszphy_resume,
4601 }, {
4602         .phy_id         = PHY_ID_KSZ8021,
4603         .phy_id_mask    = 0x00ffffff,
4604         .name           = "Micrel KSZ8021 or KSZ8031",
4605         /* PHY_BASIC_FEATURES */
4606         .driver_data    = &ksz8021_type,
4607         .probe          = kszphy_probe,
4608         .config_init    = kszphy_config_init,
4609         .config_intr    = kszphy_config_intr,
4610         .handle_interrupt = kszphy_handle_interrupt,
4611         .get_sset_count = kszphy_get_sset_count,
4612         .get_strings    = kszphy_get_strings,
4613         .get_stats      = kszphy_get_stats,
4614         .suspend        = kszphy_suspend,
4615         .resume         = kszphy_resume,
4616 }, {
4617         .phy_id         = PHY_ID_KSZ8031,
4618         .phy_id_mask    = 0x00ffffff,
4619         .name           = "Micrel KSZ8031",
4620         /* PHY_BASIC_FEATURES */
4621         .driver_data    = &ksz8021_type,
4622         .probe          = kszphy_probe,
4623         .config_init    = kszphy_config_init,
4624         .config_intr    = kszphy_config_intr,
4625         .handle_interrupt = kszphy_handle_interrupt,
4626         .get_sset_count = kszphy_get_sset_count,
4627         .get_strings    = kszphy_get_strings,
4628         .get_stats      = kszphy_get_stats,
4629         .suspend        = kszphy_suspend,
4630         .resume         = kszphy_resume,
4631 }, {
4632         .phy_id         = PHY_ID_KSZ8041,
4633         .phy_id_mask    = MICREL_PHY_ID_MASK,
4634         .name           = "Micrel KSZ8041",
4635         /* PHY_BASIC_FEATURES */
4636         .driver_data    = &ksz8041_type,
4637         .probe          = kszphy_probe,
4638         .config_init    = ksz8041_config_init,
4639         .config_aneg    = ksz8041_config_aneg,
4640         .config_intr    = kszphy_config_intr,
4641         .handle_interrupt = kszphy_handle_interrupt,
4642         .get_sset_count = kszphy_get_sset_count,
4643         .get_strings    = kszphy_get_strings,
4644         .get_stats      = kszphy_get_stats,
4645         /* No suspend/resume callbacks because of errata DS80000700A,
4646          * receiver error following software power down.
4647          */
4648 }, {
4649         .phy_id         = PHY_ID_KSZ8041RNLI,
4650         .phy_id_mask    = MICREL_PHY_ID_MASK,
4651         .name           = "Micrel KSZ8041RNLI",
4652         /* PHY_BASIC_FEATURES */
4653         .driver_data    = &ksz8041_type,
4654         .probe          = kszphy_probe,
4655         .config_init    = kszphy_config_init,
4656         .config_intr    = kszphy_config_intr,
4657         .handle_interrupt = kszphy_handle_interrupt,
4658         .get_sset_count = kszphy_get_sset_count,
4659         .get_strings    = kszphy_get_strings,
4660         .get_stats      = kszphy_get_stats,
4661         .suspend        = kszphy_suspend,
4662         .resume         = kszphy_resume,
4663 }, {
4664         .name           = "Micrel KSZ8051",
4665         /* PHY_BASIC_FEATURES */
4666         .driver_data    = &ksz8051_type,
4667         .probe          = kszphy_probe,
4668         .config_init    = kszphy_config_init,
4669         .config_intr    = kszphy_config_intr,
4670         .handle_interrupt = kszphy_handle_interrupt,
4671         .get_sset_count = kszphy_get_sset_count,
4672         .get_strings    = kszphy_get_strings,
4673         .get_stats      = kszphy_get_stats,
4674         .match_phy_device = ksz8051_match_phy_device,
4675         .suspend        = kszphy_suspend,
4676         .resume         = kszphy_resume,
4677 }, {
4678         .phy_id         = PHY_ID_KSZ8001,
4679         .name           = "Micrel KSZ8001 or KS8721",
4680         .phy_id_mask    = 0x00fffffc,
4681         /* PHY_BASIC_FEATURES */
4682         .driver_data    = &ksz8041_type,
4683         .probe          = kszphy_probe,
4684         .config_init    = kszphy_config_init,
4685         .config_intr    = kszphy_config_intr,
4686         .handle_interrupt = kszphy_handle_interrupt,
4687         .get_sset_count = kszphy_get_sset_count,
4688         .get_strings    = kszphy_get_strings,
4689         .get_stats      = kszphy_get_stats,
4690         .suspend        = kszphy_suspend,
4691         .resume         = kszphy_resume,
4692 }, {
4693         .phy_id         = PHY_ID_KSZ8081,
4694         .name           = "Micrel KSZ8081 or KSZ8091",
4695         .phy_id_mask    = MICREL_PHY_ID_MASK,
4696         .flags          = PHY_POLL_CABLE_TEST,
4697         /* PHY_BASIC_FEATURES */
4698         .driver_data    = &ksz8081_type,
4699         .probe          = kszphy_probe,
4700         .config_init    = ksz8081_config_init,
4701         .soft_reset     = genphy_soft_reset,
4702         .config_aneg    = ksz8081_config_aneg,
4703         .read_status    = ksz8081_read_status,
4704         .config_intr    = kszphy_config_intr,
4705         .handle_interrupt = kszphy_handle_interrupt,
4706         .get_sset_count = kszphy_get_sset_count,
4707         .get_strings    = kszphy_get_strings,
4708         .get_stats      = kszphy_get_stats,
4709         .suspend        = kszphy_suspend,
4710         .resume         = kszphy_resume,
4711         .cable_test_start       = ksz886x_cable_test_start,
4712         .cable_test_get_status  = ksz886x_cable_test_get_status,
4713 }, {
4714         .phy_id         = PHY_ID_KSZ8061,
4715         .name           = "Micrel KSZ8061",
4716         .phy_id_mask    = MICREL_PHY_ID_MASK,
4717         /* PHY_BASIC_FEATURES */
4718         .probe          = kszphy_probe,
4719         .config_init    = ksz8061_config_init,
4720         .config_intr    = kszphy_config_intr,
4721         .handle_interrupt = kszphy_handle_interrupt,
4722         .suspend        = kszphy_suspend,
4723         .resume         = kszphy_resume,
4724 }, {
4725         .phy_id         = PHY_ID_KSZ9021,
4726         .phy_id_mask    = 0x000ffffe,
4727         .name           = "Micrel KSZ9021 Gigabit PHY",
4728         /* PHY_GBIT_FEATURES */
4729         .driver_data    = &ksz9021_type,
4730         .probe          = kszphy_probe,
4731         .get_features   = ksz9031_get_features,
4732         .config_init    = ksz9021_config_init,
4733         .config_intr    = kszphy_config_intr,
4734         .handle_interrupt = kszphy_handle_interrupt,
4735         .get_sset_count = kszphy_get_sset_count,
4736         .get_strings    = kszphy_get_strings,
4737         .get_stats      = kszphy_get_stats,
4738         .suspend        = kszphy_suspend,
4739         .resume         = kszphy_resume,
4740         .read_mmd       = genphy_read_mmd_unsupported,
4741         .write_mmd      = genphy_write_mmd_unsupported,
4742 }, {
4743         .phy_id         = PHY_ID_KSZ9031,
4744         .phy_id_mask    = MICREL_PHY_ID_MASK,
4745         .name           = "Micrel KSZ9031 Gigabit PHY",
4746         .flags          = PHY_POLL_CABLE_TEST,
4747         .driver_data    = &ksz9021_type,
4748         .probe          = kszphy_probe,
4749         .get_features   = ksz9031_get_features,
4750         .config_init    = ksz9031_config_init,
4751         .soft_reset     = genphy_soft_reset,
4752         .read_status    = ksz9031_read_status,
4753         .config_intr    = kszphy_config_intr,
4754         .handle_interrupt = kszphy_handle_interrupt,
4755         .get_sset_count = kszphy_get_sset_count,
4756         .get_strings    = kszphy_get_strings,
4757         .get_stats      = kszphy_get_stats,
4758         .suspend        = kszphy_suspend,
4759         .resume         = kszphy_resume,
4760         .cable_test_start       = ksz9x31_cable_test_start,
4761         .cable_test_get_status  = ksz9x31_cable_test_get_status,
4762 }, {
4763         .phy_id         = PHY_ID_LAN8814,
4764         .phy_id_mask    = MICREL_PHY_ID_MASK,
4765         .name           = "Microchip INDY Gigabit Quad PHY",
4766         .flags          = PHY_POLL_CABLE_TEST,
4767         .config_init    = lan8814_config_init,
4768         .driver_data    = &lan8814_type,
4769         .probe          = lan8814_probe,
4770         .soft_reset     = genphy_soft_reset,
4771         .read_status    = ksz9031_read_status,
4772         .get_sset_count = kszphy_get_sset_count,
4773         .get_strings    = kszphy_get_strings,
4774         .get_stats      = kszphy_get_stats,
4775         .suspend        = genphy_suspend,
4776         .resume         = kszphy_resume,
4777         .config_intr    = lan8814_config_intr,
4778         .handle_interrupt = lan8814_handle_interrupt,
4779         .cable_test_start       = lan8814_cable_test_start,
4780         .cable_test_get_status  = ksz886x_cable_test_get_status,
4781 }, {
4782         .phy_id         = PHY_ID_LAN8804,
4783         .phy_id_mask    = MICREL_PHY_ID_MASK,
4784         .name           = "Microchip LAN966X Gigabit PHY",
4785         .config_init    = lan8804_config_init,
4786         .driver_data    = &ksz9021_type,
4787         .probe          = kszphy_probe,
4788         .soft_reset     = genphy_soft_reset,
4789         .read_status    = ksz9031_read_status,
4790         .get_sset_count = kszphy_get_sset_count,
4791         .get_strings    = kszphy_get_strings,
4792         .get_stats      = kszphy_get_stats,
4793         .suspend        = genphy_suspend,
4794         .resume         = kszphy_resume,
4795         .config_intr    = lan8804_config_intr,
4796         .handle_interrupt = lan8804_handle_interrupt,
4797 }, {
4798         .phy_id         = PHY_ID_LAN8841,
4799         .phy_id_mask    = MICREL_PHY_ID_MASK,
4800         .name           = "Microchip LAN8841 Gigabit PHY",
4801         .flags          = PHY_POLL_CABLE_TEST,
4802         .driver_data    = &lan8841_type,
4803         .config_init    = lan8841_config_init,
4804         .probe          = lan8841_probe,
4805         .soft_reset     = genphy_soft_reset,
4806         .config_intr    = lan8841_config_intr,
4807         .handle_interrupt = lan8841_handle_interrupt,
4808         .get_sset_count = kszphy_get_sset_count,
4809         .get_strings    = kszphy_get_strings,
4810         .get_stats      = kszphy_get_stats,
4811         .suspend        = lan8841_suspend,
4812         .resume         = genphy_resume,
4813         .cable_test_start       = lan8814_cable_test_start,
4814         .cable_test_get_status  = ksz886x_cable_test_get_status,
4815 }, {
4816         .phy_id         = PHY_ID_KSZ9131,
4817         .phy_id_mask    = MICREL_PHY_ID_MASK,
4818         .name           = "Microchip KSZ9131 Gigabit PHY",
4819         /* PHY_GBIT_FEATURES */
4820         .flags          = PHY_POLL_CABLE_TEST,
4821         .driver_data    = &ksz9131_type,
4822         .probe          = kszphy_probe,
4823         .config_init    = ksz9131_config_init,
4824         .config_intr    = kszphy_config_intr,
4825         .config_aneg    = ksz9131_config_aneg,
4826         .read_status    = ksz9131_read_status,
4827         .handle_interrupt = kszphy_handle_interrupt,
4828         .get_sset_count = kszphy_get_sset_count,
4829         .get_strings    = kszphy_get_strings,
4830         .get_stats      = kszphy_get_stats,
4831         .suspend        = kszphy_suspend,
4832         .resume         = kszphy_resume,
4833         .cable_test_start       = ksz9x31_cable_test_start,
4834         .cable_test_get_status  = ksz9x31_cable_test_get_status,
4835         .get_features   = ksz9477_get_features,
4836 }, {
4837         .phy_id         = PHY_ID_KSZ8873MLL,
4838         .phy_id_mask    = MICREL_PHY_ID_MASK,
4839         .name           = "Micrel KSZ8873MLL Switch",
4840         /* PHY_BASIC_FEATURES */
4841         .config_init    = kszphy_config_init,
4842         .config_aneg    = ksz8873mll_config_aneg,
4843         .read_status    = ksz8873mll_read_status,
4844         .suspend        = genphy_suspend,
4845         .resume         = genphy_resume,
4846 }, {
4847         .phy_id         = PHY_ID_KSZ886X,
4848         .phy_id_mask    = MICREL_PHY_ID_MASK,
4849         .name           = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
4850         .driver_data    = &ksz886x_type,
4851         /* PHY_BASIC_FEATURES */
4852         .flags          = PHY_POLL_CABLE_TEST,
4853         .config_init    = kszphy_config_init,
4854         .config_aneg    = ksz886x_config_aneg,
4855         .read_status    = ksz886x_read_status,
4856         .suspend        = genphy_suspend,
4857         .resume         = genphy_resume,
4858         .cable_test_start       = ksz886x_cable_test_start,
4859         .cable_test_get_status  = ksz886x_cable_test_get_status,
4860 }, {
4861         .name           = "Micrel KSZ87XX Switch",
4862         /* PHY_BASIC_FEATURES */
4863         .config_init    = kszphy_config_init,
4864         .match_phy_device = ksz8795_match_phy_device,
4865         .suspend        = genphy_suspend,
4866         .resume         = genphy_resume,
4867 }, {
4868         .phy_id         = PHY_ID_KSZ9477,
4869         .phy_id_mask    = MICREL_PHY_ID_MASK,
4870         .name           = "Microchip KSZ9477",
4871         /* PHY_GBIT_FEATURES */
4872         .config_init    = ksz9477_config_init,
4873         .config_intr    = kszphy_config_intr,
4874         .handle_interrupt = kszphy_handle_interrupt,
4875         .suspend        = genphy_suspend,
4876         .resume         = genphy_resume,
4877         .get_features   = ksz9477_get_features,
4878 } };
4879
4880 module_phy_driver(ksphy_driver);
4881
4882 MODULE_DESCRIPTION("Micrel PHY driver");
4883 MODULE_AUTHOR("David J. Choi");
4884 MODULE_LICENSE("GPL");
4885
4886 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
4887         { PHY_ID_KSZ9021, 0x000ffffe },
4888         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
4889         { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
4890         { PHY_ID_KSZ8001, 0x00fffffc },
4891         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
4892         { PHY_ID_KSZ8021, 0x00ffffff },
4893         { PHY_ID_KSZ8031, 0x00ffffff },
4894         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
4895         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
4896         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
4897         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
4898         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
4899         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
4900         { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
4901         { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
4902         { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
4903         { }
4904 };
4905
4906 MODULE_DEVICE_TABLE(mdio, micrel_tbl);