drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  *                       ksz9477
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/phy.h>
  29 #include <linux/micrel_phy.h>
  30 #include <linux/of.h>
  31 #include <linux/clk.h>
  32
  33 /* Operation Mode Strap Override */
  34 #define MII_KSZPHY_OMSO                         0x16
  35 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  36 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  37 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  38 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  39
  40 /* general Interrupt control/status reg in vendor specific block. */
  41 #define MII_KSZPHY_INTCS                        0x1B
  42 #define KSZPHY_INTCS_JABBER                     BIT(15)
  43 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  44 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  45 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  46 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  47 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  48 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  49 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  50 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  51                                                 KSZPHY_INTCS_LINK_DOWN)
  52
  53 /* PHY Control 1 */
  54 #define MII_KSZPHY_CTRL_1                       0x1e
  55
  56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  57 #define MII_KSZPHY_CTRL_2                       0x1f
  58 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  59 /* bitmap of PHY register to set interrupt mode */
  60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  61 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  62
  63 /* Write/read to/from extended registers */
  64 #define MII_KSZPHY_EXTREG                       0x0b
  65 #define KSZPHY_EXTREG_WRITE                     0x8000
  66
  67 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  68 #define MII_KSZPHY_EXTREG_READ                  0x0d
  69
  70 /* Extended registers */
  71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  72 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  73 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  74
  75 #define PS_TO_REG                               200
  76
  77 struct kszphy_hw_stat {
  78         const char *string;
  79         u8 reg;
  80         u8 bits;
  81 };
  82
  83 static struct kszphy_hw_stat kszphy_hw_stats[] = {
  84         { "phy_receive_errors", 21, 16},
  85         { "phy_idle_errors", 10, 8 },
  86 };
  87
  88 struct kszphy_type {
  89         u32 led_mode_reg;
  90         u16 interrupt_level_mask;
  91         bool has_broadcast_disable;
  92         bool has_nand_tree_disable;
  93         bool has_rmii_ref_clk_sel;
  94 };
  95
  96 struct kszphy_priv {
  97         const struct kszphy_type *type;
  98         int led_mode;
  99         bool rmii_ref_clk_sel;
 100         bool rmii_ref_clk_sel_val;
 101         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 102 };
 103
 104 static const struct kszphy_type ksz8021_type = {
 105         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 106         .has_broadcast_disable  = true,
 107         .has_nand_tree_disable  = true,
 108         .has_rmii_ref_clk_sel   = true,
 109 };
 110
 111 static const struct kszphy_type ksz8041_type = {
 112         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 113 };
 114
 115 static const struct kszphy_type ksz8051_type = {
 116         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 117         .has_nand_tree_disable  = true,
 118 };
 119
 120 static const struct kszphy_type ksz8081_type = {
 121         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 122         .has_broadcast_disable  = true,
 123         .has_nand_tree_disable  = true,
 124         .has_rmii_ref_clk_sel   = true,
 125 };
 126
 127 static const struct kszphy_type ks8737_type = {
 128         .interrupt_level_mask   = BIT(14),
 129 };
 130
 131 static const struct kszphy_type ksz9021_type = {
 132         .interrupt_level_mask   = BIT(14),
 133 };
 134
 135 static int kszphy_extended_write(struct phy_device *phydev,
 136                                 u32 regnum, u16 val)
 137 {
 138         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 139         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 140 }
 141
 142 static int kszphy_extended_read(struct phy_device *phydev,
 143                                 u32 regnum)
 144 {
 145         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 146         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 147 }
 148
 149 static int kszphy_ack_interrupt(struct phy_device *phydev)
 150 {
 151         /* bit[7..0] int status, which is a read and clear register. */
 152         int rc;
 153
 154         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 155
 156         return (rc < 0) ? rc : 0;
 157 }
 158
 159 static int kszphy_config_intr(struct phy_device *phydev)
 160 {
 161         const struct kszphy_type *type = phydev->drv->driver_data;
 162         int temp;
 163         u16 mask;
 164
 165         if (type && type->interrupt_level_mask)
 166                 mask = type->interrupt_level_mask;
 167         else
 168                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 169
 170         /* set the interrupt pin active low */
 171         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 172         if (temp < 0)
 173                 return temp;
 174         temp &= ~mask;
 175         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 176
 177         /* enable / disable interrupts */
 178         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 179                 temp = KSZPHY_INTCS_ALL;
 180         else
 181                 temp = 0;
 182
 183         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 184 }
 185
 186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 187 {
 188         int ctrl;
 189
 190         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 191         if (ctrl < 0)
 192                 return ctrl;
 193
 194         if (val)
 195                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 196         else
 197                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 198
 199         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 200 }
 201
 202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 203 {
 204         int rc, temp, shift;
 205
 206         switch (reg) {
 207         case MII_KSZPHY_CTRL_1:
 208                 shift = 14;
 209                 break;
 210         case MII_KSZPHY_CTRL_2:
 211                 shift = 4;
 212                 break;
 213         default:
 214                 return -EINVAL;
 215         }
 216
 217         temp = phy_read(phydev, reg);
 218         if (temp < 0) {
 219                 rc = temp;
 220                 goto out;
 221         }
 222
 223         temp &= ~(3 << shift);
 224         temp |= val << shift;
 225         rc = phy_write(phydev, reg, temp);
 226 out:
 227         if (rc < 0)
 228                 phydev_err(phydev, "failed to set led mode\n");
 229
 230         return rc;
 231 }
 232
 233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 234  * unique (non-broadcast) address on a shared bus.
 235  */
 236 static int kszphy_broadcast_disable(struct phy_device *phydev)
 237 {
 238         int ret;
 239
 240         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 241         if (ret < 0)
 242                 goto out;
 243
 244         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 245 out:
 246         if (ret)
 247                 phydev_err(phydev, "failed to disable broadcast address\n");
 248
 249         return ret;
 250 }
 251
 252 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 253 {
 254         int ret;
 255
 256         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 257         if (ret < 0)
 258                 goto out;
 259
 260         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 261                 return 0;
 262
 263         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 264                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 265 out:
 266         if (ret)
 267                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 268
 269         return ret;
 270 }
 271
 272 /* Some config bits need to be set again on resume, handle them here. */
 273 static int kszphy_config_reset(struct phy_device *phydev)
 274 {
 275         struct kszphy_priv *priv = phydev->priv;
 276         int ret;
 277
 278         if (priv->rmii_ref_clk_sel) {
 279                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 280                 if (ret) {
 281                         phydev_err(phydev,
 282                                    "failed to set rmii reference clock\n");
 283                         return ret;
 284                 }
 285         }
 286
 287         if (priv->led_mode >= 0)
 288                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 289
 290         return 0;
 291 }
 292
 293 static int kszphy_config_init(struct phy_device *phydev)
 294 {
 295         struct kszphy_priv *priv = phydev->priv;
 296         const struct kszphy_type *type;
 297
 298         if (!priv)
 299                 return 0;
 300
 301         type = priv->type;
 302
 303         if (type->has_broadcast_disable)
 304                 kszphy_broadcast_disable(phydev);
 305
 306         if (type->has_nand_tree_disable)
 307                 kszphy_nand_tree_disable(phydev);
 308
 309         return kszphy_config_reset(phydev);
 310 }
 311
 312 static int ksz8041_config_init(struct phy_device *phydev)
 313 {
 314         struct device_node *of_node = phydev->mdio.dev.of_node;
 315
 316         /* Limit supported and advertised modes in fiber mode */
 317         if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
 318                 phydev->dev_flags |= MICREL_PHY_FXEN;
 319                 phydev->supported &= SUPPORTED_100baseT_Full |
 320                                      SUPPORTED_100baseT_Half;
 321                 phydev->supported |= SUPPORTED_FIBRE;
 322                 phydev->advertising &= ADVERTISED_100baseT_Full |
 323                                        ADVERTISED_100baseT_Half;
 324                 phydev->advertising |= ADVERTISED_FIBRE;
 325                 phydev->autoneg = AUTONEG_DISABLE;
 326         }
 327
 328         return kszphy_config_init(phydev);
 329 }
 330
 331 static int ksz8041_config_aneg(struct phy_device *phydev)
 332 {
 333         /* Skip auto-negotiation in fiber mode */
 334         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 335                 phydev->speed = SPEED_100;
 336                 return 0;
 337         }
 338
 339         return genphy_config_aneg(phydev);
 340 }
 341
 342 static int ksz8061_config_init(struct phy_device *phydev)
 343 {
 344         int ret;
 345
 346         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 347         if (ret)
 348                 return ret;
 349
 350         return kszphy_config_init(phydev);
 351 }
 352
 353 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 354                                        const struct device_node *of_node,
 355                                        u16 reg,
 356                                        const char *field1, const char *field2,
 357                                        const char *field3, const char *field4)
 358 {
 359         int val1 = -1;
 360         int val2 = -2;
 361         int val3 = -3;
 362         int val4 = -4;
 363         int newval;
 364         int matches = 0;
 365
 366         if (!of_property_read_u32(of_node, field1, &val1))
 367                 matches++;
 368
 369         if (!of_property_read_u32(of_node, field2, &val2))
 370                 matches++;
 371
 372         if (!of_property_read_u32(of_node, field3, &val3))
 373                 matches++;
 374
 375         if (!of_property_read_u32(of_node, field4, &val4))
 376                 matches++;
 377
 378         if (!matches)
 379                 return 0;
 380
 381         if (matches < 4)
 382                 newval = kszphy_extended_read(phydev, reg);
 383         else
 384                 newval = 0;
 385
 386         if (val1 != -1)
 387                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 388
 389         if (val2 != -2)
 390                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 391
 392         if (val3 != -3)
 393                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 394
 395         if (val4 != -4)
 396                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 397
 398         return kszphy_extended_write(phydev, reg, newval);
 399 }
 400
 401 static int ksz9021_config_init(struct phy_device *phydev)
 402 {
 403         const struct device *dev = &phydev->mdio.dev;
 404         const struct device_node *of_node = dev->of_node;
 405         const struct device *dev_walker;
 406
 407         /* The Micrel driver has a deprecated option to place phy OF
 408          * properties in the MAC node. Walk up the tree of devices to
 409          * find a device with an OF node.
 410          */
 411         dev_walker = &phydev->mdio.dev;
 412         do {
 413                 of_node = dev_walker->of_node;
 414                 dev_walker = dev_walker->parent;
 415
 416         } while (!of_node && dev_walker);
 417
 418         if (of_node) {
 419                 ksz9021_load_values_from_of(phydev, of_node,
 420                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 421                                     "txen-skew-ps", "txc-skew-ps",
 422                                     "rxdv-skew-ps", "rxc-skew-ps");
 423                 ksz9021_load_values_from_of(phydev, of_node,
 424                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 425                                     "rxd0-skew-ps", "rxd1-skew-ps",
 426                                     "rxd2-skew-ps", "rxd3-skew-ps");
 427                 ksz9021_load_values_from_of(phydev, of_node,
 428                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 429                                     "txd0-skew-ps", "txd1-skew-ps",
 430                                     "txd2-skew-ps", "txd3-skew-ps");
 431         }
 432         return 0;
 433 }
 434
 435 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 436 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 437 #define OP_DATA                         1
 438 #define KSZ9031_PS_TO_REG               60
 439
 440 /* Extended registers */
 441 /* MMD Address 0x0 */
 442 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 443 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 444
 445 /* MMD Address 0x2 */
 446 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 447 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 448 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 449 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 450
 451 /* MMD Address 0x1C */
 452 #define MII_KSZ9031RN_EDPD              0x23
 453 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 454
 455 static int ksz9031_extended_write(struct phy_device *phydev,
 456                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 457 {
 458         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 459         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 460         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 461         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 462 }
 463
 464 static int ksz9031_extended_read(struct phy_device *phydev,
 465                                  u8 mode, u32 dev_addr, u32 regnum)
 466 {
 467         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 468         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 469         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 470         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 471 }
 472
 473 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 474                                        const struct device_node *of_node,
 475                                        u16 reg, size_t field_sz,
 476                                        const char *field[], u8 numfields)
 477 {
 478         int val[4] = {-1, -2, -3, -4};
 479         int matches = 0;
 480         u16 mask;
 481         u16 maxval;
 482         u16 newval;
 483         int i;
 484
 485         for (i = 0; i < numfields; i++)
 486                 if (!of_property_read_u32(of_node, field[i], val + i))
 487                         matches++;
 488
 489         if (!matches)
 490                 return 0;
 491
 492         if (matches < numfields)
 493                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 494         else
 495                 newval = 0;
 496
 497         maxval = (field_sz == 4) ? 0xf : 0x1f;
 498         for (i = 0; i < numfields; i++)
 499                 if (val[i] != -(i + 1)) {
 500                         mask = 0xffff;
 501                         mask ^= maxval << (field_sz * i);
 502                         newval = (newval & mask) |
 503                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 504                                         << (field_sz * i));
 505                 }
 506
 507         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 508 }
 509
 510 /* Center KSZ9031RNX FLP timing at 16ms. */
 511 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 512 {
 513         int result;
 514
 515         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 516                                         MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
 517         if (result)
 518                 return result;
 519
 520         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 521                                         MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
 522         if (result)
 523                 return result;
 524
 525         return genphy_restart_aneg(phydev);
 526 }
 527
 528 /* Enable energy-detect power-down mode */
 529 static int ksz9031_enable_edpd(struct phy_device *phydev)
 530 {
 531         int reg;
 532
 533         reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
 534         if (reg < 0)
 535                 return reg;
 536         return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
 537                                       reg | MII_KSZ9031RN_EDPD_ENABLE);
 538 }
 539
 540 static int ksz9031_config_init(struct phy_device *phydev)
 541 {
 542         const struct device *dev = &phydev->mdio.dev;
 543         const struct device_node *of_node = dev->of_node;
 544         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 545         static const char *rx_data_skews[4] = {
 546                 "rxd0-skew-ps", "rxd1-skew-ps",
 547                 "rxd2-skew-ps", "rxd3-skew-ps"
 548         };
 549         static const char *tx_data_skews[4] = {
 550                 "txd0-skew-ps", "txd1-skew-ps",
 551                 "txd2-skew-ps", "txd3-skew-ps"
 552         };
 553         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 554         const struct device *dev_walker;
 555         int result;
 556
 557         result = ksz9031_enable_edpd(phydev);
 558         if (result < 0)
 559                 return result;
 560
 561         /* The Micrel driver has a deprecated option to place phy OF
 562          * properties in the MAC node. Walk up the tree of devices to
 563          * find a device with an OF node.
 564          */
 565         dev_walker = &phydev->mdio.dev;
 566         do {
 567                 of_node = dev_walker->of_node;
 568                 dev_walker = dev_walker->parent;
 569         } while (!of_node && dev_walker);
 570
 571         if (of_node) {
 572                 ksz9031_of_load_skew_values(phydev, of_node,
 573                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 574                                 clk_skews, 2);
 575
 576                 ksz9031_of_load_skew_values(phydev, of_node,
 577                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 578                                 control_skews, 2);
 579
 580                 ksz9031_of_load_skew_values(phydev, of_node,
 581                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 582                                 rx_data_skews, 4);
 583
 584                 ksz9031_of_load_skew_values(phydev, of_node,
 585                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 586                                 tx_data_skews, 4);
 587
 588                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
 589                  * When the device links in the 1000BASE-T slave mode only,
 590                  * the optional 125MHz reference output clock (CLK125_NDO)
 591                  * has wide duty cycle variation.
 592                  *
 593                  * The optional CLK125_NDO clock does not meet the RGMII
 594                  * 45/55 percent (min/max) duty cycle requirement and therefore
 595                  * cannot be used directly by the MAC side for clocking
 596                  * applications that have setup/hold time requirements on
 597                  * rising and falling clock edges.
 598                  *
 599                  * Workaround:
 600                  * Force the phy to be the master to receive a stable clock
 601                  * which meets the duty cycle requirement.
 602                  */
 603                 if (of_property_read_bool(of_node, "micrel,force-master")) {
 604                         result = phy_read(phydev, MII_CTRL1000);
 605                         if (result < 0)
 606                                 goto err_force_master;
 607
 608                         /* enable master mode, config & prefer master */
 609                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
 610                         result = phy_write(phydev, MII_CTRL1000, result);
 611                         if (result < 0)
 612                                 goto err_force_master;
 613                 }
 614         }
 615
 616         return ksz9031_center_flp_timing(phydev);
 617
 618 err_force_master:
 619         phydev_err(phydev, "failed to force the phy to master mode\n");
 620         return result;
 621 }
 622
 623 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 624 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 625 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 626 static int ksz8873mll_read_status(struct phy_device *phydev)
 627 {
 628         int regval;
 629
 630         /* dummy read */
 631         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 632
 633         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 634
 635         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 636                 phydev->duplex = DUPLEX_HALF;
 637         else
 638                 phydev->duplex = DUPLEX_FULL;
 639
 640         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 641                 phydev->speed = SPEED_10;
 642         else
 643                 phydev->speed = SPEED_100;
 644
 645         phydev->link = 1;
 646         phydev->pause = phydev->asym_pause = 0;
 647
 648         return 0;
 649 }
 650
 651 static int ksz9031_read_status(struct phy_device *phydev)
 652 {
 653         int err;
 654         int regval;
 655
 656         err = genphy_read_status(phydev);
 657         if (err)
 658                 return err;
 659
 660         /* Make sure the PHY is not broken. Read idle error count,
 661          * and reset the PHY if it is maxed out.
 662          */
 663         regval = phy_read(phydev, MII_STAT1000);
 664         if ((regval & 0xFF) == 0xFF) {
 665                 phy_init_hw(phydev);
 666                 phydev->link = 0;
 667                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
 668                         phydev->drv->config_intr(phydev);
 669                 return genphy_config_aneg(phydev);
 670         }
 671
 672         return 0;
 673 }
 674
 675 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 676 {
 677         return 0;
 678 }
 679
 680 static int kszphy_get_sset_count(struct phy_device *phydev)
 681 {
 682         return ARRAY_SIZE(kszphy_hw_stats);
 683 }
 684
 685 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
 686 {
 687         int i;
 688
 689         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
 690                 strlcpy(data + i * ETH_GSTRING_LEN,
 691                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
 692         }
 693 }
 694
 695 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
 696 {
 697         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
 698         struct kszphy_priv *priv = phydev->priv;
 699         int val;
 700         u64 ret;
 701
 702         val = phy_read(phydev, stat.reg);
 703         if (val < 0) {
 704                 ret = U64_MAX;
 705         } else {
 706                 val = val & ((1 << stat.bits) - 1);
 707                 priv->stats[i] += val;
 708                 ret = priv->stats[i];
 709         }
 710
 711         return ret;
 712 }
 713
 714 static void kszphy_get_stats(struct phy_device *phydev,
 715                              struct ethtool_stats *stats, u64 *data)
 716 {
 717         int i;
 718
 719         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
 720                 data[i] = kszphy_get_stat(phydev, i);
 721 }
 722
 723 static int kszphy_suspend(struct phy_device *phydev)
 724 {
 725         /* Disable PHY Interrupts */
 726         if (phy_interrupt_is_valid(phydev)) {
 727                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
 728                 if (phydev->drv->config_intr)
 729                         phydev->drv->config_intr(phydev);
 730         }
 731
 732         return genphy_suspend(phydev);
 733 }
 734
 735 static int kszphy_resume(struct phy_device *phydev)
 736 {
 737         int ret;
 738
 739         genphy_resume(phydev);
 740
 741         ret = kszphy_config_reset(phydev);
 742         if (ret)
 743                 return ret;
 744
 745         /* Enable PHY Interrupts */
 746         if (phy_interrupt_is_valid(phydev)) {
 747                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
 748                 if (phydev->drv->config_intr)
 749                         phydev->drv->config_intr(phydev);
 750         }
 751
 752         return 0;
 753 }
 754
 755 static int kszphy_probe(struct phy_device *phydev)
 756 {
 757         const struct kszphy_type *type = phydev->drv->driver_data;
 758         const struct device_node *np = phydev->mdio.dev.of_node;
 759         struct kszphy_priv *priv;
 760         struct clk *clk;
 761         int ret;
 762
 763         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 764         if (!priv)
 765                 return -ENOMEM;
 766
 767         phydev->priv = priv;
 768
 769         priv->type = type;
 770
 771         if (type->led_mode_reg) {
 772                 ret = of_property_read_u32(np, "micrel,led-mode",
 773                                 &priv->led_mode);
 774                 if (ret)
 775                         priv->led_mode = -1;
 776
 777                 if (priv->led_mode > 3) {
 778                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
 779                                    priv->led_mode);
 780                         priv->led_mode = -1;
 781                 }
 782         } else {
 783                 priv->led_mode = -1;
 784         }
 785
 786         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
 787         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 788         if (!IS_ERR_OR_NULL(clk)) {
 789                 unsigned long rate = clk_get_rate(clk);
 790                 bool rmii_ref_clk_sel_25_mhz;
 791
 792                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 793                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 794                                 "micrel,rmii-reference-clock-select-25-mhz");
 795
 796                 if (rate > 24500000 && rate < 25500000) {
 797                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 798                 } else if (rate > 49500000 && rate < 50500000) {
 799                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 800                 } else {
 801                         phydev_err(phydev, "Clock rate out of range: %ld\n",
 802                                    rate);
 803                         return -EINVAL;
 804                 }
 805         }
 806
 807         /* Support legacy board-file configuration */
 808         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 809                 priv->rmii_ref_clk_sel = true;
 810                 priv->rmii_ref_clk_sel_val = true;
 811         }
 812
 813         return 0;
 814 }
 815
 816 static struct phy_driver ksphy_driver[] = {
 817 {
 818         .phy_id         = PHY_ID_KS8737,
 819         .phy_id_mask    = MICREL_PHY_ID_MASK,
 820         .name           = "Micrel KS8737",
 821         .features       = PHY_BASIC_FEATURES,
 822         .flags          = PHY_HAS_INTERRUPT,
 823         .driver_data    = &ks8737_type,
 824         .config_init    = kszphy_config_init,
 825         .ack_interrupt  = kszphy_ack_interrupt,
 826         .config_intr    = kszphy_config_intr,
 827         .suspend        = genphy_suspend,
 828         .resume         = genphy_resume,
 829 }, {
 830         .phy_id         = PHY_ID_KSZ8021,
 831         .phy_id_mask    = 0x00ffffff,
 832         .name           = "Micrel KSZ8021 or KSZ8031",
 833         .features       = PHY_BASIC_FEATURES,
 834         .flags          = PHY_HAS_INTERRUPT,
 835         .driver_data    = &ksz8021_type,
 836         .probe          = kszphy_probe,
 837         .config_init    = kszphy_config_init,
 838         .ack_interrupt  = kszphy_ack_interrupt,
 839         .config_intr    = kszphy_config_intr,
 840         .get_sset_count = kszphy_get_sset_count,
 841         .get_strings    = kszphy_get_strings,
 842         .get_stats      = kszphy_get_stats,
 843         .suspend        = genphy_suspend,
 844         .resume         = genphy_resume,
 845 }, {
 846         .phy_id         = PHY_ID_KSZ8031,
 847         .phy_id_mask    = 0x00ffffff,
 848         .name           = "Micrel KSZ8031",
 849         .features       = PHY_BASIC_FEATURES,
 850         .flags          = PHY_HAS_INTERRUPT,
 851         .driver_data    = &ksz8021_type,
 852         .probe          = kszphy_probe,
 853         .config_init    = kszphy_config_init,
 854         .ack_interrupt  = kszphy_ack_interrupt,
 855         .config_intr    = kszphy_config_intr,
 856         .get_sset_count = kszphy_get_sset_count,
 857         .get_strings    = kszphy_get_strings,
 858         .get_stats      = kszphy_get_stats,
 859         .suspend        = genphy_suspend,
 860         .resume         = genphy_resume,
 861 }, {
 862         .phy_id         = PHY_ID_KSZ8041,
 863         .phy_id_mask    = MICREL_PHY_ID_MASK,
 864         .name           = "Micrel KSZ8041",
 865         .features       = PHY_BASIC_FEATURES,
 866         .flags          = PHY_HAS_INTERRUPT,
 867         .driver_data    = &ksz8041_type,
 868         .probe          = kszphy_probe,
 869         .config_init    = ksz8041_config_init,
 870         .config_aneg    = ksz8041_config_aneg,
 871         .ack_interrupt  = kszphy_ack_interrupt,
 872         .config_intr    = kszphy_config_intr,
 873         .get_sset_count = kszphy_get_sset_count,
 874         .get_strings    = kszphy_get_strings,
 875         .get_stats      = kszphy_get_stats,
 876         .suspend        = genphy_suspend,
 877         .resume         = genphy_resume,
 878 }, {
 879         .phy_id         = PHY_ID_KSZ8041RNLI,
 880         .phy_id_mask    = MICREL_PHY_ID_MASK,
 881         .name           = "Micrel KSZ8041RNLI",
 882         .features       = PHY_BASIC_FEATURES,
 883         .flags          = PHY_HAS_INTERRUPT,
 884         .driver_data    = &ksz8041_type,
 885         .probe          = kszphy_probe,
 886         .config_init    = kszphy_config_init,
 887         .ack_interrupt  = kszphy_ack_interrupt,
 888         .config_intr    = kszphy_config_intr,
 889         .get_sset_count = kszphy_get_sset_count,
 890         .get_strings    = kszphy_get_strings,
 891         .get_stats      = kszphy_get_stats,
 892         .suspend        = genphy_suspend,
 893         .resume         = genphy_resume,
 894 }, {
 895         .phy_id         = PHY_ID_KSZ8051,
 896         .phy_id_mask    = MICREL_PHY_ID_MASK,
 897         .name           = "Micrel KSZ8051",
 898         .features       = PHY_BASIC_FEATURES,
 899         .flags          = PHY_HAS_INTERRUPT,
 900         .driver_data    = &ksz8051_type,
 901         .probe          = kszphy_probe,
 902         .config_init    = kszphy_config_init,
 903         .ack_interrupt  = kszphy_ack_interrupt,
 904         .config_intr    = kszphy_config_intr,
 905         .get_sset_count = kszphy_get_sset_count,
 906         .get_strings    = kszphy_get_strings,
 907         .get_stats      = kszphy_get_stats,
 908         .suspend        = genphy_suspend,
 909         .resume         = genphy_resume,
 910 }, {
 911         .phy_id         = PHY_ID_KSZ8001,
 912         .name           = "Micrel KSZ8001 or KS8721",
 913         .phy_id_mask    = 0x00fffffc,
 914         .features       = PHY_BASIC_FEATURES,
 915         .flags          = PHY_HAS_INTERRUPT,
 916         .driver_data    = &ksz8041_type,
 917         .probe          = kszphy_probe,
 918         .config_init    = kszphy_config_init,
 919         .ack_interrupt  = kszphy_ack_interrupt,
 920         .config_intr    = kszphy_config_intr,
 921         .get_sset_count = kszphy_get_sset_count,
 922         .get_strings    = kszphy_get_strings,
 923         .get_stats      = kszphy_get_stats,
 924         .suspend        = genphy_suspend,
 925         .resume         = genphy_resume,
 926 }, {
 927         .phy_id         = PHY_ID_KSZ8081,
 928         .name           = "Micrel KSZ8081 or KSZ8091",
 929         .phy_id_mask    = MICREL_PHY_ID_MASK,
 930         .features       = PHY_BASIC_FEATURES,
 931         .flags          = PHY_HAS_INTERRUPT,
 932         .driver_data    = &ksz8081_type,
 933         .probe          = kszphy_probe,
 934         .config_init    = kszphy_config_init,
 935         .ack_interrupt  = kszphy_ack_interrupt,
 936         .config_intr    = kszphy_config_intr,
 937         .get_sset_count = kszphy_get_sset_count,
 938         .get_strings    = kszphy_get_strings,
 939         .get_stats      = kszphy_get_stats,
 940         .suspend        = kszphy_suspend,
 941         .resume         = kszphy_resume,
 942 }, {
 943         .phy_id         = PHY_ID_KSZ8061,
 944         .name           = "Micrel KSZ8061",
 945         .phy_id_mask    = MICREL_PHY_ID_MASK,
 946         .features       = PHY_BASIC_FEATURES,
 947         .flags          = PHY_HAS_INTERRUPT,
 948         .config_init    = ksz8061_config_init,
 949         .ack_interrupt  = kszphy_ack_interrupt,
 950         .config_intr    = kszphy_config_intr,
 951         .suspend        = genphy_suspend,
 952         .resume         = genphy_resume,
 953 }, {
 954         .phy_id         = PHY_ID_KSZ9021,
 955         .phy_id_mask    = 0x000ffffe,
 956         .name           = "Micrel KSZ9021 Gigabit PHY",
 957         .features       = PHY_GBIT_FEATURES,
 958         .flags          = PHY_HAS_INTERRUPT,
 959         .driver_data    = &ksz9021_type,
 960         .probe          = kszphy_probe,
 961         .config_init    = ksz9021_config_init,
 962         .ack_interrupt  = kszphy_ack_interrupt,
 963         .config_intr    = kszphy_config_intr,
 964         .get_sset_count = kszphy_get_sset_count,
 965         .get_strings    = kszphy_get_strings,
 966         .get_stats      = kszphy_get_stats,
 967         .suspend        = genphy_suspend,
 968         .resume         = genphy_resume,
 969         .read_mmd       = genphy_read_mmd_unsupported,
 970         .write_mmd      = genphy_write_mmd_unsupported,
 971 }, {
 972         .phy_id         = PHY_ID_KSZ9031,
 973         .phy_id_mask    = MICREL_PHY_ID_MASK,
 974         .name           = "Micrel KSZ9031 Gigabit PHY",
 975         .features       = PHY_GBIT_FEATURES,
 976         .flags          = PHY_HAS_INTERRUPT,
 977         .driver_data    = &ksz9021_type,
 978         .probe          = kszphy_probe,
 979         .config_init    = ksz9031_config_init,
 980         .read_status    = ksz9031_read_status,
 981         .ack_interrupt  = kszphy_ack_interrupt,
 982         .config_intr    = kszphy_config_intr,
 983         .get_sset_count = kszphy_get_sset_count,
 984         .get_strings    = kszphy_get_strings,
 985         .get_stats      = kszphy_get_stats,
 986         .suspend        = genphy_suspend,
 987         .resume         = kszphy_resume,
 988 }, {
 989         .phy_id         = PHY_ID_KSZ8873MLL,
 990         .phy_id_mask    = MICREL_PHY_ID_MASK,
 991         .name           = "Micrel KSZ8873MLL Switch",
 992         .config_init    = kszphy_config_init,
 993         .config_aneg    = ksz8873mll_config_aneg,
 994         .read_status    = ksz8873mll_read_status,
 995         .suspend        = genphy_suspend,
 996         .resume         = genphy_resume,
 997 }, {
 998         .phy_id         = PHY_ID_KSZ886X,
 999         .phy_id_mask    = MICREL_PHY_ID_MASK,
1000         .name           = "Micrel KSZ886X Switch",
1001         .features       = PHY_BASIC_FEATURES,
1002         .flags          = PHY_HAS_INTERRUPT,
1003         .config_init    = kszphy_config_init,
1004         .suspend        = genphy_suspend,
1005         .resume         = genphy_resume,
1006 }, {
1007         .phy_id         = PHY_ID_KSZ8795,
1008         .phy_id_mask    = MICREL_PHY_ID_MASK,
1009         .name           = "Micrel KSZ8795",
1010         .features       = PHY_BASIC_FEATURES,
1011         .flags          = PHY_HAS_INTERRUPT,
1012         .config_init    = kszphy_config_init,
1013         .config_aneg    = ksz8873mll_config_aneg,
1014         .read_status    = ksz8873mll_read_status,
1015         .suspend        = genphy_suspend,
1016         .resume         = genphy_resume,
1017 }, {
1018         .phy_id         = PHY_ID_KSZ9477,
1019         .phy_id_mask    = MICREL_PHY_ID_MASK,
1020         .name           = "Microchip KSZ9477",
1021         .features       = PHY_GBIT_FEATURES,
1022         .config_init    = kszphy_config_init,
1023         .suspend        = genphy_suspend,
1024         .resume         = genphy_resume,
1025 } };
1026
1027 module_phy_driver(ksphy_driver);
1028
1029 MODULE_DESCRIPTION("Micrel PHY driver");
1030 MODULE_AUTHOR("David J. Choi");
1031 MODULE_LICENSE("GPL");
1032
1033 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1034         { PHY_ID_KSZ9021, 0x000ffffe },
1035         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1036         { PHY_ID_KSZ8001, 0x00fffffc },
1037         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1038         { PHY_ID_KSZ8021, 0x00ffffff },
1039         { PHY_ID_KSZ8031, 0x00ffffff },
1040         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1041         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1042         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1043         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1044         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1045         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1046         { }
1047 };
1048
1049 MODULE_DEVICE_TABLE(mdio, micrel_tbl);