drivers/net/phy/mediatek-ge-soc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <linux/bitfield.h>
   3 #include <linux/bitmap.h>
   4 #include <linux/mfd/syscon.h>
   5 #include <linux/module.h>
   6 #include <linux/nvmem-consumer.h>
   7 #include <linux/pinctrl/consumer.h>
   8 #include <linux/phy.h>
   9 #include <linux/regmap.h>
  10
  11 #define MTK_GPHY_ID_MT7981                      0x03a29461
  12 #define MTK_GPHY_ID_MT7988                      0x03a29481
  13
  14 #define MTK_EXT_PAGE_ACCESS                     0x1f
  15 #define MTK_PHY_PAGE_STANDARD                   0x0000
  16 #define MTK_PHY_PAGE_EXTENDED_3                 0x0003
  17
  18 #define MTK_PHY_LPI_REG_14                      0x14
  19 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK        GENMASK(8, 0)
  20
  21 #define MTK_PHY_LPI_REG_1c                      0x1c
  22 #define MTK_PHY_SMI_DET_ON_THRESH_MASK          GENMASK(13, 8)
  23
  24 #define MTK_PHY_PAGE_EXTENDED_2A30              0x2a30
  25 #define MTK_PHY_PAGE_EXTENDED_52B5              0x52b5
  26
  27 #define ANALOG_INTERNAL_OPERATION_MAX_US        20
  28 #define TXRESERVE_MIN                           0
  29 #define TXRESERVE_MAX                           7
  30
  31 #define MTK_PHY_ANARG_RG                        0x10
  32 #define   MTK_PHY_TCLKOFFSET_MASK               GENMASK(12, 8)
  33
  34 /* Registers on MDIO_MMD_VEND1 */
  35 #define MTK_PHY_TXVLD_DA_RG                     0x12
  36 #define   MTK_PHY_DA_TX_I2MPB_A_GBE_MASK        GENMASK(15, 10)
  37 #define   MTK_PHY_DA_TX_I2MPB_A_TBT_MASK        GENMASK(5, 0)
  38
  39 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2           0x16
  40 #define   MTK_PHY_DA_TX_I2MPB_A_HBT_MASK        GENMASK(15, 10)
  41 #define   MTK_PHY_DA_TX_I2MPB_A_TST_MASK        GENMASK(5, 0)
  42
  43 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1           0x17
  44 #define   MTK_PHY_DA_TX_I2MPB_B_GBE_MASK        GENMASK(13, 8)
  45 #define   MTK_PHY_DA_TX_I2MPB_B_TBT_MASK        GENMASK(5, 0)
  46
  47 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2           0x18
  48 #define   MTK_PHY_DA_TX_I2MPB_B_HBT_MASK        GENMASK(13, 8)
  49 #define   MTK_PHY_DA_TX_I2MPB_B_TST_MASK        GENMASK(5, 0)
  50
  51 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1           0x19
  52 #define   MTK_PHY_DA_TX_I2MPB_C_GBE_MASK        GENMASK(13, 8)
  53 #define   MTK_PHY_DA_TX_I2MPB_C_TBT_MASK        GENMASK(5, 0)
  54
  55 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2           0x20
  56 #define   MTK_PHY_DA_TX_I2MPB_C_HBT_MASK        GENMASK(13, 8)
  57 #define   MTK_PHY_DA_TX_I2MPB_C_TST_MASK        GENMASK(5, 0)
  58
  59 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1           0x21
  60 #define   MTK_PHY_DA_TX_I2MPB_D_GBE_MASK        GENMASK(13, 8)
  61 #define   MTK_PHY_DA_TX_I2MPB_D_TBT_MASK        GENMASK(5, 0)
  62
  63 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2           0x22
  64 #define   MTK_PHY_DA_TX_I2MPB_D_HBT_MASK        GENMASK(13, 8)
  65 #define   MTK_PHY_DA_TX_I2MPB_D_TST_MASK        GENMASK(5, 0)
  66
  67 #define MTK_PHY_RXADC_CTRL_RG7                  0xc6
  68 #define   MTK_PHY_DA_AD_BUF_BIAS_LP_MASK        GENMASK(9, 8)
  69
  70 #define MTK_PHY_RXADC_CTRL_RG9                  0xc8
  71 #define   MTK_PHY_DA_RX_PSBN_TBT_MASK           GENMASK(14, 12)
  72 #define   MTK_PHY_DA_RX_PSBN_HBT_MASK           GENMASK(10, 8)
  73 #define   MTK_PHY_DA_RX_PSBN_GBE_MASK           GENMASK(6, 4)
  74 #define   MTK_PHY_DA_RX_PSBN_LP_MASK            GENMASK(2, 0)
  75
  76 #define MTK_PHY_LDO_OUTPUT_V                    0xd7
  77
  78 #define MTK_PHY_RG_ANA_CAL_RG0                  0xdb
  79 #define   MTK_PHY_RG_CAL_CKINV                  BIT(12)
  80 #define   MTK_PHY_RG_ANA_CALEN                  BIT(8)
  81 #define   MTK_PHY_RG_ZCALEN_A                   BIT(0)
  82
  83 #define MTK_PHY_RG_ANA_CAL_RG1                  0xdc
  84 #define   MTK_PHY_RG_ZCALEN_B                   BIT(12)
  85 #define   MTK_PHY_RG_ZCALEN_C                   BIT(8)
  86 #define   MTK_PHY_RG_ZCALEN_D                   BIT(4)
  87 #define   MTK_PHY_RG_TXVOS_CALEN                BIT(0)
  88
  89 #define MTK_PHY_RG_ANA_CAL_RG5                  0xe0
  90 #define   MTK_PHY_RG_REXT_TRIM_MASK             GENMASK(13, 8)
  91
  92 #define MTK_PHY_RG_TX_FILTER                    0xfe
  93
  94 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120      0x120
  95 #define   MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
  96 #define   MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
  97
  98 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122      0x122
  99 #define   MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK       GENMASK(7, 0)
 100
 101 #define MTK_PHY_RG_TESTMUX_ADC_CTRL             0x144
 102 #define   MTK_PHY_RG_TXEN_DIG_MASK              GENMASK(5, 5)
 103
 104 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B         0x172
 105 #define   MTK_PHY_CR_TX_AMP_OFFSET_A_MASK       GENMASK(13, 8)
 106 #define   MTK_PHY_CR_TX_AMP_OFFSET_B_MASK       GENMASK(6, 0)
 107
 108 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D         0x173
 109 #define   MTK_PHY_CR_TX_AMP_OFFSET_C_MASK       GENMASK(13, 8)
 110 #define   MTK_PHY_CR_TX_AMP_OFFSET_D_MASK       GENMASK(6, 0)
 111
 112 #define MTK_PHY_RG_AD_CAL_COMP                  0x17a
 113 #define   MTK_PHY_AD_CAL_COMP_OUT_SHIFT         (8)
 114
 115 #define MTK_PHY_RG_AD_CAL_CLK                   0x17b
 116 #define   MTK_PHY_DA_CAL_CLK                    BIT(0)
 117
 118 #define MTK_PHY_RG_AD_CALIN                     0x17c
 119 #define   MTK_PHY_DA_CALIN_FLAG                 BIT(0)
 120
 121 #define MTK_PHY_RG_DASN_DAC_IN0_A               0x17d
 122 #define   MTK_PHY_DASN_DAC_IN0_A_MASK           GENMASK(9, 0)
 123
 124 #define MTK_PHY_RG_DASN_DAC_IN0_B               0x17e
 125 #define   MTK_PHY_DASN_DAC_IN0_B_MASK           GENMASK(9, 0)
 126
 127 #define MTK_PHY_RG_DASN_DAC_IN0_C               0x17f
 128 #define   MTK_PHY_DASN_DAC_IN0_C_MASK           GENMASK(9, 0)
 129
 130 #define MTK_PHY_RG_DASN_DAC_IN0_D               0x180
 131 #define   MTK_PHY_DASN_DAC_IN0_D_MASK           GENMASK(9, 0)
 132
 133 #define MTK_PHY_RG_DASN_DAC_IN1_A               0x181
 134 #define   MTK_PHY_DASN_DAC_IN1_A_MASK           GENMASK(9, 0)
 135
 136 #define MTK_PHY_RG_DASN_DAC_IN1_B               0x182
 137 #define   MTK_PHY_DASN_DAC_IN1_B_MASK           GENMASK(9, 0)
 138
 139 #define MTK_PHY_RG_DASN_DAC_IN1_C               0x183
 140 #define   MTK_PHY_DASN_DAC_IN1_C_MASK           GENMASK(9, 0)
 141
 142 #define MTK_PHY_RG_DASN_DAC_IN1_D               0x184
 143 #define   MTK_PHY_DASN_DAC_IN1_D_MASK           GENMASK(9, 0)
 144
 145 #define MTK_PHY_RG_DEV1E_REG19b                 0x19b
 146 #define   MTK_PHY_BYPASS_DSP_LPI_READY          BIT(8)
 147
 148 #define MTK_PHY_RG_LP_IIR2_K1_L                 0x22a
 149 #define MTK_PHY_RG_LP_IIR2_K1_U                 0x22b
 150 #define MTK_PHY_RG_LP_IIR2_K2_L                 0x22c
 151 #define MTK_PHY_RG_LP_IIR2_K2_U                 0x22d
 152 #define MTK_PHY_RG_LP_IIR2_K3_L                 0x22e
 153 #define MTK_PHY_RG_LP_IIR2_K3_U                 0x22f
 154 #define MTK_PHY_RG_LP_IIR2_K4_L                 0x230
 155 #define MTK_PHY_RG_LP_IIR2_K4_U                 0x231
 156 #define MTK_PHY_RG_LP_IIR2_K5_L                 0x232
 157 #define MTK_PHY_RG_LP_IIR2_K5_U                 0x233
 158
 159 #define MTK_PHY_RG_DEV1E_REG234                 0x234
 160 #define   MTK_PHY_TR_OPEN_LOOP_EN_MASK          GENMASK(0, 0)
 161 #define   MTK_PHY_LPF_X_AVERAGE_MASK            GENMASK(7, 4)
 162 #define   MTK_PHY_TR_LP_IIR_EEE_EN              BIT(12)
 163
 164 #define MTK_PHY_RG_LPF_CNT_VAL                  0x235
 165
 166 #define MTK_PHY_RG_DEV1E_REG238                 0x238
 167 #define   MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK    GENMASK(8, 0)
 168 #define   MTK_PHY_LPI_SLV_SEND_TX_EN            BIT(12)
 169
 170 #define MTK_PHY_RG_DEV1E_REG239                 0x239
 171 #define   MTK_PHY_LPI_SEND_LOC_TIMER_MASK       GENMASK(8, 0)
 172 #define   MTK_PHY_LPI_TXPCS_LOC_RCV             BIT(12)
 173
 174 #define MTK_PHY_RG_DEV1E_REG27C                 0x27c
 175 #define   MTK_PHY_VGASTATE_FFE_THR_ST1_MASK     GENMASK(12, 8)
 176 #define MTK_PHY_RG_DEV1E_REG27D                 0x27d
 177 #define   MTK_PHY_VGASTATE_FFE_THR_ST2_MASK     GENMASK(4, 0)
 178
 179 #define MTK_PHY_RG_DEV1E_REG2C7                 0x2c7
 180 #define   MTK_PHY_MAX_GAIN_MASK                 GENMASK(4, 0)
 181 #define   MTK_PHY_MIN_GAIN_MASK                 GENMASK(12, 8)
 182
 183 #define MTK_PHY_RG_DEV1E_REG2D1                 0x2d1
 184 #define   MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK  GENMASK(7, 0)
 185 #define   MTK_PHY_LPI_SKIP_SD_SLV_TR            BIT(8)
 186 #define   MTK_PHY_LPI_TR_READY                  BIT(9)
 187 #define   MTK_PHY_LPI_VCO_EEE_STG0_EN           BIT(10)
 188
 189 #define MTK_PHY_RG_DEV1E_REG323                 0x323
 190 #define   MTK_PHY_EEE_WAKE_MAS_INT_DC           BIT(0)
 191 #define   MTK_PHY_EEE_WAKE_SLV_INT_DC           BIT(4)
 192
 193 #define MTK_PHY_RG_DEV1E_REG324                 0x324
 194 #define   MTK_PHY_SMI_DETCNT_MAX_MASK           GENMASK(5, 0)
 195 #define   MTK_PHY_SMI_DET_MAX_EN                BIT(8)
 196
 197 #define MTK_PHY_RG_DEV1E_REG326                 0x326
 198 #define   MTK_PHY_LPI_MODE_SD_ON                BIT(0)
 199 #define   MTK_PHY_RESET_RANDUPD_CNT             BIT(1)
 200 #define   MTK_PHY_TREC_UPDATE_ENAB_CLR          BIT(2)
 201 #define   MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
 202 #define   MTK_PHY_TR_READY_SKIP_AFE_WAKEUP      BIT(5)
 203
 204 #define MTK_PHY_LDO_PUMP_EN_PAIRAB              0x502
 205 #define MTK_PHY_LDO_PUMP_EN_PAIRCD              0x503
 206
 207 #define MTK_PHY_DA_TX_R50_PAIR_A                0x53d
 208 #define MTK_PHY_DA_TX_R50_PAIR_B                0x53e
 209 #define MTK_PHY_DA_TX_R50_PAIR_C                0x53f
 210 #define MTK_PHY_DA_TX_R50_PAIR_D                0x540
 211
 212 /* Registers on MDIO_MMD_VEND2 */
 213 #define MTK_PHY_LED0_ON_CTRL                    0x24
 214 #define MTK_PHY_LED1_ON_CTRL                    0x26
 215 #define   MTK_PHY_LED_ON_MASK                   GENMASK(6, 0)
 216 #define   MTK_PHY_LED_ON_LINK1000               BIT(0)
 217 #define   MTK_PHY_LED_ON_LINK100                BIT(1)
 218 #define   MTK_PHY_LED_ON_LINK10                 BIT(2)
 219 #define   MTK_PHY_LED_ON_LINKDOWN               BIT(3)
 220 #define   MTK_PHY_LED_ON_FDX                    BIT(4) /* Full duplex */
 221 #define   MTK_PHY_LED_ON_HDX                    BIT(5) /* Half duplex */
 222 #define   MTK_PHY_LED_ON_FORCE_ON               BIT(6)
 223 #define   MTK_PHY_LED_ON_POLARITY               BIT(14)
 224 #define   MTK_PHY_LED_ON_ENABLE                 BIT(15)
 225
 226 #define MTK_PHY_LED0_BLINK_CTRL                 0x25
 227 #define MTK_PHY_LED1_BLINK_CTRL                 0x27
 228 #define   MTK_PHY_LED_BLINK_1000TX              BIT(0)
 229 #define   MTK_PHY_LED_BLINK_1000RX              BIT(1)
 230 #define   MTK_PHY_LED_BLINK_100TX               BIT(2)
 231 #define   MTK_PHY_LED_BLINK_100RX               BIT(3)
 232 #define   MTK_PHY_LED_BLINK_10TX                BIT(4)
 233 #define   MTK_PHY_LED_BLINK_10RX                BIT(5)
 234 #define   MTK_PHY_LED_BLINK_COLLISION           BIT(6)
 235 #define   MTK_PHY_LED_BLINK_RX_CRC_ERR          BIT(7)
 236 #define   MTK_PHY_LED_BLINK_RX_IDLE_ERR         BIT(8)
 237 #define   MTK_PHY_LED_BLINK_FORCE_BLINK         BIT(9)
 238
 239 #define MTK_PHY_LED1_DEFAULT_POLARITIES         BIT(1)
 240
 241 #define MTK_PHY_RG_BG_RASEL                     0x115
 242 #define   MTK_PHY_RG_BG_RASEL_MASK              GENMASK(2, 0)
 243
 244 /* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
 245 #define RG_GPIO_MISC_TPBANK0                    0x6f0
 246 #define   RG_GPIO_MISC_TPBANK0_BOOTMODE         GENMASK(11, 8)
 247
 248 /* These macro privides efuse parsing for internal phy. */
 249 #define EFS_DA_TX_I2MPB_A(x)                    (((x) >> 0) & GENMASK(5, 0))
 250 #define EFS_DA_TX_I2MPB_B(x)                    (((x) >> 6) & GENMASK(5, 0))
 251 #define EFS_DA_TX_I2MPB_C(x)                    (((x) >> 12) & GENMASK(5, 0))
 252 #define EFS_DA_TX_I2MPB_D(x)                    (((x) >> 18) & GENMASK(5, 0))
 253 #define EFS_DA_TX_AMP_OFFSET_A(x)               (((x) >> 24) & GENMASK(5, 0))
 254
 255 #define EFS_DA_TX_AMP_OFFSET_B(x)               (((x) >> 0) & GENMASK(5, 0))
 256 #define EFS_DA_TX_AMP_OFFSET_C(x)               (((x) >> 6) & GENMASK(5, 0))
 257 #define EFS_DA_TX_AMP_OFFSET_D(x)               (((x) >> 12) & GENMASK(5, 0))
 258 #define EFS_DA_TX_R50_A(x)                      (((x) >> 18) & GENMASK(5, 0))
 259 #define EFS_DA_TX_R50_B(x)                      (((x) >> 24) & GENMASK(5, 0))
 260
 261 #define EFS_DA_TX_R50_C(x)                      (((x) >> 0) & GENMASK(5, 0))
 262 #define EFS_DA_TX_R50_D(x)                      (((x) >> 6) & GENMASK(5, 0))
 263
 264 #define EFS_RG_BG_RASEL(x)                      (((x) >> 4) & GENMASK(2, 0))
 265 #define EFS_RG_REXT_TRIM(x)                     (((x) >> 7) & GENMASK(5, 0))
 266
 267 enum {
 268         NO_PAIR,
 269         PAIR_A,
 270         PAIR_B,
 271         PAIR_C,
 272         PAIR_D,
 273 };
 274
 275 enum calibration_mode {
 276         EFUSE_K,
 277         SW_K
 278 };
 279
 280 enum CAL_ITEM {
 281         REXT,
 282         TX_OFFSET,
 283         TX_AMP,
 284         TX_R50,
 285         TX_VCM
 286 };
 287
 288 enum CAL_MODE {
 289         EFUSE_M,
 290         SW_M
 291 };
 292
 293 #define MTK_PHY_LED_STATE_FORCE_ON      0
 294 #define MTK_PHY_LED_STATE_FORCE_BLINK   1
 295 #define MTK_PHY_LED_STATE_NETDEV        2
 296
 297 struct mtk_socphy_priv {
 298         unsigned long           led_state;
 299 };
 300
 301 struct mtk_socphy_shared {
 302         u32                     boottrap;
 303         struct mtk_socphy_priv  priv[4];
 304 };
 305
 306 static int mtk_socphy_read_page(struct phy_device *phydev)
 307 {
 308         return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
 309 }
 310
 311 static int mtk_socphy_write_page(struct phy_device *phydev, int page)
 312 {
 313         return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
 314 }
 315
 316 /* One calibration cycle consists of:
 317  * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
 318  *   until AD_CAL_COMP is ready to output calibration result.
 319  * 2.Wait until DA_CAL_CLK is available.
 320  * 3.Fetch AD_CAL_COMP_OUT.
 321  */
 322 static int cal_cycle(struct phy_device *phydev, int devad,
 323                      u32 regnum, u16 mask, u16 cal_val)
 324 {
 325         int reg_val;
 326         int ret;
 327
 328         phy_modify_mmd(phydev, devad, regnum,
 329                        mask, cal_val);
 330         phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
 331                          MTK_PHY_DA_CALIN_FLAG);
 332
 333         ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
 334                                         MTK_PHY_RG_AD_CAL_CLK, reg_val,
 335                                         reg_val & MTK_PHY_DA_CAL_CLK, 500,
 336                                         ANALOG_INTERNAL_OPERATION_MAX_US, false);
 337         if (ret) {
 338                 phydev_err(phydev, "Calibration cycle timeout\n");
 339                 return ret;
 340         }
 341
 342         phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
 343                            MTK_PHY_DA_CALIN_FLAG);
 344         ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
 345                            MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
 346         phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
 347
 348         return ret;
 349 }
 350
 351 static int rext_fill_result(struct phy_device *phydev, u16 *buf)
 352 {
 353         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
 354                        MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
 355         phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
 356                        MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
 357
 358         return 0;
 359 }
 360
 361 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
 362 {
 363         u16 rext_cal_val[2];
 364
 365         rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
 366         rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
 367         rext_fill_result(phydev, rext_cal_val);
 368
 369         return 0;
 370 }
 371
 372 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
 373 {
 374         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
 375                        MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
 376         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
 377                        MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
 378         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
 379                        MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
 380         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
 381                        MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
 382
 383         return 0;
 384 }
 385
 386 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
 387 {
 388         u16 tx_offset_cal_val[4];
 389
 390         tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
 391         tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
 392         tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
 393         tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
 394
 395         tx_offset_fill_result(phydev, tx_offset_cal_val);
 396
 397         return 0;
 398 }
 399
 400 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
 401 {
 402         int i;
 403         int bias[16] = {};
 404         const int vals_9461[16] = { 7, 1, 4, 7,
 405                                     7, 1, 4, 7,
 406                                     7, 1, 4, 7,
 407                                     7, 1, 4, 7 };
 408         const int vals_9481[16] = { 10, 6, 6, 10,
 409                                     10, 6, 6, 10,
 410                                     10, 6, 6, 10,
 411                                     10, 6, 6, 10 };
 412         switch (phydev->drv->phy_id) {
 413         case MTK_GPHY_ID_MT7981:
 414                 /* We add some calibration to efuse values
 415                  * due to board level influence.
 416                  * GBE: +7, TBT: +1, HBT: +4, TST: +7
 417                  */
 418                 memcpy(bias, (const void *)vals_9461, sizeof(bias));
 419                 break;
 420         case MTK_GPHY_ID_MT7988:
 421                 memcpy(bias, (const void *)vals_9481, sizeof(bias));
 422                 break;
 423         }
 424
 425         /* Prevent overflow */
 426         for (i = 0; i < 12; i++) {
 427                 if (buf[i >> 2] + bias[i] > 63) {
 428                         buf[i >> 2] = 63;
 429                         bias[i] = 0;
 430                 }
 431         }
 432
 433         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
 434                        MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
 435         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
 436                        MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
 437         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
 438                        MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
 439         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
 440                        MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
 441
 442         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
 443                        MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
 444         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
 445                        MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
 446         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
 447                        MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
 448         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
 449                        MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
 450
 451         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
 452                        MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
 453         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
 454                        MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
 455         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
 456                        MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
 457         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
 458                        MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
 459
 460         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
 461                        MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
 462         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
 463                        MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
 464         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
 465                        MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
 466         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
 467                        MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
 468
 469         return 0;
 470 }
 471
 472 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
 473 {
 474         u16 tx_amp_cal_val[4];
 475
 476         tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
 477         tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
 478         tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
 479         tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
 480         tx_amp_fill_result(phydev, tx_amp_cal_val);
 481
 482         return 0;
 483 }
 484
 485 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
 486                               u8 txg_calen_x)
 487 {
 488         int bias = 0;
 489         u16 reg, val;
 490
 491         if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
 492                 bias = -2;
 493
 494         val = clamp_val(bias + tx_r50_cal_val, 0, 63);
 495
 496         switch (txg_calen_x) {
 497         case PAIR_A:
 498                 reg = MTK_PHY_DA_TX_R50_PAIR_A;
 499                 break;
 500         case PAIR_B:
 501                 reg = MTK_PHY_DA_TX_R50_PAIR_B;
 502                 break;
 503         case PAIR_C:
 504                 reg = MTK_PHY_DA_TX_R50_PAIR_C;
 505                 break;
 506         case PAIR_D:
 507                 reg = MTK_PHY_DA_TX_R50_PAIR_D;
 508                 break;
 509         default:
 510                 return -EINVAL;
 511         }
 512
 513         phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
 514
 515         return 0;
 516 }
 517
 518 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
 519                             u8 txg_calen_x)
 520 {
 521         u16 tx_r50_cal_val;
 522
 523         switch (txg_calen_x) {
 524         case PAIR_A:
 525                 tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
 526                 break;
 527         case PAIR_B:
 528                 tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
 529                 break;
 530         case PAIR_C:
 531                 tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
 532                 break;
 533         case PAIR_D:
 534                 tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
 535                 break;
 536         default:
 537                 return -EINVAL;
 538         }
 539         tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
 540
 541         return 0;
 542 }
 543
 544 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
 545 {
 546         u8 lower_idx, upper_idx, txreserve_val;
 547         u8 lower_ret, upper_ret;
 548         int ret;
 549
 550         phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
 551                          MTK_PHY_RG_ANA_CALEN);
 552         phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
 553                            MTK_PHY_RG_CAL_CKINV);
 554         phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
 555                          MTK_PHY_RG_TXVOS_CALEN);
 556
 557         switch (rg_txreserve_x) {
 558         case PAIR_A:
 559                 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 560                                    MTK_PHY_RG_DASN_DAC_IN0_A,
 561                                    MTK_PHY_DASN_DAC_IN0_A_MASK);
 562                 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 563                                    MTK_PHY_RG_DASN_DAC_IN1_A,
 564                                    MTK_PHY_DASN_DAC_IN1_A_MASK);
 565                 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
 566                                  MTK_PHY_RG_ANA_CAL_RG0,
 567                                  MTK_PHY_RG_ZCALEN_A);
 568                 break;
 569         case PAIR_B:
 570                 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 571                                    MTK_PHY_RG_DASN_DAC_IN0_B,
 572                                    MTK_PHY_DASN_DAC_IN0_B_MASK);
 573                 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 574                                    MTK_PHY_RG_DASN_DAC_IN1_B,
 575                                    MTK_PHY_DASN_DAC_IN1_B_MASK);
 576                 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
 577                                  MTK_PHY_RG_ANA_CAL_RG1,
 578                                  MTK_PHY_RG_ZCALEN_B);
 579                 break;
 580         case PAIR_C:
 581                 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 582                                    MTK_PHY_RG_DASN_DAC_IN0_C,
 583                                    MTK_PHY_DASN_DAC_IN0_C_MASK);
 584                 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 585                                    MTK_PHY_RG_DASN_DAC_IN1_C,
 586                                    MTK_PHY_DASN_DAC_IN1_C_MASK);
 587                 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
 588                                  MTK_PHY_RG_ANA_CAL_RG1,
 589                                  MTK_PHY_RG_ZCALEN_C);
 590                 break;
 591         case PAIR_D:
 592                 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 593                                    MTK_PHY_RG_DASN_DAC_IN0_D,
 594                                    MTK_PHY_DASN_DAC_IN0_D_MASK);
 595                 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 596                                    MTK_PHY_RG_DASN_DAC_IN1_D,
 597                                    MTK_PHY_DASN_DAC_IN1_D_MASK);
 598                 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
 599                                  MTK_PHY_RG_ANA_CAL_RG1,
 600                                  MTK_PHY_RG_ZCALEN_D);
 601                 break;
 602         default:
 603                 ret = -EINVAL;
 604                 goto restore;
 605         }
 606
 607         lower_idx = TXRESERVE_MIN;
 608         upper_idx = TXRESERVE_MAX;
 609
 610         phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
 611         while ((upper_idx - lower_idx) > 1) {
 612                 txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
 613                 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
 614                                 MTK_PHY_DA_RX_PSBN_TBT_MASK |
 615                                 MTK_PHY_DA_RX_PSBN_HBT_MASK |
 616                                 MTK_PHY_DA_RX_PSBN_GBE_MASK |
 617                                 MTK_PHY_DA_RX_PSBN_LP_MASK,
 618                                 txreserve_val << 12 | txreserve_val << 8 |
 619                                 txreserve_val << 4 | txreserve_val);
 620                 if (ret == 1) {
 621                         upper_idx = txreserve_val;
 622                         upper_ret = ret;
 623                 } else if (ret == 0) {
 624                         lower_idx = txreserve_val;
 625                         lower_ret = ret;
 626                 } else {
 627                         goto restore;
 628                 }
 629         }
 630
 631         if (lower_idx == TXRESERVE_MIN) {
 632                 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
 633                                       MTK_PHY_RXADC_CTRL_RG9,
 634                                       MTK_PHY_DA_RX_PSBN_TBT_MASK |
 635                                       MTK_PHY_DA_RX_PSBN_HBT_MASK |
 636                                       MTK_PHY_DA_RX_PSBN_GBE_MASK |
 637                                       MTK_PHY_DA_RX_PSBN_LP_MASK,
 638                                       lower_idx << 12 | lower_idx << 8 |
 639                                       lower_idx << 4 | lower_idx);
 640                 ret = lower_ret;
 641         } else if (upper_idx == TXRESERVE_MAX) {
 642                 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
 643                                       MTK_PHY_RXADC_CTRL_RG9,
 644                                       MTK_PHY_DA_RX_PSBN_TBT_MASK |
 645                                       MTK_PHY_DA_RX_PSBN_HBT_MASK |
 646                                       MTK_PHY_DA_RX_PSBN_GBE_MASK |
 647                                       MTK_PHY_DA_RX_PSBN_LP_MASK,
 648                                       upper_idx << 12 | upper_idx << 8 |
 649                                       upper_idx << 4 | upper_idx);
 650                 ret = upper_ret;
 651         }
 652         if (ret < 0)
 653                 goto restore;
 654
 655         /* We calibrate TX-VCM in different logic. Check upper index and then
 656          * lower index. If this calibration is valid, apply lower index's result.
 657          */
 658         ret = upper_ret - lower_ret;
 659         if (ret == 1) {
 660                 ret = 0;
 661                 /* Make sure we use upper_idx in our calibration system */
 662                 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
 663                           MTK_PHY_DA_RX_PSBN_TBT_MASK |
 664                           MTK_PHY_DA_RX_PSBN_HBT_MASK |
 665                           MTK_PHY_DA_RX_PSBN_GBE_MASK |
 666                           MTK_PHY_DA_RX_PSBN_LP_MASK,
 667                           upper_idx << 12 | upper_idx << 8 |
 668                           upper_idx << 4 | upper_idx);
 669                 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
 670         } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
 671                    lower_ret == 1) {
 672                 ret = 0;
 673                 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
 674                           MTK_PHY_DA_RX_PSBN_TBT_MASK |
 675                           MTK_PHY_DA_RX_PSBN_HBT_MASK |
 676                           MTK_PHY_DA_RX_PSBN_GBE_MASK |
 677                           MTK_PHY_DA_RX_PSBN_LP_MASK,
 678                           lower_idx << 12 | lower_idx << 8 |
 679                           lower_idx << 4 | lower_idx);
 680                 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
 681                             lower_idx);
 682         } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
 683                    lower_ret == 0) {
 684                 ret = 0;
 685                 phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
 686                             upper_idx);
 687         } else {
 688                 ret = -EINVAL;
 689         }
 690
 691 restore:
 692         phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
 693                            MTK_PHY_RG_ANA_CALEN);
 694         phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
 695                            MTK_PHY_RG_TXVOS_CALEN);
 696         phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
 697                            MTK_PHY_RG_ZCALEN_A);
 698         phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
 699                            MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
 700                            MTK_PHY_RG_ZCALEN_D);
 701
 702         return ret;
 703 }
 704
 705 static void mt798x_phy_common_finetune(struct phy_device *phydev)
 706 {
 707         phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
 708         /* EnabRandUpdTrig = 1 */
 709         __phy_write(phydev, 0x11, 0x2f00);
 710         __phy_write(phydev, 0x12, 0xe);
 711         __phy_write(phydev, 0x10, 0x8fb0);
 712
 713         /* NormMseLoThresh = 85 */
 714         __phy_write(phydev, 0x11, 0x55a0);
 715         __phy_write(phydev, 0x12, 0x0);
 716         __phy_write(phydev, 0x10, 0x83aa);
 717
 718         /* TrFreeze = 0 */
 719         __phy_write(phydev, 0x11, 0x0);
 720         __phy_write(phydev, 0x12, 0x0);
 721         __phy_write(phydev, 0x10, 0x9686);
 722
 723         /* SSTrKp1000Slv = 5 */
 724         __phy_write(phydev, 0x11, 0xbaef);
 725         __phy_write(phydev, 0x12, 0x2e);
 726         __phy_write(phydev, 0x10, 0x968c);
 727
 728         /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
 729          * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
 730          */
 731         __phy_write(phydev, 0x11, 0xd10a);
 732         __phy_write(phydev, 0x12, 0x34);
 733         __phy_write(phydev, 0x10, 0x8f82);
 734
 735         /* VcoSlicerThreshBitsHigh */
 736         __phy_write(phydev, 0x11, 0x5555);
 737         __phy_write(phydev, 0x12, 0x55);
 738         __phy_write(phydev, 0x10, 0x8ec0);
 739         phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
 740
 741         /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
 742         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
 743                        MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
 744                        BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
 745
 746         /* rg_tr_lpf_cnt_val = 512 */
 747         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
 748
 749         /* IIR2 related */
 750         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
 751         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
 752         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
 753         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
 754         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
 755         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
 756         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
 757         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
 758         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
 759         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
 760
 761         /* FFE peaking */
 762         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
 763                        MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
 764         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
 765                        MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
 766
 767         /* Disable LDO pump */
 768         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
 769         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
 770         /* Adjust LDO output voltage */
 771         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
 772 }
 773
 774 static void mt7981_phy_finetune(struct phy_device *phydev)
 775 {
 776         u16 val[8] = { 0x01ce, 0x01c1,
 777                        0x020f, 0x0202,
 778                        0x03d0, 0x03c0,
 779                        0x0013, 0x0005 };
 780         int i, k;
 781
 782         /* 100M eye finetune:
 783          * Keep middle level of TX MLT3 shapper as default.
 784          * Only change TX MLT3 overshoot level here.
 785          */
 786         for (k = 0, i = 1; i < 12; i++) {
 787                 if (i % 3 == 0)
 788                         continue;
 789                 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
 790         }
 791
 792         phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
 793         /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
 794         __phy_write(phydev, 0x11, 0xc71);
 795         __phy_write(phydev, 0x12, 0xc);
 796         __phy_write(phydev, 0x10, 0x8fae);
 797
 798         /* ResetSyncOffset = 6 */
 799         __phy_write(phydev, 0x11, 0x600);
 800         __phy_write(phydev, 0x12, 0x0);
 801         __phy_write(phydev, 0x10, 0x8fc0);
 802
 803         /* VgaDecRate = 1 */
 804         __phy_write(phydev, 0x11, 0x4c2a);
 805         __phy_write(phydev, 0x12, 0x3e);
 806         __phy_write(phydev, 0x10, 0x8fa4);
 807
 808         /* FfeUpdGainForce = 4 */
 809         __phy_write(phydev, 0x11, 0x240);
 810         __phy_write(phydev, 0x12, 0x0);
 811         __phy_write(phydev, 0x10, 0x9680);
 812
 813         phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
 814 }
 815
 816 static void mt7988_phy_finetune(struct phy_device *phydev)
 817 {
 818         u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
 819                         0x020d, 0x0206, 0x0384, 0x03d0,
 820                         0x03c6, 0x030a, 0x0011, 0x0005 };
 821         int i;
 822
 823         /* Set default MLT3 shaper first */
 824         for (i = 0; i < 12; i++)
 825                 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
 826
 827         /* TCT finetune */
 828         phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
 829
 830         /* Disable TX power saving */
 831         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
 832                        MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
 833
 834         phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
 835
 836         /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
 837         __phy_write(phydev, 0x11, 0x671);
 838         __phy_write(phydev, 0x12, 0xc);
 839         __phy_write(phydev, 0x10, 0x8fae);
 840
 841         /* ResetSyncOffset = 5 */
 842         __phy_write(phydev, 0x11, 0x500);
 843         __phy_write(phydev, 0x12, 0x0);
 844         __phy_write(phydev, 0x10, 0x8fc0);
 845
 846         /* VgaDecRate is 1 at default on mt7988 */
 847
 848         phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
 849
 850         phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
 851         /* TxClkOffset = 2 */
 852         __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
 853                      FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
 854         phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
 855 }
 856
 857 static void mt798x_phy_eee(struct phy_device *phydev)
 858 {
 859         phy_modify_mmd(phydev, MDIO_MMD_VEND1,
 860                        MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
 861                        MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
 862                        MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
 863                        FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
 864                        FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
 865
 866         phy_modify_mmd(phydev, MDIO_MMD_VEND1,
 867                        MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
 868                        MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
 869                        FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
 870                                   0xff));
 871
 872         phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 873                            MTK_PHY_RG_TESTMUX_ADC_CTRL,
 874                            MTK_PHY_RG_TXEN_DIG_MASK);
 875
 876         phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
 877                          MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
 878
 879         phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
 880                            MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
 881
 882         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
 883                        MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
 884                        MTK_PHY_LPI_SLV_SEND_TX_EN,
 885                        FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
 886
 887         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
 888                        MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
 889                        MTK_PHY_LPI_TXPCS_LOC_RCV,
 890                        FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
 891
 892         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
 893                        MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
 894                        FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
 895                        FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
 896
 897         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
 898                        MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
 899                        FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
 900                                   0x33) |
 901                        MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
 902                        MTK_PHY_LPI_VCO_EEE_STG0_EN);
 903
 904         phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
 905                          MTK_PHY_EEE_WAKE_MAS_INT_DC |
 906                          MTK_PHY_EEE_WAKE_SLV_INT_DC);
 907
 908         phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
 909                        MTK_PHY_SMI_DETCNT_MAX_MASK,
 910                        FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
 911                        MTK_PHY_SMI_DET_MAX_EN);
 912
 913         phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
 914                          MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
 915                          MTK_PHY_TREC_UPDATE_ENAB_CLR |
 916                          MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
 917                          MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
 918
 919         phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
 920         /* Regsigdet_sel_1000 = 0 */
 921         __phy_write(phydev, 0x11, 0xb);
 922         __phy_write(phydev, 0x12, 0x0);
 923         __phy_write(phydev, 0x10, 0x9690);
 924
 925         /* REG_EEE_st2TrKf1000 = 3 */
 926         __phy_write(phydev, 0x11, 0x114f);
 927         __phy_write(phydev, 0x12, 0x2);
 928         __phy_write(phydev, 0x10, 0x969a);
 929
 930         /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
 931         __phy_write(phydev, 0x11, 0x3028);
 932         __phy_write(phydev, 0x12, 0x0);
 933         __phy_write(phydev, 0x10, 0x969e);
 934
 935         /* RegEEE_slv_wake_int_timer_tar = 8 */
 936         __phy_write(phydev, 0x11, 0x5010);
 937         __phy_write(phydev, 0x12, 0x0);
 938         __phy_write(phydev, 0x10, 0x96a0);
 939
 940         /* RegEEE_trfreeze_timer2 = 586 */
 941         __phy_write(phydev, 0x11, 0x24a);
 942         __phy_write(phydev, 0x12, 0x0);
 943         __phy_write(phydev, 0x10, 0x96a8);
 944
 945         /* RegEEE100Stg1_tar = 16 */
 946         __phy_write(phydev, 0x11, 0x3210);
 947         __phy_write(phydev, 0x12, 0x0);
 948         __phy_write(phydev, 0x10, 0x96b8);
 949
 950         /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
 951         __phy_write(phydev, 0x11, 0x1463);
 952         __phy_write(phydev, 0x12, 0x0);
 953         __phy_write(phydev, 0x10, 0x96ca);
 954
 955         /* DfeTailEnableVgaThresh1000 = 27 */
 956         __phy_write(phydev, 0x11, 0x36);
 957         __phy_write(phydev, 0x12, 0x0);
 958         __phy_write(phydev, 0x10, 0x8f80);
 959         phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
 960
 961         phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
 962         __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
 963                      FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
 964
 965         __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
 966                      FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
 967         phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
 968
 969         phy_modify_mmd(phydev, MDIO_MMD_VEND1,
 970                        MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
 971                        MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
 972                        FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
 973 }
 974
 975 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
 976                   u8 start_pair, u8 end_pair)
 977 {
 978         u8 pair_n;
 979         int ret;
 980
 981         for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
 982                 /* TX_OFFSET & TX_AMP have no SW calibration. */
 983                 switch (cal_item) {
 984                 case TX_VCM:
 985                         ret = tx_vcm_cal_sw(phydev, pair_n);
 986                         break;
 987                 default:
 988                         return -EINVAL;
 989                 }
 990                 if (ret)
 991                         return ret;
 992         }
 993         return 0;
 994 }
 995
 996 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
 997                      u8 start_pair, u8 end_pair, u32 *buf)
 998 {
 999         u8 pair_n;
1000         int ret;
1001
1002         for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1003                 /* TX_VCM has no efuse calibration. */
1004                 switch (cal_item) {
1005                 case REXT:
1006                         ret = rext_cal_efuse(phydev, buf);
1007                         break;
1008                 case TX_OFFSET:
1009                         ret = tx_offset_cal_efuse(phydev, buf);
1010                         break;
1011                 case TX_AMP:
1012                         ret = tx_amp_cal_efuse(phydev, buf);
1013                         break;
1014                 case TX_R50:
1015                         ret = tx_r50_cal_efuse(phydev, buf, pair_n);
1016                         break;
1017                 default:
1018                         return -EINVAL;
1019                 }
1020                 if (ret)
1021                         return ret;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
1028                      enum CAL_MODE cal_mode, u8 start_pair,
1029                      u8 end_pair, u32 *buf)
1030 {
1031         int ret;
1032
1033         switch (cal_mode) {
1034         case EFUSE_M:
1035                 ret = cal_efuse(phydev, cal_item, start_pair,
1036                                 end_pair, buf);
1037                 break;
1038         case SW_M:
1039                 ret = cal_sw(phydev, cal_item, start_pair, end_pair);
1040                 break;
1041         default:
1042                 return -EINVAL;
1043         }
1044
1045         if (ret) {
1046                 phydev_err(phydev, "cal %d failed\n", cal_item);
1047                 return -EIO;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static int mt798x_phy_calibration(struct phy_device *phydev)
1054 {
1055         int ret = 0;
1056         u32 *buf;
1057         size_t len;
1058         struct nvmem_cell *cell;
1059
1060         cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
1061         if (IS_ERR(cell)) {
1062                 if (PTR_ERR(cell) == -EPROBE_DEFER)
1063                         return PTR_ERR(cell);
1064                 return 0;
1065         }
1066
1067         buf = (u32 *)nvmem_cell_read(cell, &len);
1068         if (IS_ERR(buf))
1069                 return PTR_ERR(buf);
1070         nvmem_cell_put(cell);
1071
1072         if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
1073                 phydev_err(phydev, "invalid efuse data\n");
1074                 ret = -EINVAL;
1075                 goto out;
1076         }
1077
1078         ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1079         if (ret)
1080                 goto out;
1081         ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1082         if (ret)
1083                 goto out;
1084         ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1085         if (ret)
1086                 goto out;
1087         ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
1088         if (ret)
1089                 goto out;
1090         ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
1091         if (ret)
1092                 goto out;
1093
1094 out:
1095         kfree(buf);
1096         return ret;
1097 }
1098
1099 static int mt798x_phy_config_init(struct phy_device *phydev)
1100 {
1101         switch (phydev->drv->phy_id) {
1102         case MTK_GPHY_ID_MT7981:
1103                 mt7981_phy_finetune(phydev);
1104                 break;
1105         case MTK_GPHY_ID_MT7988:
1106                 mt7988_phy_finetune(phydev);
1107                 break;
1108         }
1109
1110         mt798x_phy_common_finetune(phydev);
1111         mt798x_phy_eee(phydev);
1112
1113         return mt798x_phy_calibration(phydev);
1114 }
1115
1116 static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
1117                                     bool on)
1118 {
1119         unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
1120         struct mtk_socphy_priv *priv = phydev->priv;
1121         bool changed;
1122
1123         if (on)
1124                 changed = !test_and_set_bit(bit_on, &priv->led_state);
1125         else
1126                 changed = !!test_and_clear_bit(bit_on, &priv->led_state);
1127
1128         changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
1129                                         (index ? 16 : 0), &priv->led_state);
1130         if (changed)
1131                 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1132                                       MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
1133                                       MTK_PHY_LED_ON_MASK,
1134                                       on ? MTK_PHY_LED_ON_FORCE_ON : 0);
1135         else
1136                 return 0;
1137 }
1138
1139 static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
1140                                        bool blinking)
1141 {
1142         unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
1143         struct mtk_socphy_priv *priv = phydev->priv;
1144         bool changed;
1145
1146         if (blinking)
1147                 changed = !test_and_set_bit(bit_blink, &priv->led_state);
1148         else
1149                 changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
1150
1151         changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
1152                               (index ? 16 : 0), &priv->led_state);
1153         if (changed)
1154                 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
1155                                      MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL,
1156                                      blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
1157         else
1158                 return 0;
1159 }
1160
1161 static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
1162                                     unsigned long *delay_on,
1163                                     unsigned long *delay_off)
1164 {
1165         bool blinking = false;
1166         int err = 0;
1167
1168         if (index > 1)
1169                 return -EINVAL;
1170
1171         if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
1172                 blinking = true;
1173                 *delay_on = 50;
1174                 *delay_off = 50;
1175         }
1176
1177         err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
1178         if (err)
1179                 return err;
1180
1181         return mt798x_phy_hw_led_on_set(phydev, index, false);
1182 }
1183
1184 static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
1185                                          u8 index, enum led_brightness value)
1186 {
1187         int err;
1188
1189         err = mt798x_phy_hw_led_blink_set(phydev, index, false);
1190         if (err)
1191                 return err;
1192
1193         return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
1194 }
1195
1196 static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
1197                                                  BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
1198                                                  BIT(TRIGGER_NETDEV_LINK)        |
1199                                                  BIT(TRIGGER_NETDEV_LINK_10)     |
1200                                                  BIT(TRIGGER_NETDEV_LINK_100)    |
1201                                                  BIT(TRIGGER_NETDEV_LINK_1000)   |
1202                                                  BIT(TRIGGER_NETDEV_RX)          |
1203                                                  BIT(TRIGGER_NETDEV_TX));
1204
1205 static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
1206                                           unsigned long rules)
1207 {
1208         if (index > 1)
1209                 return -EINVAL;
1210
1211         /* All combinations of the supported triggers are allowed */
1212         if (rules & ~supported_triggers)
1213                 return -EOPNOTSUPP;
1214
1215         return 0;
1216 };
1217
1218 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
1219                                          unsigned long *rules)
1220 {
1221         unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
1222         unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
1223         unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
1224         struct mtk_socphy_priv *priv = phydev->priv;
1225         int on, blink;
1226
1227         if (index > 1)
1228                 return -EINVAL;
1229
1230         on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1231                           index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
1232
1233         if (on < 0)
1234                 return -EIO;
1235
1236         blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1237                              index ? MTK_PHY_LED1_BLINK_CTRL :
1238                                      MTK_PHY_LED0_BLINK_CTRL);
1239         if (blink < 0)
1240                 return -EIO;
1241
1242         if ((on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 |
1243                    MTK_PHY_LED_ON_LINK10)) ||
1244             (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX |
1245                       MTK_PHY_LED_BLINK_10RX | MTK_PHY_LED_BLINK_1000TX |
1246                       MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX)))
1247                 set_bit(bit_netdev, &priv->led_state);
1248         else
1249                 clear_bit(bit_netdev, &priv->led_state);
1250
1251         if (on & MTK_PHY_LED_ON_FORCE_ON)
1252                 set_bit(bit_on, &priv->led_state);
1253         else
1254                 clear_bit(bit_on, &priv->led_state);
1255
1256         if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
1257                 set_bit(bit_blink, &priv->led_state);
1258         else
1259                 clear_bit(bit_blink, &priv->led_state);
1260
1261         if (!rules)
1262                 return 0;
1263
1264         if (on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK10))
1265                 *rules |= BIT(TRIGGER_NETDEV_LINK);
1266
1267         if (on & MTK_PHY_LED_ON_LINK10)
1268                 *rules |= BIT(TRIGGER_NETDEV_LINK_10);
1269
1270         if (on & MTK_PHY_LED_ON_LINK100)
1271                 *rules |= BIT(TRIGGER_NETDEV_LINK_100);
1272
1273         if (on & MTK_PHY_LED_ON_LINK1000)
1274                 *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
1275
1276         if (on & MTK_PHY_LED_ON_FDX)
1277                 *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1278
1279         if (on & MTK_PHY_LED_ON_HDX)
1280                 *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
1281
1282         if (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | MTK_PHY_LED_BLINK_10RX))
1283                 *rules |= BIT(TRIGGER_NETDEV_RX);
1284
1285         if (blink & (MTK_PHY_LED_BLINK_1000TX | MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX))
1286                 *rules |= BIT(TRIGGER_NETDEV_TX);
1287
1288         return 0;
1289 };
1290
1291 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
1292                                          unsigned long rules)
1293 {
1294         unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
1295         struct mtk_socphy_priv *priv = phydev->priv;
1296         u16 on = 0, blink = 0;
1297         int ret;
1298
1299         if (index > 1)
1300                 return -EINVAL;
1301
1302         if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
1303                 on |= MTK_PHY_LED_ON_FDX;
1304
1305         if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
1306                 on |= MTK_PHY_LED_ON_HDX;
1307
1308         if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
1309                 on |= MTK_PHY_LED_ON_LINK10;
1310
1311         if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
1312                 on |= MTK_PHY_LED_ON_LINK100;
1313
1314         if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
1315                 on |= MTK_PHY_LED_ON_LINK1000;
1316
1317         if (rules & BIT(TRIGGER_NETDEV_RX)) {
1318                 blink |= MTK_PHY_LED_BLINK_10RX  |
1319                          MTK_PHY_LED_BLINK_100RX |
1320                          MTK_PHY_LED_BLINK_1000RX;
1321         }
1322
1323         if (rules & BIT(TRIGGER_NETDEV_TX)) {
1324                 blink |= MTK_PHY_LED_BLINK_10TX  |
1325                          MTK_PHY_LED_BLINK_100TX |
1326                          MTK_PHY_LED_BLINK_1000TX;
1327         }
1328
1329         if (blink || on)
1330                 set_bit(bit_netdev, &priv->led_state);
1331         else
1332                 clear_bit(bit_netdev, &priv->led_state);
1333
1334         ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1335                                 MTK_PHY_LED1_ON_CTRL :
1336                                 MTK_PHY_LED0_ON_CTRL,
1337                              MTK_PHY_LED_ON_FDX     |
1338                              MTK_PHY_LED_ON_HDX     |
1339                              MTK_PHY_LED_ON_LINK10  |
1340                              MTK_PHY_LED_ON_LINK100 |
1341                              MTK_PHY_LED_ON_LINK1000,
1342                              on);
1343
1344         if (ret)
1345                 return ret;
1346
1347         return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
1348                                 MTK_PHY_LED1_BLINK_CTRL :
1349                                 MTK_PHY_LED0_BLINK_CTRL, blink);
1350 };
1351
1352 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
1353 {
1354         struct mtk_socphy_shared *priv = phydev->shared->priv;
1355         u32 polarities;
1356
1357         if (led_num == 0)
1358                 polarities = ~(priv->boottrap);
1359         else
1360                 polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
1361
1362         if (polarities & BIT(phydev->mdio.addr))
1363                 return true;
1364
1365         return false;
1366 }
1367
1368 static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
1369 {
1370         struct pinctrl *pinctrl;
1371         int index;
1372
1373         /* Setup LED polarity according to bootstrap use of LED pins */
1374         for (index = 0; index < 2; ++index)
1375                 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1376                                 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
1377                                MTK_PHY_LED_ON_POLARITY,
1378                                mt7988_phy_led_get_polarity(phydev, index) ?
1379                                 MTK_PHY_LED_ON_POLARITY : 0);
1380
1381         /* Only now setup pinctrl to avoid bogus blinking */
1382         pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
1383         if (IS_ERR(pinctrl))
1384                 dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
1385
1386         return 0;
1387 }
1388
1389 static int mt7988_phy_probe_shared(struct phy_device *phydev)
1390 {
1391         struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
1392         struct mtk_socphy_shared *shared = phydev->shared->priv;
1393         struct regmap *regmap;
1394         u32 reg;
1395         int ret;
1396
1397         /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
1398          * LED_C and LED_D respectively. At the same time those pins are used to
1399          * bootstrap configuration of the reference clock source (LED_A),
1400          * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
1401          * In practise this is done using a LED and a resistor pulling the pin
1402          * either to GND or to VIO.
1403          * The detected value at boot time is accessible at run-time using the
1404          * TPBANK0 register located in the gpio base of the pinctrl, in order
1405          * to read it here it needs to be referenced by a phandle called
1406          * 'mediatek,pio' in the MDIO bus hosting the PHY.
1407          * The 4 bits in TPBANK0 are kept as package shared data and are used to
1408          * set LED polarity for each of the LED0.
1409          */
1410         regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
1411         if (IS_ERR(regmap))
1412                 return PTR_ERR(regmap);
1413
1414         ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
1415         if (ret)
1416                 return ret;
1417
1418         shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
1419
1420         return 0;
1421 }
1422
1423 static void mt798x_phy_leds_state_init(struct phy_device *phydev)
1424 {
1425         int i;
1426
1427         for (i = 0; i < 2; ++i)
1428                 mt798x_phy_led_hw_control_get(phydev, i, NULL);
1429 }
1430
1431 static int mt7988_phy_probe(struct phy_device *phydev)
1432 {
1433         struct mtk_socphy_shared *shared;
1434         struct mtk_socphy_priv *priv;
1435         int err;
1436
1437         if (phydev->mdio.addr > 3)
1438                 return -EINVAL;
1439
1440         err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
1441                                     sizeof(struct mtk_socphy_shared));
1442         if (err)
1443                 return err;
1444
1445         if (phy_package_probe_once(phydev)) {
1446                 err = mt7988_phy_probe_shared(phydev);
1447                 if (err)
1448                         return err;
1449         }
1450
1451         shared = phydev->shared->priv;
1452         priv = &shared->priv[phydev->mdio.addr];
1453
1454         phydev->priv = priv;
1455
1456         mt798x_phy_leds_state_init(phydev);
1457
1458         err = mt7988_phy_fix_leds_polarities(phydev);
1459         if (err)
1460                 return err;
1461
1462         return mt798x_phy_calibration(phydev);
1463 }
1464
1465 static int mt7981_phy_probe(struct phy_device *phydev)
1466 {
1467         struct mtk_socphy_priv *priv;
1468
1469         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
1470                             GFP_KERNEL);
1471         if (!priv)
1472                 return -ENOMEM;
1473
1474         phydev->priv = priv;
1475
1476         mt798x_phy_leds_state_init(phydev);
1477
1478         return mt798x_phy_calibration(phydev);
1479 }
1480
1481 static struct phy_driver mtk_socphy_driver[] = {
1482         {
1483                 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
1484                 .name           = "MediaTek MT7981 PHY",
1485                 .config_init    = mt798x_phy_config_init,
1486                 .config_intr    = genphy_no_config_intr,
1487                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1488                 .probe          = mt7981_phy_probe,
1489                 .suspend        = genphy_suspend,
1490                 .resume         = genphy_resume,
1491                 .read_page      = mtk_socphy_read_page,
1492                 .write_page     = mtk_socphy_write_page,
1493                 .led_blink_set  = mt798x_phy_led_blink_set,
1494                 .led_brightness_set = mt798x_phy_led_brightness_set,
1495                 .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
1496                 .led_hw_control_set = mt798x_phy_led_hw_control_set,
1497                 .led_hw_control_get = mt798x_phy_led_hw_control_get,
1498         },
1499         {
1500                 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
1501                 .name           = "MediaTek MT7988 PHY",
1502                 .config_init    = mt798x_phy_config_init,
1503                 .config_intr    = genphy_no_config_intr,
1504                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1505                 .probe          = mt7988_phy_probe,
1506                 .suspend        = genphy_suspend,
1507                 .resume         = genphy_resume,
1508                 .read_page      = mtk_socphy_read_page,
1509                 .write_page     = mtk_socphy_write_page,
1510                 .led_blink_set  = mt798x_phy_led_blink_set,
1511                 .led_brightness_set = mt798x_phy_led_brightness_set,
1512                 .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
1513                 .led_hw_control_set = mt798x_phy_led_hw_control_set,
1514                 .led_hw_control_get = mt798x_phy_led_hw_control_get,
1515         },
1516 };
1517
1518 module_phy_driver(mtk_socphy_driver);
1519
1520 static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
1521         { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
1522         { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
1523         { }
1524 };
1525
1526 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
1527 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
1528 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
1529 MODULE_LICENSE("GPL");
1530
1531 MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);