1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/marvell.c
5 * Driver for Marvell PHYs
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
11 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/ctype.h>
16 #include <linux/errno.h>
17 #include <linux/unistd.h>
18 #include <linux/hwmon.h>
19 #include <linux/interrupt.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/spinlock.h>
27 #include <linux/module.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/ethtool_netlink.h>
31 #include <linux/phy.h>
32 #include <linux/marvell_phy.h>
33 #include <linux/bitfield.h>
35 #include <linux/sfp.h>
39 #include <linux/uaccess.h>
41 #define MII_MARVELL_PHY_PAGE 22
42 #define MII_MARVELL_COPPER_PAGE 0x00
43 #define MII_MARVELL_FIBER_PAGE 0x01
44 #define MII_MARVELL_MSCR_PAGE 0x02
45 #define MII_MARVELL_LED_PAGE 0x03
46 #define MII_MARVELL_VCT5_PAGE 0x05
47 #define MII_MARVELL_MISC_TEST_PAGE 0x06
48 #define MII_MARVELL_VCT7_PAGE 0x07
49 #define MII_MARVELL_WOL_PAGE 0x11
50 #define MII_MARVELL_MODE_PAGE 0x12
52 #define MII_M1011_IEVENT 0x13
53 #define MII_M1011_IEVENT_CLEAR 0x0000
55 #define MII_M1011_IMASK 0x12
56 #define MII_M1011_IMASK_INIT 0x6400
57 #define MII_M1011_IMASK_CLEAR 0x0000
59 #define MII_M1011_PHY_SCR 0x10
60 #define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
61 #define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
62 #define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
63 #define MII_M1011_PHY_SCR_MDI (0x0 << 5)
64 #define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
65 #define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
67 #define MII_M1011_PHY_SSR 0x11
68 #define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
70 #define MII_M1111_PHY_LED_CONTROL 0x18
71 #define MII_M1111_PHY_LED_DIRECT 0x4100
72 #define MII_M1111_PHY_LED_COMBINE 0x411c
73 #define MII_M1111_PHY_EXT_CR 0x14
74 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
75 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
76 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
77 #define MII_M1111_RGMII_RX_DELAY BIT(7)
78 #define MII_M1111_RGMII_TX_DELAY BIT(1)
79 #define MII_M1111_PHY_EXT_SR 0x1b
81 #define MII_M1111_HWCFG_MODE_MASK 0xf
82 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
83 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
84 #define MII_M1111_HWCFG_MODE_RTBI 0x7
85 #define MII_M1111_HWCFG_MODE_COPPER_1000X_AN 0x8
86 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
87 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
88 #define MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN 0xc
89 #define MII_M1111_HWCFG_SERIAL_AN_BYPASS BIT(12)
90 #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
91 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
93 #define MII_88E1121_PHY_MSCR_REG 21
94 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
95 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
96 #define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
98 #define MII_88E1121_MISC_TEST 0x1a
99 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
100 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
101 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
102 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
103 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
104 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
106 #define MII_88E1510_TEMP_SENSOR 0x1b
107 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
109 #define MII_88E1540_COPPER_CTRL3 0x1a
110 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
111 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
112 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
113 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
114 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
115 #define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
117 #define MII_88E6390_MISC_TEST 0x1b
118 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S (0x0 << 14)
119 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE (0x1 << 14)
120 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_ONESHOT (0x2 << 14)
121 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE (0x3 << 14)
122 #define MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK (0x3 << 14)
123 #define MII_88E6393_MISC_TEST_SAMPLES_2048 (0x0 << 11)
124 #define MII_88E6393_MISC_TEST_SAMPLES_4096 (0x1 << 11)
125 #define MII_88E6393_MISC_TEST_SAMPLES_8192 (0x2 << 11)
126 #define MII_88E6393_MISC_TEST_SAMPLES_16384 (0x3 << 11)
127 #define MII_88E6393_MISC_TEST_SAMPLES_MASK (0x3 << 11)
128 #define MII_88E6393_MISC_TEST_RATE_2_3MS (0x5 << 8)
129 #define MII_88E6393_MISC_TEST_RATE_6_4MS (0x6 << 8)
130 #define MII_88E6393_MISC_TEST_RATE_11_9MS (0x7 << 8)
131 #define MII_88E6393_MISC_TEST_RATE_MASK (0x7 << 8)
133 #define MII_88E6390_TEMP_SENSOR 0x1c
134 #define MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK 0xff00
135 #define MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT 8
136 #define MII_88E6390_TEMP_SENSOR_MASK 0xff
137 #define MII_88E6390_TEMP_SENSOR_SAMPLES 10
139 #define MII_88E1318S_PHY_MSCR1_REG 16
140 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
142 /* Copper Specific Interrupt Enable Register */
143 #define MII_88E1318S_PHY_CSIER 0x12
144 /* WOL Event Interrupt Enable */
145 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
147 /* LED Timer Control Register */
148 #define MII_88E1318S_PHY_LED_TCR 0x12
149 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
150 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
151 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
153 /* Magic Packet MAC address registers */
154 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
155 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
156 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
158 #define MII_88E1318S_PHY_WOL_CTRL 0x10
159 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
160 #define MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE BIT(13)
161 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
163 #define MII_PHY_LED_CTRL 16
164 #define MII_88E1121_PHY_LED_DEF 0x0030
165 #define MII_88E1510_PHY_LED_DEF 0x1177
166 #define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
168 #define MII_M1011_PHY_STATUS 0x11
169 #define MII_M1011_PHY_STATUS_1000 0x8000
170 #define MII_M1011_PHY_STATUS_100 0x4000
171 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
172 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
173 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
174 #define MII_M1011_PHY_STATUS_LINK 0x0400
176 #define MII_88E3016_PHY_SPEC_CTRL 0x10
177 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
178 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
180 #define MII_88E1510_GEN_CTRL_REG_1 0x14
181 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
182 #define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII 0x0 /* RGMII to copper */
183 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
184 /* RGMII to 1000BASE-X */
185 #define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X 0x2
186 /* RGMII to 100BASE-FX */
187 #define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX 0x3
189 #define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII 0x4
190 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
192 #define MII_88E1510_MSCR_2 0x15
194 #define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
195 #define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
196 #define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
197 #define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
198 #define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
199 #define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
200 #define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
202 #define MII_VCT5_CTRL 0x17
203 #define MII_VCT5_CTRL_ENABLE BIT(15)
204 #define MII_VCT5_CTRL_COMPLETE BIT(14)
205 #define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
206 #define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
207 #define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
208 #define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
209 #define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
210 #define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
211 #define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
212 #define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
213 #define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
214 #define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
215 #define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
216 #define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
217 #define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
218 #define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
219 #define MII_VCT5_CTRL_SAMPLES_SHIFT 8
220 #define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
221 #define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
222 #define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
223 #define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
224 #define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
226 #define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
227 #define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
228 #define MII_VCT5_TX_PULSE_CTRL 0x1c
229 #define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
230 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
231 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
232 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
233 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
234 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
235 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
236 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
237 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
238 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
239 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
240 #define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
241 #define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
243 /* For TDR measurements less than 11 meters, a short pulse should be
246 #define TDR_SHORT_CABLE_LENGTH 11
248 #define MII_VCT7_PAIR_0_DISTANCE 0x10
249 #define MII_VCT7_PAIR_1_DISTANCE 0x11
250 #define MII_VCT7_PAIR_2_DISTANCE 0x12
251 #define MII_VCT7_PAIR_3_DISTANCE 0x13
253 #define MII_VCT7_RESULTS 0x14
254 #define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
255 #define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
256 #define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
257 #define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
258 #define MII_VCT7_RESULTS_PAIR3_SHIFT 12
259 #define MII_VCT7_RESULTS_PAIR2_SHIFT 8
260 #define MII_VCT7_RESULTS_PAIR1_SHIFT 4
261 #define MII_VCT7_RESULTS_PAIR0_SHIFT 0
262 #define MII_VCT7_RESULTS_INVALID 0
263 #define MII_VCT7_RESULTS_OK 1
264 #define MII_VCT7_RESULTS_OPEN 2
265 #define MII_VCT7_RESULTS_SAME_SHORT 3
266 #define MII_VCT7_RESULTS_CROSS_SHORT 4
267 #define MII_VCT7_RESULTS_BUSY 9
269 #define MII_VCT7_CTRL 0x15
270 #define MII_VCT7_CTRL_RUN_NOW BIT(15)
271 #define MII_VCT7_CTRL_RUN_ANEG BIT(14)
272 #define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
273 #define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
274 #define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
275 #define MII_VCT7_CTRL_METERS BIT(10)
276 #define MII_VCT7_CTRL_CENTIMETERS 0
278 #define LPA_PAUSE_FIBER 0x180
279 #define LPA_PAUSE_ASYM_FIBER 0x100
281 #define NB_FIBER_STATS 1
283 MODULE_DESCRIPTION("Marvell PHY driver");
284 MODULE_AUTHOR("Andy Fleming");
285 MODULE_LICENSE("GPL");
287 struct marvell_hw_stat {
294 static struct marvell_hw_stat marvell_hw_stats[] = {
295 { "phy_receive_errors_copper", 0, 21, 16},
296 { "phy_idle_errors", 0, 10, 8 },
297 { "phy_receive_errors_fiber", 1, 21, 16},
300 struct marvell_priv {
301 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
303 struct device *hwmon_dev;
311 static int marvell_read_page(struct phy_device *phydev)
313 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
316 static int marvell_write_page(struct phy_device *phydev, int page)
318 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
321 static int marvell_set_page(struct phy_device *phydev, int page)
323 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
326 static int marvell_ack_interrupt(struct phy_device *phydev)
330 /* Clear the interrupts by reading the reg */
331 err = phy_read(phydev, MII_M1011_IEVENT);
339 static int marvell_config_intr(struct phy_device *phydev)
343 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
344 err = marvell_ack_interrupt(phydev);
348 err = phy_write(phydev, MII_M1011_IMASK,
349 MII_M1011_IMASK_INIT);
351 err = phy_write(phydev, MII_M1011_IMASK,
352 MII_M1011_IMASK_CLEAR);
356 err = marvell_ack_interrupt(phydev);
362 static irqreturn_t marvell_handle_interrupt(struct phy_device *phydev)
366 irq_status = phy_read(phydev, MII_M1011_IEVENT);
367 if (irq_status < 0) {
372 if (!(irq_status & MII_M1011_IMASK_INIT))
375 phy_trigger_machine(phydev);
380 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
386 val = MII_M1011_PHY_SCR_MDI;
389 val = MII_M1011_PHY_SCR_MDI_X;
391 case ETH_TP_MDI_AUTO:
392 case ETH_TP_MDI_INVALID:
394 val = MII_M1011_PHY_SCR_AUTO_CROSS;
398 return phy_modify_changed(phydev, MII_M1011_PHY_SCR,
399 MII_M1011_PHY_SCR_AUTO_CROSS, val);
402 static int marvell_config_aneg(struct phy_device *phydev)
407 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
413 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
414 MII_M1111_PHY_LED_DIRECT);
418 err = genphy_config_aneg(phydev);
422 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
423 /* A write to speed/duplex bits (that is performed by
424 * genphy_config_aneg() call above) must be followed by
425 * a software reset. Otherwise, the write has no effect.
427 err = genphy_soft_reset(phydev);
435 static int m88e1101_config_aneg(struct phy_device *phydev)
439 /* This Marvell PHY has an errata which requires
440 * that certain registers get written in order
441 * to restart autonegotiation
443 err = genphy_soft_reset(phydev);
447 err = phy_write(phydev, 0x1d, 0x1f);
451 err = phy_write(phydev, 0x1e, 0x200c);
455 err = phy_write(phydev, 0x1d, 0x5);
459 err = phy_write(phydev, 0x1e, 0);
463 err = phy_write(phydev, 0x1e, 0x100);
467 return marvell_config_aneg(phydev);
470 #if IS_ENABLED(CONFIG_OF_MDIO)
471 /* Set and/or override some configuration registers based on the
472 * marvell,reg-init property stored in the of_node for the phydev.
474 * marvell,reg-init = <reg-page reg mask value>,...;
476 * There may be one or more sets of <reg-page reg mask value>:
478 * reg-page: which register bank to use.
480 * mask: if non-zero, ANDed with existing register value.
481 * value: ORed with the masked value and written to the regiser.
484 static int marvell_of_reg_init(struct phy_device *phydev)
487 int len, i, saved_page, current_page, ret = 0;
489 if (!phydev->mdio.dev.of_node)
492 paddr = of_get_property(phydev->mdio.dev.of_node,
493 "marvell,reg-init", &len);
494 if (!paddr || len < (4 * sizeof(*paddr)))
497 saved_page = phy_save_page(phydev);
500 current_page = saved_page;
502 len /= sizeof(*paddr);
503 for (i = 0; i < len - 3; i += 4) {
504 u16 page = be32_to_cpup(paddr + i);
505 u16 reg = be32_to_cpup(paddr + i + 1);
506 u16 mask = be32_to_cpup(paddr + i + 2);
507 u16 val_bits = be32_to_cpup(paddr + i + 3);
510 if (page != current_page) {
512 ret = marvell_write_page(phydev, page);
519 val = __phy_read(phydev, reg);
528 ret = __phy_write(phydev, reg, val);
533 return phy_restore_page(phydev, saved_page, ret);
536 static int marvell_of_reg_init(struct phy_device *phydev)
540 #endif /* CONFIG_OF_MDIO */
542 static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
546 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
547 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
548 MII_88E1121_PHY_MSCR_TX_DELAY;
549 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
550 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
551 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
552 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
556 return phy_modify_paged_changed(phydev, MII_MARVELL_MSCR_PAGE,
557 MII_88E1121_PHY_MSCR_REG,
558 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
561 static int m88e1121_config_aneg(struct phy_device *phydev)
566 if (phy_interface_is_rgmii(phydev)) {
567 err = m88e1121_config_aneg_rgmii_delays(phydev);
574 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
580 err = genphy_config_aneg(phydev);
584 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
585 /* A software reset is used to ensure a "commit" of the
588 err = genphy_soft_reset(phydev);
596 static int m88e1318_config_aneg(struct phy_device *phydev)
600 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
601 MII_88E1318S_PHY_MSCR1_REG,
602 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
606 return m88e1121_config_aneg(phydev);
610 * linkmode_adv_to_fiber_adv_t
611 * @advertise: the linkmode advertisement settings
613 * A small helper function that translates linkmode advertisement
614 * settings to phy autonegotiation advertisements for the MII_ADV
615 * register for fiber link.
617 static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
621 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
622 result |= ADVERTISE_1000XHALF;
623 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
624 result |= ADVERTISE_1000XFULL;
626 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
627 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
628 result |= ADVERTISE_1000XPSE_ASYM;
629 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
630 result |= ADVERTISE_1000XPAUSE;
636 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
637 * @phydev: target phy_device struct
639 * Description: If auto-negotiation is enabled, we configure the
640 * advertising, and then restart auto-negotiation. If it is not
641 * enabled, then we write the BMCR. Adapted for fiber link in
642 * some Marvell's devices.
644 static int marvell_config_aneg_fiber(struct phy_device *phydev)
650 if (phydev->autoneg != AUTONEG_ENABLE)
651 return genphy_setup_forced(phydev);
653 /* Only allow advertising what this PHY supports */
654 linkmode_and(phydev->advertising, phydev->advertising,
657 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
659 /* Setup fiber advertisement */
660 err = phy_modify_changed(phydev, MII_ADVERTISE,
661 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
662 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
669 return genphy_check_and_restart_aneg(phydev, changed);
672 static int m88e1111_config_aneg(struct phy_device *phydev)
674 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
680 /* If not using SGMII or copper 1000BaseX modes, use normal process.
681 * Steps below are only required for these modes.
683 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
684 (extsr & MII_M1111_HWCFG_MODE_MASK) !=
685 MII_M1111_HWCFG_MODE_COPPER_1000X_AN)
686 return marvell_config_aneg(phydev);
688 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
692 /* Configure the copper link first */
693 err = marvell_config_aneg(phydev);
697 /* Then the fiber link */
698 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
702 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
703 /* Do not touch the fiber advertisement if we're in copper->sgmii mode.
704 * Just ensure that SGMII-side autonegotiation is enabled.
705 * If we switched from some other mode to SGMII it may not be.
707 err = genphy_check_and_restart_aneg(phydev, false);
709 err = marvell_config_aneg_fiber(phydev);
713 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
716 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
720 static int m88e1510_config_aneg(struct phy_device *phydev)
724 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
728 /* Configure the copper link first */
729 err = m88e1318_config_aneg(phydev);
733 /* Do not touch the fiber page if we're in copper->sgmii mode */
734 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
737 /* Then the fiber link */
738 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
742 err = marvell_config_aneg_fiber(phydev);
746 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
749 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
753 static void marvell_config_led(struct phy_device *phydev)
758 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
759 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
760 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
761 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
762 def_config = MII_88E1121_PHY_LED_DEF;
764 /* Default PHY LED config:
765 * LED[0] .. 1000Mbps Link
766 * LED[1] .. 100Mbps Link
767 * LED[2] .. Blink, Activity
769 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
770 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
771 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
773 def_config = MII_88E1510_PHY_LED_DEF;
779 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
782 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
785 static int marvell_config_init(struct phy_device *phydev)
787 /* Set default LED */
788 marvell_config_led(phydev);
790 /* Set registers from marvell,reg-init DT property */
791 return marvell_of_reg_init(phydev);
794 static int m88e3016_config_init(struct phy_device *phydev)
798 /* Enable Scrambler and Auto-Crossover */
799 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
800 MII_88E3016_DISABLE_SCRAMBLER,
801 MII_88E3016_AUTO_MDIX_CROSSOVER);
805 return marvell_config_init(phydev);
808 static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
810 int fibre_copper_auto)
812 if (fibre_copper_auto)
813 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
815 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
816 MII_M1111_HWCFG_MODE_MASK |
817 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
818 MII_M1111_HWCFG_FIBER_COPPER_RES,
822 static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
826 switch (phydev->interface) {
827 case PHY_INTERFACE_MODE_RGMII_ID:
828 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
830 case PHY_INTERFACE_MODE_RGMII_RXID:
831 delay = MII_M1111_RGMII_RX_DELAY;
833 case PHY_INTERFACE_MODE_RGMII_TXID:
834 delay = MII_M1111_RGMII_TX_DELAY;
841 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
842 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
846 static int m88e1111_config_init_rgmii(struct phy_device *phydev)
851 err = m88e1111_config_init_rgmii_delays(phydev);
855 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
859 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
861 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
862 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
864 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
866 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
869 static int m88e1111_config_init_sgmii(struct phy_device *phydev)
873 err = m88e1111_config_init_hwcfg_mode(
875 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
876 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
880 /* make sure copper is selected */
881 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
884 static int m88e1111_config_init_rtbi(struct phy_device *phydev)
888 err = m88e1111_config_init_rgmii_delays(phydev);
892 err = m88e1111_config_init_hwcfg_mode(
894 MII_M1111_HWCFG_MODE_RTBI,
895 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
900 err = genphy_soft_reset(phydev);
904 return m88e1111_config_init_hwcfg_mode(
906 MII_M1111_HWCFG_MODE_RTBI,
907 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
910 static int m88e1111_config_init_1000basex(struct phy_device *phydev)
912 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
918 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled */
919 mode = extsr & MII_M1111_HWCFG_MODE_MASK;
920 if (mode == MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN) {
921 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
922 MII_M1111_HWCFG_MODE_MASK |
923 MII_M1111_HWCFG_SERIAL_AN_BYPASS,
924 MII_M1111_HWCFG_MODE_COPPER_1000X_AN |
925 MII_M1111_HWCFG_SERIAL_AN_BYPASS);
932 static int m88e1111_config_init(struct phy_device *phydev)
936 if (phy_interface_is_rgmii(phydev)) {
937 err = m88e1111_config_init_rgmii(phydev);
942 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
943 err = m88e1111_config_init_sgmii(phydev);
948 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
949 err = m88e1111_config_init_rtbi(phydev);
954 if (phydev->interface == PHY_INTERFACE_MODE_1000BASEX) {
955 err = m88e1111_config_init_1000basex(phydev);
960 err = marvell_of_reg_init(phydev);
964 err = genphy_soft_reset(phydev);
968 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
969 /* If the HWCFG_MODE was changed from another mode (such as
970 * 1000BaseX) to SGMII, the state of the support bits may have
971 * also changed now that the PHY has been reset.
972 * Update the PHY abilities accordingly.
974 err = genphy_read_abilities(phydev);
975 linkmode_or(phydev->advertising, phydev->advertising,
981 static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
983 int val, cnt, enable;
985 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
989 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
990 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
992 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
997 static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
1001 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
1005 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
1006 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
1008 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
1009 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
1011 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR,
1012 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
1013 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
1020 return genphy_soft_reset(phydev);
1023 static int m88e1111_get_tunable(struct phy_device *phydev,
1024 struct ethtool_tunable *tuna, void *data)
1027 case ETHTOOL_PHY_DOWNSHIFT:
1028 return m88e1111_get_downshift(phydev, data);
1034 static int m88e1111_set_tunable(struct phy_device *phydev,
1035 struct ethtool_tunable *tuna, const void *data)
1038 case ETHTOOL_PHY_DOWNSHIFT:
1039 return m88e1111_set_downshift(phydev, *(const u8 *)data);
1045 static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
1047 int val, cnt, enable;
1049 val = phy_read(phydev, MII_M1011_PHY_SCR);
1053 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
1054 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
1056 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1061 static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
1065 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
1069 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR,
1070 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
1072 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
1073 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
1075 err = phy_modify(phydev, MII_M1011_PHY_SCR,
1076 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
1077 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
1084 return genphy_soft_reset(phydev);
1087 static int m88e1011_get_tunable(struct phy_device *phydev,
1088 struct ethtool_tunable *tuna, void *data)
1091 case ETHTOOL_PHY_DOWNSHIFT:
1092 return m88e1011_get_downshift(phydev, data);
1098 static int m88e1011_set_tunable(struct phy_device *phydev,
1099 struct ethtool_tunable *tuna, const void *data)
1102 case ETHTOOL_PHY_DOWNSHIFT:
1103 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1109 static int m88e1112_config_init(struct phy_device *phydev)
1113 err = m88e1011_set_downshift(phydev, 3);
1117 return m88e1111_config_init(phydev);
1120 static int m88e1111gbe_config_init(struct phy_device *phydev)
1124 err = m88e1111_set_downshift(phydev, 3);
1128 return m88e1111_config_init(phydev);
1131 static int marvell_1011gbe_config_init(struct phy_device *phydev)
1135 err = m88e1011_set_downshift(phydev, 3);
1139 return marvell_config_init(phydev);
1141 static int m88e1116r_config_init(struct phy_device *phydev)
1145 err = genphy_soft_reset(phydev);
1151 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1155 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1159 err = m88e1011_set_downshift(phydev, 8);
1163 if (phy_interface_is_rgmii(phydev)) {
1164 err = m88e1121_config_aneg_rgmii_delays(phydev);
1169 err = genphy_soft_reset(phydev);
1173 return marvell_config_init(phydev);
1176 static int m88e1318_config_init(struct phy_device *phydev)
1178 if (phy_interrupt_is_valid(phydev)) {
1179 int err = phy_modify_paged(
1180 phydev, MII_MARVELL_LED_PAGE,
1181 MII_88E1318S_PHY_LED_TCR,
1182 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1183 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1184 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1189 return marvell_config_init(phydev);
1192 static int m88e1510_config_init(struct phy_device *phydev)
1194 static const struct {
1205 /* As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/
1206 * 88E1514 Rev A0, Errata Section 5.1:
1207 * If EEE is intended to be used, the following register writes
1208 * must be done once after every hardware reset.
1210 err = marvell_set_page(phydev, 0x00FF);
1214 for (i = 0; i < ARRAY_SIZE(errata_vals); ++i) {
1215 err = phy_write(phydev, 17, errata_vals[i].reg17);
1218 err = phy_write(phydev, 16, errata_vals[i].reg16);
1223 err = marvell_set_page(phydev, 0x00FB);
1226 err = phy_write(phydev, 07, 0xC00D);
1229 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1233 /* SGMII-to-Copper mode initialization */
1234 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1235 /* Select page 18 */
1236 err = marvell_set_page(phydev, 18);
1240 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1241 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1242 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1243 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1247 /* PHY reset is necessary after changing MODE[2:0] */
1248 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
1249 MII_88E1510_GEN_CTRL_REG_1_RESET);
1253 /* Reset page selection */
1254 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1258 err = m88e1011_set_downshift(phydev, 3);
1262 return m88e1318_config_init(phydev);
1265 static int m88e1118_config_aneg(struct phy_device *phydev)
1269 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1273 err = genphy_config_aneg(phydev);
1277 return genphy_soft_reset(phydev);
1280 static int m88e1118_config_init(struct phy_device *phydev)
1285 /* Enable 1000 Mbit */
1286 err = phy_write_paged(phydev, MII_MARVELL_MSCR_PAGE,
1287 MII_88E1121_PHY_MSCR_REG, 0x1070);
1291 if (phy_interface_is_rgmii(phydev)) {
1292 err = m88e1121_config_aneg_rgmii_delays(phydev);
1297 /* Adjust LED Control */
1298 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1303 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, 0x10, leds);
1307 err = marvell_of_reg_init(phydev);
1311 /* Reset page register */
1312 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1316 return genphy_soft_reset(phydev);
1319 static int m88e1149_config_init(struct phy_device *phydev)
1323 /* Change address */
1324 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1328 /* Enable 1000 Mbit */
1329 err = phy_write(phydev, 0x15, 0x1048);
1333 err = marvell_of_reg_init(phydev);
1338 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1342 return genphy_soft_reset(phydev);
1345 static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1349 err = m88e1111_config_init_rgmii_delays(phydev);
1353 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1354 err = phy_write(phydev, 0x1d, 0x0012);
1358 err = phy_modify(phydev, 0x1e, 0x0fc0,
1359 2 << 9 | /* 36 ohm */
1360 2 << 6); /* 39 ohm */
1364 err = phy_write(phydev, 0x1d, 0x3);
1368 err = phy_write(phydev, 0x1e, 0x8000);
1373 static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1375 return m88e1111_config_init_hwcfg_mode(
1376 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1377 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1380 static int m88e1145_config_init(struct phy_device *phydev)
1384 /* Take care of errata E0 & E1 */
1385 err = phy_write(phydev, 0x1d, 0x001b);
1389 err = phy_write(phydev, 0x1e, 0x418f);
1393 err = phy_write(phydev, 0x1d, 0x0016);
1397 err = phy_write(phydev, 0x1e, 0xa2da);
1401 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1402 err = m88e1145_config_init_rgmii(phydev);
1407 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1408 err = m88e1145_config_init_sgmii(phydev);
1412 err = m88e1111_set_downshift(phydev, 3);
1416 err = marvell_of_reg_init(phydev);
1423 static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1427 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1431 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1432 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1436 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1439 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1442 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1445 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1448 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1458 static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1460 struct ethtool_eee eee;
1463 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1464 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1465 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1467 /* According to the Marvell data sheet EEE must be disabled for
1468 * Fast Link Down detection to work properly
1470 ret = phy_ethtool_get_eee(phydev, &eee);
1471 if (!ret && eee.eee_enabled) {
1472 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1477 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1478 else if (*msecs <= 15)
1479 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1480 else if (*msecs <= 30)
1481 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1483 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1485 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1487 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1488 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1492 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1493 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1496 static int m88e1540_get_tunable(struct phy_device *phydev,
1497 struct ethtool_tunable *tuna, void *data)
1500 case ETHTOOL_PHY_FAST_LINK_DOWN:
1501 return m88e1540_get_fld(phydev, data);
1502 case ETHTOOL_PHY_DOWNSHIFT:
1503 return m88e1011_get_downshift(phydev, data);
1509 static int m88e1540_set_tunable(struct phy_device *phydev,
1510 struct ethtool_tunable *tuna, const void *data)
1513 case ETHTOOL_PHY_FAST_LINK_DOWN:
1514 return m88e1540_set_fld(phydev, data);
1515 case ETHTOOL_PHY_DOWNSHIFT:
1516 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1522 /* The VOD can be out of specification on link up. Poke an
1523 * undocumented register, in an undocumented page, with a magic value
1526 static int m88e6390_errata(struct phy_device *phydev)
1530 err = phy_write(phydev, MII_BMCR,
1531 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1535 usleep_range(300, 400);
1537 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1541 return genphy_soft_reset(phydev);
1544 static int m88e6390_config_aneg(struct phy_device *phydev)
1548 err = m88e6390_errata(phydev);
1552 return m88e1510_config_aneg(phydev);
1556 * fiber_lpa_mod_linkmode_lpa_t
1557 * @advertising: the linkmode advertisement settings
1558 * @lpa: value of the MII_LPA register for fiber link
1560 * A small helper function that translates MII_LPA bits to linkmode LP
1561 * advertisement settings. Other bits in advertising are left
1564 static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1566 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1567 advertising, lpa & LPA_1000XHALF);
1569 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1570 advertising, lpa & LPA_1000XFULL);
1573 static int marvell_read_status_page_an(struct phy_device *phydev,
1574 int fiber, int status)
1579 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1584 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1585 phydev->duplex = DUPLEX_FULL;
1587 phydev->duplex = DUPLEX_HALF;
1589 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1590 case MII_M1011_PHY_STATUS_1000:
1591 phydev->speed = SPEED_1000;
1594 case MII_M1011_PHY_STATUS_100:
1595 phydev->speed = SPEED_100;
1599 phydev->speed = SPEED_10;
1604 err = genphy_read_lpa(phydev);
1608 phy_resolve_aneg_pause(phydev);
1610 lpa = phy_read(phydev, MII_LPA);
1614 /* The fiber link is only 1000M capable */
1615 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1617 if (phydev->duplex == DUPLEX_FULL) {
1618 if (!(lpa & LPA_PAUSE_FIBER)) {
1620 phydev->asym_pause = 0;
1621 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1623 phydev->asym_pause = 1;
1626 phydev->asym_pause = 0;
1634 /* marvell_read_status_page
1637 * Check the link, then figure out the current state
1638 * by comparing what we advertise with what the link partner
1639 * advertises. Start by checking the gigabit possibilities,
1640 * then move on to 10/100.
1642 static int marvell_read_status_page(struct phy_device *phydev, int page)
1648 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1652 /* Use the generic register for copper link status,
1653 * and the PHY status register for fiber link status.
1655 if (page == MII_MARVELL_FIBER_PAGE) {
1656 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1658 err = genphy_update_link(phydev);
1663 if (page == MII_MARVELL_FIBER_PAGE)
1668 linkmode_zero(phydev->lp_advertising);
1670 phydev->asym_pause = 0;
1671 phydev->speed = SPEED_UNKNOWN;
1672 phydev->duplex = DUPLEX_UNKNOWN;
1673 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1675 if (phydev->autoneg == AUTONEG_ENABLE)
1676 err = marvell_read_status_page_an(phydev, fiber, status);
1678 err = genphy_read_status_fixed(phydev);
1683 /* marvell_read_status
1685 * Some Marvell's phys have two modes: fiber and copper.
1686 * Both need status checked.
1688 * First, check the fiber link and status.
1689 * If the fiber link is down, check the copper link and status which
1690 * will be the default value if both link are down.
1692 static int marvell_read_status(struct phy_device *phydev)
1696 /* Check the fiber mode first */
1697 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1698 phydev->supported) &&
1699 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1700 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1704 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1708 /* If the fiber link is up, it is the selected and
1709 * used link. In this case, we need to stay in the
1710 * fiber page. Please to be careful about that, avoid
1711 * to restore Copper page in other functions which
1712 * could break the behaviour for some fiber phy like
1718 /* If fiber link is down, check and save copper mode state */
1719 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1724 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1727 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1733 * Some Marvell's phys have two modes: fiber and copper.
1734 * Both need to be suspended
1736 static int marvell_suspend(struct phy_device *phydev)
1740 /* Suspend the fiber mode first */
1741 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1742 phydev->supported)) {
1743 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1747 /* With the page set, use the generic suspend */
1748 err = genphy_suspend(phydev);
1752 /* Then, the copper link */
1753 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1758 /* With the page set, use the generic suspend */
1759 return genphy_suspend(phydev);
1762 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1768 * Some Marvell's phys have two modes: fiber and copper.
1769 * Both need to be resumed
1771 static int marvell_resume(struct phy_device *phydev)
1775 /* Resume the fiber mode first */
1776 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1777 phydev->supported)) {
1778 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1782 /* With the page set, use the generic resume */
1783 err = genphy_resume(phydev);
1787 /* Then, the copper link */
1788 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1793 /* With the page set, use the generic resume */
1794 return genphy_resume(phydev);
1797 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1801 static int marvell_aneg_done(struct phy_device *phydev)
1803 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1805 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1808 static void m88e1318_get_wol(struct phy_device *phydev,
1809 struct ethtool_wolinfo *wol)
1813 wol->supported = WAKE_MAGIC | WAKE_PHY;
1816 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1817 MII_88E1318S_PHY_WOL_CTRL);
1821 if (ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1822 wol->wolopts |= WAKE_MAGIC;
1824 if (ret & MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE)
1825 wol->wolopts |= WAKE_PHY;
1828 static int m88e1318_set_wol(struct phy_device *phydev,
1829 struct ethtool_wolinfo *wol)
1831 int err = 0, oldpage;
1833 oldpage = phy_save_page(phydev);
1837 if (wol->wolopts & (WAKE_MAGIC | WAKE_PHY)) {
1838 /* Explicitly switch to page 0x00, just to be sure */
1839 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1843 /* If WOL event happened once, the LED[2] interrupt pin
1844 * will not be cleared unless we reading the interrupt status
1845 * register. If interrupts are in use, the normal interrupt
1846 * handling will clear the WOL event. Clear the WOL event
1847 * before enabling it if !phy_interrupt_is_valid()
1849 if (!phy_interrupt_is_valid(phydev))
1850 __phy_read(phydev, MII_M1011_IEVENT);
1852 /* Enable the WOL interrupt */
1853 err = __phy_set_bits(phydev, MII_88E1318S_PHY_CSIER,
1854 MII_88E1318S_PHY_CSIER_WOL_EIE);
1858 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1862 /* Setup LED[2] as interrupt pin (active low) */
1863 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1864 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1865 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1866 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1871 if (wol->wolopts & WAKE_MAGIC) {
1872 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1876 /* Store the device address for the magic packet */
1877 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1878 ((phydev->attached_dev->dev_addr[5] << 8) |
1879 phydev->attached_dev->dev_addr[4]));
1882 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1883 ((phydev->attached_dev->dev_addr[3] << 8) |
1884 phydev->attached_dev->dev_addr[2]));
1887 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1888 ((phydev->attached_dev->dev_addr[1] << 8) |
1889 phydev->attached_dev->dev_addr[0]));
1893 /* Clear WOL status and enable magic packet matching */
1894 err = __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
1895 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1896 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1900 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1904 /* Clear WOL status and disable magic packet matching */
1905 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1906 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1907 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1912 if (wol->wolopts & WAKE_PHY) {
1913 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1917 /* Clear WOL status and enable link up event */
1918 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL, 0,
1919 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1920 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE);
1924 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1928 /* Clear WOL status and disable link up event */
1929 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1930 MII_88E1318S_PHY_WOL_CTRL_LINK_UP_ENABLE,
1931 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1937 return phy_restore_page(phydev, oldpage, err);
1940 static int marvell_get_sset_count(struct phy_device *phydev)
1942 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1944 return ARRAY_SIZE(marvell_hw_stats);
1946 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1949 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1951 int count = marvell_get_sset_count(phydev);
1954 for (i = 0; i < count; i++) {
1955 strlcpy(data + i * ETH_GSTRING_LEN,
1956 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1960 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1962 struct marvell_hw_stat stat = marvell_hw_stats[i];
1963 struct marvell_priv *priv = phydev->priv;
1967 val = phy_read_paged(phydev, stat.page, stat.reg);
1971 val = val & ((1 << stat.bits) - 1);
1972 priv->stats[i] += val;
1973 ret = priv->stats[i];
1979 static void marvell_get_stats(struct phy_device *phydev,
1980 struct ethtool_stats *stats, u64 *data)
1982 int count = marvell_get_sset_count(phydev);
1985 for (i = 0; i < count; i++)
1986 data[i] = marvell_get_stat(phydev, i);
1989 static int m88e1510_loopback(struct phy_device *phydev, bool enable)
1994 u16 bmcr_ctl = 0, mscr2_ctl = 0;
1996 if (phydev->speed == SPEED_1000)
1997 bmcr_ctl = BMCR_SPEED1000;
1998 else if (phydev->speed == SPEED_100)
1999 bmcr_ctl = BMCR_SPEED100;
2001 if (phydev->duplex == DUPLEX_FULL)
2002 bmcr_ctl |= BMCR_FULLDPLX;
2004 err = phy_write(phydev, MII_BMCR, bmcr_ctl);
2008 if (phydev->speed == SPEED_1000)
2009 mscr2_ctl = BMCR_SPEED1000;
2010 else if (phydev->speed == SPEED_100)
2011 mscr2_ctl = BMCR_SPEED100;
2013 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
2014 MII_88E1510_MSCR_2, BMCR_SPEED1000 |
2015 BMCR_SPEED100, mscr2_ctl);
2019 /* Need soft reset to have speed configuration takes effect */
2020 err = genphy_soft_reset(phydev);
2024 /* FIXME: Based on trial and error test, it seem 1G need to have
2025 * delay between soft reset and loopback enablement.
2027 if (phydev->speed == SPEED_1000)
2030 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
2033 err = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0);
2037 return phy_config_aneg(phydev);
2041 static int marvell_vct5_wait_complete(struct phy_device *phydev)
2046 for (i = 0; i < 32; i++) {
2047 val = __phy_read(phydev, MII_VCT5_CTRL);
2051 if (val & MII_VCT5_CTRL_COMPLETE)
2055 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
2059 static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
2065 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
2066 val = __phy_read(phydev, reg);
2071 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
2072 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
2074 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
2075 amplitude = -amplitude;
2077 return 1000 * amplitude / 128;
2080 static u32 marvell_vct5_distance2cm(int distance)
2082 return distance * 805 / 10;
2085 static u32 marvell_vct5_cm2distance(int cm)
2087 return cm * 10 / 805;
2090 static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
2091 int distance, int pair)
2098 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
2103 reg = MII_VCT5_CTRL_ENABLE |
2104 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2105 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2106 MII_VCT5_CTRL_SAMPLE_POINT |
2107 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
2108 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
2112 err = marvell_vct5_wait_complete(phydev);
2116 for (i = 0; i < 4; i++) {
2117 if (pair != PHY_PAIR_ALL && i != pair)
2120 mV = marvell_vct5_amplitude(phydev, i);
2121 ethnl_cable_test_amplitude(phydev, i, mV);
2127 static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
2129 struct marvell_priv *priv = phydev->priv;
2136 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
2137 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
2139 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2141 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2142 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2143 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2145 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2146 MII_VCT5_TX_PULSE_CTRL, reg);
2150 /* Reading the TDR data is very MDIO heavy. We need to optimize
2151 * access to keep the time to a minimum. So lock the bus once,
2152 * and don't release it until complete. We can then avoid having
2153 * to change the page for every access, greatly speeding things
2156 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
2160 for (distance = priv->first;
2161 distance <= priv->last;
2162 distance += priv->step) {
2163 err = marvell_vct5_amplitude_distance(phydev, distance,
2168 if (distance > TDR_SHORT_CABLE_LENGTH &&
2169 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
2170 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
2171 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
2172 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
2173 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
2174 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
2181 return phy_restore_page(phydev, page, err);
2184 static int marvell_cable_test_start_common(struct phy_device *phydev)
2186 int bmcr, bmsr, ret;
2188 /* If auto-negotiation is enabled, but not complete, the cable
2189 * test never completes. So disable auto-neg.
2191 bmcr = phy_read(phydev, MII_BMCR);
2195 bmsr = phy_read(phydev, MII_BMSR);
2200 if (bmcr & BMCR_ANENABLE) {
2201 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
2204 ret = genphy_soft_reset(phydev);
2209 /* If the link is up, allow it some time to go down */
2210 if (bmsr & BMSR_LSTATUS)
2216 static int marvell_vct7_cable_test_start(struct phy_device *phydev)
2218 struct marvell_priv *priv = phydev->priv;
2221 ret = marvell_cable_test_start_common(phydev);
2225 priv->cable_test_tdr = false;
2227 /* Reset the VCT5 API control to defaults, otherwise
2228 * VCT7 does not work correctly.
2230 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2232 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2233 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2234 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
2235 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
2239 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2240 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
2244 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2246 MII_VCT7_CTRL_RUN_NOW |
2247 MII_VCT7_CTRL_CENTIMETERS);
2250 static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
2251 const struct phy_tdr_config *cfg)
2253 struct marvell_priv *priv = phydev->priv;
2256 priv->cable_test_tdr = true;
2257 priv->first = marvell_vct5_cm2distance(cfg->first);
2258 priv->last = marvell_vct5_cm2distance(cfg->last);
2259 priv->step = marvell_vct5_cm2distance(cfg->step);
2260 priv->pair = cfg->pair;
2262 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2265 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2269 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2274 ret = marvell_cable_test_start_common(phydev);
2278 ret = ethnl_cable_test_pulse(phydev, 1000);
2282 return ethnl_cable_test_step(phydev,
2283 marvell_vct5_distance2cm(priv->first),
2284 marvell_vct5_distance2cm(priv->last),
2285 marvell_vct5_distance2cm(priv->step));
2288 static int marvell_vct7_distance_to_length(int distance, bool meter)
2296 static bool marvell_vct7_distance_valid(int result)
2299 case MII_VCT7_RESULTS_OPEN:
2300 case MII_VCT7_RESULTS_SAME_SHORT:
2301 case MII_VCT7_RESULTS_CROSS_SHORT:
2307 static int marvell_vct7_report_length(struct phy_device *phydev,
2308 int pair, bool meter)
2313 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2314 MII_VCT7_PAIR_0_DISTANCE + pair);
2318 length = marvell_vct7_distance_to_length(ret, meter);
2320 ethnl_cable_test_fault_length(phydev, pair, length);
2325 static int marvell_vct7_cable_test_report_trans(int result)
2328 case MII_VCT7_RESULTS_OK:
2329 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2330 case MII_VCT7_RESULTS_OPEN:
2331 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2332 case MII_VCT7_RESULTS_SAME_SHORT:
2333 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2334 case MII_VCT7_RESULTS_CROSS_SHORT:
2335 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2337 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2341 static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2343 int pair0, pair1, pair2, pair3;
2347 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2352 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2353 MII_VCT7_RESULTS_PAIR3_SHIFT;
2354 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2355 MII_VCT7_RESULTS_PAIR2_SHIFT;
2356 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2357 MII_VCT7_RESULTS_PAIR1_SHIFT;
2358 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2359 MII_VCT7_RESULTS_PAIR0_SHIFT;
2361 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2362 marvell_vct7_cable_test_report_trans(pair0));
2363 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2364 marvell_vct7_cable_test_report_trans(pair1));
2365 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2366 marvell_vct7_cable_test_report_trans(pair2));
2367 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2368 marvell_vct7_cable_test_report_trans(pair3));
2370 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2374 meter = ret & MII_VCT7_CTRL_METERS;
2376 if (marvell_vct7_distance_valid(pair0))
2377 marvell_vct7_report_length(phydev, 0, meter);
2378 if (marvell_vct7_distance_valid(pair1))
2379 marvell_vct7_report_length(phydev, 1, meter);
2380 if (marvell_vct7_distance_valid(pair2))
2381 marvell_vct7_report_length(phydev, 2, meter);
2382 if (marvell_vct7_distance_valid(pair3))
2383 marvell_vct7_report_length(phydev, 3, meter);
2388 static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2391 struct marvell_priv *priv = phydev->priv;
2394 if (priv->cable_test_tdr) {
2395 ret = marvell_vct5_amplitude_graph(phydev);
2402 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2408 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2411 return marvell_vct7_cable_test_report(phydev);
2418 struct marvell_hwmon_ops {
2419 int (*config)(struct phy_device *phydev);
2420 int (*get_temp)(struct phy_device *phydev, long *temp);
2421 int (*get_temp_critical)(struct phy_device *phydev, long *temp);
2422 int (*set_temp_critical)(struct phy_device *phydev, long temp);
2423 int (*get_temp_alarm)(struct phy_device *phydev, long *alarm);
2426 static const struct marvell_hwmon_ops *
2427 to_marvell_hwmon_ops(const struct phy_device *phydev)
2429 return phydev->drv->driver_data;
2432 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2440 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2444 /* Enable temperature sensor */
2445 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2449 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2450 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2454 /* Wait for temperature to stabilize */
2455 usleep_range(10000, 12000);
2457 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2463 /* Disable temperature sensor */
2464 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2465 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2469 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2472 return phy_restore_page(phydev, oldpage, ret);
2475 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2481 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2482 MII_88E1510_TEMP_SENSOR);
2486 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2491 static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2497 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2498 MII_88E1121_MISC_TEST);
2502 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2503 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2510 static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2513 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2515 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2516 MII_88E1121_MISC_TEST,
2517 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2518 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2521 static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2527 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2528 MII_88E1121_MISC_TEST);
2532 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2537 static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2546 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2550 /* Enable temperature sensor */
2551 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2555 ret &= ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2556 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE_SAMPLE_1S;
2558 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2562 /* Wait for temperature to stabilize */
2563 usleep_range(10000, 12000);
2565 /* Reading the temperature sense has an errata. You need to read
2566 * a number of times and take an average.
2568 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2569 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2572 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2575 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2576 *temp = (sum - 75) * 1000;
2578 /* Disable temperature sensor */
2579 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2583 ret = ret & ~MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK;
2584 ret |= MII_88E6390_MISC_TEST_TEMP_SENSOR_DISABLE;
2586 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2589 phy_restore_page(phydev, oldpage, ret);
2594 static int m88e6393_get_temp(struct phy_device *phydev, long *temp)
2598 err = m88e1510_get_temp(phydev, temp);
2600 /* 88E1510 measures T + 25, while the PHY on 88E6393X switch
2601 * T + 75, so we have to subtract another 50
2608 static int m88e6393_get_temp_critical(struct phy_device *phydev, long *temp)
2614 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2615 MII_88E6390_TEMP_SENSOR);
2619 *temp = (((ret & MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK) >>
2620 MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT) - 75) * 1000;
2625 static int m88e6393_set_temp_critical(struct phy_device *phydev, long temp)
2627 temp = (temp / 1000) + 75;
2629 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2630 MII_88E6390_TEMP_SENSOR,
2631 MII_88E6393_TEMP_SENSOR_THRESHOLD_MASK,
2632 temp << MII_88E6393_TEMP_SENSOR_THRESHOLD_SHIFT);
2635 static int m88e6393_hwmon_config(struct phy_device *phydev)
2639 err = m88e6393_set_temp_critical(phydev, 100000);
2643 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2644 MII_88E6390_MISC_TEST,
2645 MII_88E6390_MISC_TEST_TEMP_SENSOR_MASK |
2646 MII_88E6393_MISC_TEST_SAMPLES_MASK |
2647 MII_88E6393_MISC_TEST_RATE_MASK,
2648 MII_88E6390_MISC_TEST_TEMP_SENSOR_ENABLE |
2649 MII_88E6393_MISC_TEST_SAMPLES_2048 |
2650 MII_88E6393_MISC_TEST_RATE_2_3MS);
2653 static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
2654 u32 attr, int channel, long *temp)
2656 struct phy_device *phydev = dev_get_drvdata(dev);
2657 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2658 int err = -EOPNOTSUPP;
2661 case hwmon_temp_input:
2663 err = ops->get_temp(phydev, temp);
2665 case hwmon_temp_crit:
2666 if (ops->get_temp_critical)
2667 err = ops->get_temp_critical(phydev, temp);
2669 case hwmon_temp_max_alarm:
2670 if (ops->get_temp_alarm)
2671 err = ops->get_temp_alarm(phydev, temp);
2678 static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
2679 u32 attr, int channel, long temp)
2681 struct phy_device *phydev = dev_get_drvdata(dev);
2682 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2683 int err = -EOPNOTSUPP;
2686 case hwmon_temp_crit:
2687 if (ops->set_temp_critical)
2688 err = ops->set_temp_critical(phydev, temp);
2695 static umode_t marvell_hwmon_is_visible(const void *data,
2696 enum hwmon_sensor_types type,
2697 u32 attr, int channel)
2699 const struct phy_device *phydev = data;
2700 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2702 if (type != hwmon_temp)
2706 case hwmon_temp_input:
2707 return ops->get_temp ? 0444 : 0;
2708 case hwmon_temp_max_alarm:
2709 return ops->get_temp_alarm ? 0444 : 0;
2710 case hwmon_temp_crit:
2711 return (ops->get_temp_critical ? 0444 : 0) |
2712 (ops->set_temp_critical ? 0200 : 0);
2718 static u32 marvell_hwmon_chip_config[] = {
2719 HWMON_C_REGISTER_TZ,
2723 static const struct hwmon_channel_info marvell_hwmon_chip = {
2725 .config = marvell_hwmon_chip_config,
2728 /* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not
2729 * defined for all PHYs, because the hwmon code checks whether the attributes
2730 * exists via the .is_visible method
2732 static u32 marvell_hwmon_temp_config[] = {
2733 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2737 static const struct hwmon_channel_info marvell_hwmon_temp = {
2739 .config = marvell_hwmon_temp_config,
2742 static const struct hwmon_channel_info *marvell_hwmon_info[] = {
2743 &marvell_hwmon_chip,
2744 &marvell_hwmon_temp,
2748 static const struct hwmon_ops marvell_hwmon_hwmon_ops = {
2749 .is_visible = marvell_hwmon_is_visible,
2750 .read = marvell_hwmon_read,
2751 .write = marvell_hwmon_write,
2754 static const struct hwmon_chip_info marvell_hwmon_chip_info = {
2755 .ops = &marvell_hwmon_hwmon_ops,
2756 .info = marvell_hwmon_info,
2759 static int marvell_hwmon_name(struct phy_device *phydev)
2761 struct marvell_priv *priv = phydev->priv;
2762 struct device *dev = &phydev->mdio.dev;
2763 const char *devname = dev_name(dev);
2764 size_t len = strlen(devname);
2767 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2768 if (!priv->hwmon_name)
2771 for (i = j = 0; i < len && devname[i]; i++) {
2772 if (isalnum(devname[i]))
2773 priv->hwmon_name[j++] = devname[i];
2779 static int marvell_hwmon_probe(struct phy_device *phydev)
2781 const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);
2782 struct marvell_priv *priv = phydev->priv;
2783 struct device *dev = &phydev->mdio.dev;
2789 err = marvell_hwmon_name(phydev);
2793 priv->hwmon_dev = devm_hwmon_device_register_with_info(
2794 dev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL);
2795 if (IS_ERR(priv->hwmon_dev))
2796 return PTR_ERR(priv->hwmon_dev);
2799 err = ops->config(phydev);
2804 static const struct marvell_hwmon_ops m88e1121_hwmon_ops = {
2805 .get_temp = m88e1121_get_temp,
2808 static const struct marvell_hwmon_ops m88e1510_hwmon_ops = {
2809 .get_temp = m88e1510_get_temp,
2810 .get_temp_critical = m88e1510_get_temp_critical,
2811 .set_temp_critical = m88e1510_set_temp_critical,
2812 .get_temp_alarm = m88e1510_get_temp_alarm,
2815 static const struct marvell_hwmon_ops m88e6390_hwmon_ops = {
2816 .get_temp = m88e6390_get_temp,
2819 static const struct marvell_hwmon_ops m88e6393_hwmon_ops = {
2820 .config = m88e6393_hwmon_config,
2821 .get_temp = m88e6393_get_temp,
2822 .get_temp_critical = m88e6393_get_temp_critical,
2823 .set_temp_critical = m88e6393_set_temp_critical,
2824 .get_temp_alarm = m88e1510_get_temp_alarm,
2827 #define DEF_MARVELL_HWMON_OPS(s) (&(s))
2831 #define DEF_MARVELL_HWMON_OPS(s) NULL
2833 static int marvell_hwmon_probe(struct phy_device *phydev)
2839 static int marvell_probe(struct phy_device *phydev)
2841 struct marvell_priv *priv;
2843 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2847 phydev->priv = priv;
2849 return marvell_hwmon_probe(phydev);
2852 static int m88e1510_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
2854 struct phy_device *phydev = upstream;
2855 phy_interface_t interface;
2861 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
2863 dev = &phydev->mdio.dev;
2865 sfp_parse_support(phydev->sfp_bus, id, supported);
2866 interface = sfp_select_interface(phydev->sfp_bus, supported);
2868 dev_info(dev, "%s SFP module inserted\n", phy_modes(interface));
2870 switch (interface) {
2871 case PHY_INTERFACE_MODE_1000BASEX:
2872 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X;
2875 case PHY_INTERFACE_MODE_100BASEX:
2876 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX;
2879 case PHY_INTERFACE_MODE_SGMII:
2880 mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII;
2884 dev_err(dev, "Incompatible SFP module inserted\n");
2889 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
2893 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
2894 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK, mode);
2898 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
2899 MII_88E1510_GEN_CTRL_REG_1_RESET);
2902 return phy_restore_page(phydev, oldpage, ret);
2905 static void m88e1510_sfp_remove(void *upstream)
2907 struct phy_device *phydev = upstream;
2911 oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);
2915 ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
2916 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
2917 MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII);
2921 ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
2922 MII_88E1510_GEN_CTRL_REG_1_RESET);
2925 phy_restore_page(phydev, oldpage, ret);
2928 static const struct sfp_upstream_ops m88e1510_sfp_ops = {
2929 .module_insert = m88e1510_sfp_insert,
2930 .module_remove = m88e1510_sfp_remove,
2931 .attach = phy_sfp_attach,
2932 .detach = phy_sfp_detach,
2935 static int m88e1510_probe(struct phy_device *phydev)
2939 err = marvell_probe(phydev);
2943 return phy_sfp_probe(phydev, &m88e1510_sfp_ops);
2946 static struct phy_driver marvell_drivers[] = {
2948 .phy_id = MARVELL_PHY_ID_88E1101,
2949 .phy_id_mask = MARVELL_PHY_ID_MASK,
2950 .name = "Marvell 88E1101",
2951 /* PHY_GBIT_FEATURES */
2952 .probe = marvell_probe,
2953 .config_init = marvell_config_init,
2954 .config_aneg = m88e1101_config_aneg,
2955 .config_intr = marvell_config_intr,
2956 .handle_interrupt = marvell_handle_interrupt,
2957 .resume = genphy_resume,
2958 .suspend = genphy_suspend,
2959 .read_page = marvell_read_page,
2960 .write_page = marvell_write_page,
2961 .get_sset_count = marvell_get_sset_count,
2962 .get_strings = marvell_get_strings,
2963 .get_stats = marvell_get_stats,
2966 .phy_id = MARVELL_PHY_ID_88E1112,
2967 .phy_id_mask = MARVELL_PHY_ID_MASK,
2968 .name = "Marvell 88E1112",
2969 /* PHY_GBIT_FEATURES */
2970 .probe = marvell_probe,
2971 .config_init = m88e1112_config_init,
2972 .config_aneg = marvell_config_aneg,
2973 .config_intr = marvell_config_intr,
2974 .handle_interrupt = marvell_handle_interrupt,
2975 .resume = genphy_resume,
2976 .suspend = genphy_suspend,
2977 .read_page = marvell_read_page,
2978 .write_page = marvell_write_page,
2979 .get_sset_count = marvell_get_sset_count,
2980 .get_strings = marvell_get_strings,
2981 .get_stats = marvell_get_stats,
2982 .get_tunable = m88e1011_get_tunable,
2983 .set_tunable = m88e1011_set_tunable,
2986 .phy_id = MARVELL_PHY_ID_88E1111,
2987 .phy_id_mask = MARVELL_PHY_ID_MASK,
2988 .name = "Marvell 88E1111",
2989 /* PHY_GBIT_FEATURES */
2990 .probe = marvell_probe,
2991 .config_init = m88e1111gbe_config_init,
2992 .config_aneg = m88e1111_config_aneg,
2993 .read_status = marvell_read_status,
2994 .config_intr = marvell_config_intr,
2995 .handle_interrupt = marvell_handle_interrupt,
2996 .resume = genphy_resume,
2997 .suspend = genphy_suspend,
2998 .read_page = marvell_read_page,
2999 .write_page = marvell_write_page,
3000 .get_sset_count = marvell_get_sset_count,
3001 .get_strings = marvell_get_strings,
3002 .get_stats = marvell_get_stats,
3003 .get_tunable = m88e1111_get_tunable,
3004 .set_tunable = m88e1111_set_tunable,
3007 .phy_id = MARVELL_PHY_ID_88E1111_FINISAR,
3008 .phy_id_mask = MARVELL_PHY_ID_MASK,
3009 .name = "Marvell 88E1111 (Finisar)",
3010 /* PHY_GBIT_FEATURES */
3011 .probe = marvell_probe,
3012 .config_init = m88e1111gbe_config_init,
3013 .config_aneg = m88e1111_config_aneg,
3014 .read_status = marvell_read_status,
3015 .config_intr = marvell_config_intr,
3016 .handle_interrupt = marvell_handle_interrupt,
3017 .resume = genphy_resume,
3018 .suspend = genphy_suspend,
3019 .read_page = marvell_read_page,
3020 .write_page = marvell_write_page,
3021 .get_sset_count = marvell_get_sset_count,
3022 .get_strings = marvell_get_strings,
3023 .get_stats = marvell_get_stats,
3024 .get_tunable = m88e1111_get_tunable,
3025 .set_tunable = m88e1111_set_tunable,
3028 .phy_id = MARVELL_PHY_ID_88E1118,
3029 .phy_id_mask = MARVELL_PHY_ID_MASK,
3030 .name = "Marvell 88E1118",
3031 /* PHY_GBIT_FEATURES */
3032 .probe = marvell_probe,
3033 .config_init = m88e1118_config_init,
3034 .config_aneg = m88e1118_config_aneg,
3035 .config_intr = marvell_config_intr,
3036 .handle_interrupt = marvell_handle_interrupt,
3037 .resume = genphy_resume,
3038 .suspend = genphy_suspend,
3039 .read_page = marvell_read_page,
3040 .write_page = marvell_write_page,
3041 .get_sset_count = marvell_get_sset_count,
3042 .get_strings = marvell_get_strings,
3043 .get_stats = marvell_get_stats,
3046 .phy_id = MARVELL_PHY_ID_88E1121R,
3047 .phy_id_mask = MARVELL_PHY_ID_MASK,
3048 .name = "Marvell 88E1121R",
3049 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops),
3050 /* PHY_GBIT_FEATURES */
3051 .probe = marvell_probe,
3052 .config_init = marvell_1011gbe_config_init,
3053 .config_aneg = m88e1121_config_aneg,
3054 .read_status = marvell_read_status,
3055 .config_intr = marvell_config_intr,
3056 .handle_interrupt = marvell_handle_interrupt,
3057 .resume = genphy_resume,
3058 .suspend = genphy_suspend,
3059 .read_page = marvell_read_page,
3060 .write_page = marvell_write_page,
3061 .get_sset_count = marvell_get_sset_count,
3062 .get_strings = marvell_get_strings,
3063 .get_stats = marvell_get_stats,
3064 .get_tunable = m88e1011_get_tunable,
3065 .set_tunable = m88e1011_set_tunable,
3068 .phy_id = MARVELL_PHY_ID_88E1318S,
3069 .phy_id_mask = MARVELL_PHY_ID_MASK,
3070 .name = "Marvell 88E1318S",
3071 /* PHY_GBIT_FEATURES */
3072 .probe = marvell_probe,
3073 .config_init = m88e1318_config_init,
3074 .config_aneg = m88e1318_config_aneg,
3075 .read_status = marvell_read_status,
3076 .config_intr = marvell_config_intr,
3077 .handle_interrupt = marvell_handle_interrupt,
3078 .get_wol = m88e1318_get_wol,
3079 .set_wol = m88e1318_set_wol,
3080 .resume = genphy_resume,
3081 .suspend = genphy_suspend,
3082 .read_page = marvell_read_page,
3083 .write_page = marvell_write_page,
3084 .get_sset_count = marvell_get_sset_count,
3085 .get_strings = marvell_get_strings,
3086 .get_stats = marvell_get_stats,
3089 .phy_id = MARVELL_PHY_ID_88E1145,
3090 .phy_id_mask = MARVELL_PHY_ID_MASK,
3091 .name = "Marvell 88E1145",
3092 /* PHY_GBIT_FEATURES */
3093 .probe = marvell_probe,
3094 .config_init = m88e1145_config_init,
3095 .config_aneg = m88e1101_config_aneg,
3096 .config_intr = marvell_config_intr,
3097 .handle_interrupt = marvell_handle_interrupt,
3098 .resume = genphy_resume,
3099 .suspend = genphy_suspend,
3100 .read_page = marvell_read_page,
3101 .write_page = marvell_write_page,
3102 .get_sset_count = marvell_get_sset_count,
3103 .get_strings = marvell_get_strings,
3104 .get_stats = marvell_get_stats,
3105 .get_tunable = m88e1111_get_tunable,
3106 .set_tunable = m88e1111_set_tunable,
3109 .phy_id = MARVELL_PHY_ID_88E1149R,
3110 .phy_id_mask = MARVELL_PHY_ID_MASK,
3111 .name = "Marvell 88E1149R",
3112 /* PHY_GBIT_FEATURES */
3113 .probe = marvell_probe,
3114 .config_init = m88e1149_config_init,
3115 .config_aneg = m88e1118_config_aneg,
3116 .config_intr = marvell_config_intr,
3117 .handle_interrupt = marvell_handle_interrupt,
3118 .resume = genphy_resume,
3119 .suspend = genphy_suspend,
3120 .read_page = marvell_read_page,
3121 .write_page = marvell_write_page,
3122 .get_sset_count = marvell_get_sset_count,
3123 .get_strings = marvell_get_strings,
3124 .get_stats = marvell_get_stats,
3127 .phy_id = MARVELL_PHY_ID_88E1240,
3128 .phy_id_mask = MARVELL_PHY_ID_MASK,
3129 .name = "Marvell 88E1240",
3130 /* PHY_GBIT_FEATURES */
3131 .probe = marvell_probe,
3132 .config_init = m88e1112_config_init,
3133 .config_aneg = marvell_config_aneg,
3134 .config_intr = marvell_config_intr,
3135 .handle_interrupt = marvell_handle_interrupt,
3136 .resume = genphy_resume,
3137 .suspend = genphy_suspend,
3138 .read_page = marvell_read_page,
3139 .write_page = marvell_write_page,
3140 .get_sset_count = marvell_get_sset_count,
3141 .get_strings = marvell_get_strings,
3142 .get_stats = marvell_get_stats,
3143 .get_tunable = m88e1011_get_tunable,
3144 .set_tunable = m88e1011_set_tunable,
3147 .phy_id = MARVELL_PHY_ID_88E1116R,
3148 .phy_id_mask = MARVELL_PHY_ID_MASK,
3149 .name = "Marvell 88E1116R",
3150 /* PHY_GBIT_FEATURES */
3151 .probe = marvell_probe,
3152 .config_init = m88e1116r_config_init,
3153 .config_intr = marvell_config_intr,
3154 .handle_interrupt = marvell_handle_interrupt,
3155 .resume = genphy_resume,
3156 .suspend = genphy_suspend,
3157 .read_page = marvell_read_page,
3158 .write_page = marvell_write_page,
3159 .get_sset_count = marvell_get_sset_count,
3160 .get_strings = marvell_get_strings,
3161 .get_stats = marvell_get_stats,
3162 .get_tunable = m88e1011_get_tunable,
3163 .set_tunable = m88e1011_set_tunable,
3166 .phy_id = MARVELL_PHY_ID_88E1510,
3167 .phy_id_mask = MARVELL_PHY_ID_MASK,
3168 .name = "Marvell 88E1510",
3169 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3170 .features = PHY_GBIT_FIBRE_FEATURES,
3171 .flags = PHY_POLL_CABLE_TEST,
3172 .probe = m88e1510_probe,
3173 .config_init = m88e1510_config_init,
3174 .config_aneg = m88e1510_config_aneg,
3175 .read_status = marvell_read_status,
3176 .config_intr = marvell_config_intr,
3177 .handle_interrupt = marvell_handle_interrupt,
3178 .get_wol = m88e1318_get_wol,
3179 .set_wol = m88e1318_set_wol,
3180 .resume = marvell_resume,
3181 .suspend = marvell_suspend,
3182 .read_page = marvell_read_page,
3183 .write_page = marvell_write_page,
3184 .get_sset_count = marvell_get_sset_count,
3185 .get_strings = marvell_get_strings,
3186 .get_stats = marvell_get_stats,
3187 .set_loopback = m88e1510_loopback,
3188 .get_tunable = m88e1011_get_tunable,
3189 .set_tunable = m88e1011_set_tunable,
3190 .cable_test_start = marvell_vct7_cable_test_start,
3191 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3192 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3195 .phy_id = MARVELL_PHY_ID_88E1540,
3196 .phy_id_mask = MARVELL_PHY_ID_MASK,
3197 .name = "Marvell 88E1540",
3198 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3199 /* PHY_GBIT_FEATURES */
3200 .flags = PHY_POLL_CABLE_TEST,
3201 .probe = marvell_probe,
3202 .config_init = marvell_1011gbe_config_init,
3203 .config_aneg = m88e1510_config_aneg,
3204 .read_status = marvell_read_status,
3205 .config_intr = marvell_config_intr,
3206 .handle_interrupt = marvell_handle_interrupt,
3207 .resume = genphy_resume,
3208 .suspend = genphy_suspend,
3209 .read_page = marvell_read_page,
3210 .write_page = marvell_write_page,
3211 .get_sset_count = marvell_get_sset_count,
3212 .get_strings = marvell_get_strings,
3213 .get_stats = marvell_get_stats,
3214 .get_tunable = m88e1540_get_tunable,
3215 .set_tunable = m88e1540_set_tunable,
3216 .cable_test_start = marvell_vct7_cable_test_start,
3217 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3218 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3221 .phy_id = MARVELL_PHY_ID_88E1545,
3222 .phy_id_mask = MARVELL_PHY_ID_MASK,
3223 .name = "Marvell 88E1545",
3224 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3225 .probe = marvell_probe,
3226 /* PHY_GBIT_FEATURES */
3227 .flags = PHY_POLL_CABLE_TEST,
3228 .config_init = marvell_1011gbe_config_init,
3229 .config_aneg = m88e1510_config_aneg,
3230 .read_status = marvell_read_status,
3231 .config_intr = marvell_config_intr,
3232 .handle_interrupt = marvell_handle_interrupt,
3233 .resume = genphy_resume,
3234 .suspend = genphy_suspend,
3235 .read_page = marvell_read_page,
3236 .write_page = marvell_write_page,
3237 .get_sset_count = marvell_get_sset_count,
3238 .get_strings = marvell_get_strings,
3239 .get_stats = marvell_get_stats,
3240 .get_tunable = m88e1540_get_tunable,
3241 .set_tunable = m88e1540_set_tunable,
3242 .cable_test_start = marvell_vct7_cable_test_start,
3243 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3244 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3247 .phy_id = MARVELL_PHY_ID_88E3016,
3248 .phy_id_mask = MARVELL_PHY_ID_MASK,
3249 .name = "Marvell 88E3016",
3250 /* PHY_BASIC_FEATURES */
3251 .probe = marvell_probe,
3252 .config_init = m88e3016_config_init,
3253 .aneg_done = marvell_aneg_done,
3254 .read_status = marvell_read_status,
3255 .config_intr = marvell_config_intr,
3256 .handle_interrupt = marvell_handle_interrupt,
3257 .resume = genphy_resume,
3258 .suspend = genphy_suspend,
3259 .read_page = marvell_read_page,
3260 .write_page = marvell_write_page,
3261 .get_sset_count = marvell_get_sset_count,
3262 .get_strings = marvell_get_strings,
3263 .get_stats = marvell_get_stats,
3266 .phy_id = MARVELL_PHY_ID_88E6341_FAMILY,
3267 .phy_id_mask = MARVELL_PHY_ID_MASK,
3268 .name = "Marvell 88E6341 Family",
3269 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3270 /* PHY_GBIT_FEATURES */
3271 .flags = PHY_POLL_CABLE_TEST,
3272 .probe = marvell_probe,
3273 .config_init = marvell_1011gbe_config_init,
3274 .config_aneg = m88e6390_config_aneg,
3275 .read_status = marvell_read_status,
3276 .config_intr = marvell_config_intr,
3277 .handle_interrupt = marvell_handle_interrupt,
3278 .resume = genphy_resume,
3279 .suspend = genphy_suspend,
3280 .read_page = marvell_read_page,
3281 .write_page = marvell_write_page,
3282 .get_sset_count = marvell_get_sset_count,
3283 .get_strings = marvell_get_strings,
3284 .get_stats = marvell_get_stats,
3285 .get_tunable = m88e1540_get_tunable,
3286 .set_tunable = m88e1540_set_tunable,
3287 .cable_test_start = marvell_vct7_cable_test_start,
3288 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3289 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3292 .phy_id = MARVELL_PHY_ID_88E6390_FAMILY,
3293 .phy_id_mask = MARVELL_PHY_ID_MASK,
3294 .name = "Marvell 88E6390 Family",
3295 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops),
3296 /* PHY_GBIT_FEATURES */
3297 .flags = PHY_POLL_CABLE_TEST,
3298 .probe = marvell_probe,
3299 .config_init = marvell_1011gbe_config_init,
3300 .config_aneg = m88e6390_config_aneg,
3301 .read_status = marvell_read_status,
3302 .config_intr = marvell_config_intr,
3303 .handle_interrupt = marvell_handle_interrupt,
3304 .resume = genphy_resume,
3305 .suspend = genphy_suspend,
3306 .read_page = marvell_read_page,
3307 .write_page = marvell_write_page,
3308 .get_sset_count = marvell_get_sset_count,
3309 .get_strings = marvell_get_strings,
3310 .get_stats = marvell_get_stats,
3311 .get_tunable = m88e1540_get_tunable,
3312 .set_tunable = m88e1540_set_tunable,
3313 .cable_test_start = marvell_vct7_cable_test_start,
3314 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3315 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3318 .phy_id = MARVELL_PHY_ID_88E6393_FAMILY,
3319 .phy_id_mask = MARVELL_PHY_ID_MASK,
3320 .name = "Marvell 88E6393 Family",
3321 .driver_data = DEF_MARVELL_HWMON_OPS(m88e6393_hwmon_ops),
3322 /* PHY_GBIT_FEATURES */
3323 .flags = PHY_POLL_CABLE_TEST,
3324 .probe = marvell_probe,
3325 .config_init = marvell_1011gbe_config_init,
3326 .config_aneg = m88e1510_config_aneg,
3327 .read_status = marvell_read_status,
3328 .config_intr = marvell_config_intr,
3329 .handle_interrupt = marvell_handle_interrupt,
3330 .resume = genphy_resume,
3331 .suspend = genphy_suspend,
3332 .read_page = marvell_read_page,
3333 .write_page = marvell_write_page,
3334 .get_sset_count = marvell_get_sset_count,
3335 .get_strings = marvell_get_strings,
3336 .get_stats = marvell_get_stats,
3337 .get_tunable = m88e1540_get_tunable,
3338 .set_tunable = m88e1540_set_tunable,
3339 .cable_test_start = marvell_vct7_cable_test_start,
3340 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3341 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3344 .phy_id = MARVELL_PHY_ID_88E1340S,
3345 .phy_id_mask = MARVELL_PHY_ID_MASK,
3346 .name = "Marvell 88E1340S",
3347 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3348 .probe = marvell_probe,
3349 /* PHY_GBIT_FEATURES */
3350 .config_init = marvell_1011gbe_config_init,
3351 .config_aneg = m88e1510_config_aneg,
3352 .read_status = marvell_read_status,
3353 .config_intr = marvell_config_intr,
3354 .handle_interrupt = marvell_handle_interrupt,
3355 .resume = genphy_resume,
3356 .suspend = genphy_suspend,
3357 .read_page = marvell_read_page,
3358 .write_page = marvell_write_page,
3359 .get_sset_count = marvell_get_sset_count,
3360 .get_strings = marvell_get_strings,
3361 .get_stats = marvell_get_stats,
3362 .get_tunable = m88e1540_get_tunable,
3363 .set_tunable = m88e1540_set_tunable,
3366 .phy_id = MARVELL_PHY_ID_88E1548P,
3367 .phy_id_mask = MARVELL_PHY_ID_MASK,
3368 .name = "Marvell 88E1548P",
3369 .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),
3370 .probe = marvell_probe,
3371 .features = PHY_GBIT_FIBRE_FEATURES,
3372 .config_init = marvell_1011gbe_config_init,
3373 .config_aneg = m88e1510_config_aneg,
3374 .read_status = marvell_read_status,
3375 .config_intr = marvell_config_intr,
3376 .handle_interrupt = marvell_handle_interrupt,
3377 .resume = genphy_resume,
3378 .suspend = genphy_suspend,
3379 .read_page = marvell_read_page,
3380 .write_page = marvell_write_page,
3381 .get_sset_count = marvell_get_sset_count,
3382 .get_strings = marvell_get_strings,
3383 .get_stats = marvell_get_stats,
3384 .get_tunable = m88e1540_get_tunable,
3385 .set_tunable = m88e1540_set_tunable,
3389 module_phy_driver(marvell_drivers);
3391 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
3392 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3393 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3394 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
3395 { MARVELL_PHY_ID_88E1111_FINISAR, MARVELL_PHY_ID_MASK },
3396 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3397 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3398 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3399 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3400 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3401 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3402 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
3403 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
3404 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
3405 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
3406 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
3407 { MARVELL_PHY_ID_88E6341_FAMILY, MARVELL_PHY_ID_MASK },
3408 { MARVELL_PHY_ID_88E6390_FAMILY, MARVELL_PHY_ID_MASK },
3409 { MARVELL_PHY_ID_88E6393_FAMILY, MARVELL_PHY_ID_MASK },
3410 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
3411 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
3415 MODULE_DEVICE_TABLE(mdio, marvell_tbl);