1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
10 #include <marvell_phy.h>
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
15 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
17 #define MII_MARVELL_PHY_PAGE 22
19 /* 88E1011 PHY Status Register */
20 #define MIIM_88E1xxx_PHY_STATUS 0x11
21 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
22 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
23 #define MIIM_88E1xxx_PHYSTAT_100 0x4000
24 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
25 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
26 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
28 #define MIIM_88E1xxx_PHY_SCR 0x10
29 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
31 /* 88E1111 PHY LED Control Register */
32 #define MIIM_88E1111_PHY_LED_CONTROL 24
33 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
34 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
36 /* 88E1111 Extended PHY Specific Control Register */
37 #define MIIM_88E1111_PHY_EXT_CR 0x14
38 #define MIIM_88E1111_RX_DELAY 0x80
39 #define MIIM_88E1111_TX_DELAY 0x2
41 /* 88E1111 Extended PHY Specific Status Register */
42 #define MIIM_88E1111_PHY_EXT_SR 0x1b
43 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf
44 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
45 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
46 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
47 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
48 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
49 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
51 #define MIIM_88E1111_COPPER 0
52 #define MIIM_88E1111_FIBER 1
54 /* 88E1118 PHY defines */
55 #define MIIM_88E1118_PHY_PAGE 22
56 #define MIIM_88E1118_PHY_LED_PAGE 3
58 /* 88E1121 PHY LED Control Register */
59 #define MIIM_88E1121_PHY_LED_CTRL 16
60 #define MIIM_88E1121_PHY_LED_PAGE 3
61 #define MIIM_88E1121_PHY_LED_DEF 0x0030
63 /* 88E1121 PHY IRQ Enable/Status Register */
64 #define MIIM_88E1121_PHY_IRQ_EN 18
65 #define MIIM_88E1121_PHY_IRQ_STATUS 19
67 #define MIIM_88E1121_PHY_PAGE 22
69 /* 88E1145 Extended PHY Specific Control Register */
70 #define MIIM_88E1145_PHY_EXT_CR 20
71 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
72 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
74 #define MIIM_88E1145_PHY_LED_CONTROL 24
75 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100
77 #define MIIM_88E1145_PHY_PAGE 29
78 #define MIIM_88E1145_PHY_CAL_OV 30
80 #define MIIM_88E1149_PHY_PAGE 29
82 /* 88E1310 PHY defines */
83 #define MIIM_88E1310_PHY_LED_CTRL 16
84 #define MIIM_88E1310_PHY_IRQ_EN 18
85 #define MIIM_88E1310_PHY_RGMII_CTRL 21
86 #define MIIM_88E1310_PHY_PAGE 22
88 /* 88E151x PHY defines */
89 /* Page 2 registers */
90 #define MIIM_88E151x_PHY_MSCR 21
91 #define MIIM_88E151x_RGMII_RX_DELAY BIT(5)
92 #define MIIM_88E151x_RGMII_TX_DELAY BIT(4)
93 #define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4))
94 /* Page 3 registers */
95 #define MIIM_88E151x_LED_FUNC_CTRL 16
96 #define MIIM_88E151x_LED_FLD_SZ 4
97 #define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ)
98 #define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ)
99 #define MIIM_88E151x_LED0_ACT 3
100 #define MIIM_88E151x_LED1_100_1000_LINK 6
101 #define MIIM_88E151x_LED_TIMER_CTRL 18
102 #define MIIM_88E151x_INT_EN_OFFS 7
103 /* Page 18 registers */
104 #define MIIM_88E151x_GENERAL_CTRL 20
105 #define MIIM_88E151x_MODE_SGMII 1
106 #define MIIM_88E151x_RESET_OFFS 15
108 static int marvell_read_page(struct phy_device *phydev)
110 return phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
113 static int marvell_write_page(struct phy_device *phydev, int page)
115 return phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, page);
118 /* Set and/or override some configuration registers based on the
119 * marvell,reg-init property stored in the of_node for the phydev.
121 * marvell,reg-init = <reg-page reg mask value>,...;
123 * There may be one or more sets of <reg-page reg mask value>:
125 * reg-page: which register bank to use.
127 * mask: if non-zero, ANDed with existing register value.
128 * value: ORed with the masked value and written to the regiser.
131 static int marvell_of_reg_init(struct phy_device *phydev)
134 int len, i, saved_page, current_page, ret = 0;
136 if (!ofnode_valid(phydev->node))
139 prop = ofnode_get_property(phydev->node, "marvell,reg-init", &len);
143 saved_page = marvell_read_page(phydev);
146 current_page = saved_page;
148 len /= sizeof(*prop);
149 for (i = 0; i < len - 3; i += 4) {
150 u16 page = be32_to_cpup(prop + i);
151 u16 reg = be32_to_cpup(prop + i + 1);
152 u16 mask = be32_to_cpup(prop + i + 2);
153 u16 val_bits = be32_to_cpup(prop + i + 3);
156 if (page != current_page) {
158 ret = marvell_write_page(phydev, page);
165 val = phy_read(phydev, MDIO_DEVAD_NONE, reg);
174 ret = phy_write(phydev, MDIO_DEVAD_NONE, reg, val);
180 return marvell_write_page(phydev, saved_page);
183 static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
184 int devaddr, int regnum)
186 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
189 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
190 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
191 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
196 static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr,
197 int devaddr, int regnum, u16 val)
199 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
201 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr);
202 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
203 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage);
208 /* Marvell 88E1011S */
209 static int m88e1011s_config(struct phy_device *phydev)
211 /* Reset and configure the PHY */
212 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
214 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
215 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
216 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
217 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
218 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
220 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
222 marvell_of_reg_init(phydev);
224 genphy_config_aneg(phydev);
229 /* Parse the 88E1011's status register for speed and duplex
232 static int m88e1xxx_parse_status(struct phy_device *phydev)
235 unsigned int mii_reg;
237 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
239 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
240 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
243 puts("Waiting for PHY realtime link");
244 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
245 /* Timeout reached ? */
246 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
247 puts(" TIMEOUT !\n");
252 if ((i++ % 1000) == 0)
255 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
256 MIIM_88E1xxx_PHY_STATUS);
259 mdelay(500); /* another 500 ms (results in faster booting) */
261 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
267 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
268 phydev->duplex = DUPLEX_FULL;
270 phydev->duplex = DUPLEX_HALF;
272 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
275 case MIIM_88E1xxx_PHYSTAT_GBIT:
276 phydev->speed = SPEED_1000;
278 case MIIM_88E1xxx_PHYSTAT_100:
279 phydev->speed = SPEED_100;
282 phydev->speed = SPEED_10;
289 static int m88e1011s_startup(struct phy_device *phydev)
293 ret = genphy_update_link(phydev);
297 return m88e1xxx_parse_status(phydev);
300 /* Marvell 88E1111S */
301 static int m88e1111s_config(struct phy_device *phydev)
305 if (phy_interface_is_rgmii(phydev)) {
306 reg = phy_read(phydev,
307 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
308 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
309 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
310 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
311 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
312 reg &= ~MIIM_88E1111_TX_DELAY;
313 reg |= MIIM_88E1111_RX_DELAY;
314 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
315 reg &= ~MIIM_88E1111_RX_DELAY;
316 reg |= MIIM_88E1111_TX_DELAY;
320 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
322 reg = phy_read(phydev,
323 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
325 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
327 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
328 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
330 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
333 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
336 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
337 reg = phy_read(phydev,
338 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
340 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
341 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
342 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
344 phy_write(phydev, MDIO_DEVAD_NONE,
345 MIIM_88E1111_PHY_EXT_SR, reg);
348 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
349 reg = phy_read(phydev,
350 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
351 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
353 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
355 reg = phy_read(phydev, MDIO_DEVAD_NONE,
356 MIIM_88E1111_PHY_EXT_SR);
357 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
358 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
359 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
360 phy_write(phydev, MDIO_DEVAD_NONE,
361 MIIM_88E1111_PHY_EXT_SR, reg);
366 reg = phy_read(phydev, MDIO_DEVAD_NONE,
367 MIIM_88E1111_PHY_EXT_SR);
368 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
369 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
370 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
371 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
372 phy_write(phydev, MDIO_DEVAD_NONE,
373 MIIM_88E1111_PHY_EXT_SR, reg);
379 marvell_of_reg_init(phydev);
381 genphy_config_aneg(phydev);
382 genphy_restart_aneg(phydev);
388 * m88e151x_phy_writebits - write bits to a register
390 void m88e151x_phy_writebits(struct phy_device *phydev,
391 u8 reg_num, u16 offset, u16 len, u16 data)
395 if ((len + offset) >= 16)
396 mask = 0 - (1 << offset);
398 mask = (1 << (len + offset)) - (1 << offset);
400 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
403 reg |= data << offset;
405 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
408 static int m88e151x_config(struct phy_device *phydev)
413 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
414 * /88E1514 Rev A0, Errata Section 3.1
417 /* EEE initialization */
418 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
419 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
420 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
421 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
422 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
423 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
424 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
425 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
426 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
427 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
429 /* SGMII-to-Copper mode initialization */
430 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
432 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
434 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
435 m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
436 0, 3, MIIM_88E151x_MODE_SGMII);
438 /* PHY reset is necessary after changing MODE[2:0] */
439 m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
440 MIIM_88E151x_RESET_OFFS, 1, 1);
442 /* Reset page selection */
443 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
448 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
449 reg = phy_read(phydev, MDIO_DEVAD_NONE,
450 MIIM_88E1111_PHY_EXT_SR);
452 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
453 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
454 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
456 phy_write(phydev, MDIO_DEVAD_NONE,
457 MIIM_88E1111_PHY_EXT_SR, reg);
460 if (phy_interface_is_rgmii(phydev)) {
461 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2);
463 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR);
464 reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY;
465 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
466 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
467 reg |= MIIM_88E151x_RGMII_RXTX_DELAY;
468 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
469 reg |= MIIM_88E151x_RGMII_RX_DELAY;
470 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
471 reg |= MIIM_88E151x_RGMII_TX_DELAY;
472 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg);
474 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0);
480 marvell_of_reg_init(phydev);
482 genphy_config_aneg(phydev);
483 genphy_restart_aneg(phydev);
488 /* Marvell 88E1118 */
489 static int m88e1118_config(struct phy_device *phydev)
491 /* Change Page Number */
492 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
493 /* Delay RGMII TX and RX */
494 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
495 /* Change Page Number */
496 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
497 /* Adjust LED control */
498 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
499 /* Change Page Number */
500 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
502 marvell_of_reg_init(phydev);
504 return genphy_config_aneg(phydev);
507 static int m88e1118_startup(struct phy_device *phydev)
511 /* Change Page Number */
512 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
514 ret = genphy_update_link(phydev);
518 return m88e1xxx_parse_status(phydev);
521 /* Marvell 88E1121R */
522 static int m88e1121_config(struct phy_device *phydev)
526 marvell_of_reg_init(phydev);
528 /* Configure the PHY */
529 genphy_config_aneg(phydev);
531 /* Switch the page to access the led register */
532 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
533 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
534 MIIM_88E1121_PHY_LED_PAGE);
536 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
537 MIIM_88E1121_PHY_LED_DEF);
538 /* Restore the page pointer */
539 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
541 /* Disable IRQs and de-assert interrupt */
542 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
543 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
548 /* Marvell 88E1145 */
549 static int m88e1145_config(struct phy_device *phydev)
554 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
555 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
556 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
557 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
559 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
560 MIIM_88E1xxx_PHY_MDI_X_AUTO);
562 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
563 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
564 reg |= MIIM_M88E1145_RGMII_RX_DELAY |
565 MIIM_M88E1145_RGMII_TX_DELAY;
566 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
568 marvell_of_reg_init(phydev);
570 genphy_config_aneg(phydev);
573 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
575 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
580 static int m88e1145_startup(struct phy_device *phydev)
584 ret = genphy_update_link(phydev);
588 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
589 MIIM_88E1145_PHY_LED_DIRECT);
590 return m88e1xxx_parse_status(phydev);
593 /* Marvell 88E1149S */
594 static int m88e1149_config(struct phy_device *phydev)
596 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
597 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
598 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
599 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
600 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
602 marvell_of_reg_init(phydev);
604 genphy_config_aneg(phydev);
611 /* Marvell 88E1240 */
612 static int m88e1240_config(struct phy_device *phydev)
614 marvell_of_reg_init(phydev);
616 genphy_config_aneg(phydev);
621 /* Marvell 88E1310 */
622 static int m88e1310_config(struct phy_device *phydev)
626 /* LED link and activity */
627 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
628 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
629 reg = (reg & ~0xf) | 0x1;
630 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
632 /* Set LED2/INT to INT mode, low active */
633 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
634 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
635 reg = (reg & 0x77ff) | 0x0880;
636 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
638 /* Set RGMII delay */
639 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
640 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
642 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
644 /* Ensure to return to page 0 */
645 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
647 marvell_of_reg_init(phydev);
649 return genphy_config_aneg(phydev);
652 static int m88e1680_config(struct phy_device *phydev)
655 * As per Marvell Release Notes - Alaska V 88E1680 Rev A2
661 /* Matrix LED mode (not neede if single LED mode is used */
662 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004);
663 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27);
665 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg);
667 /* QSGMII TX amplitude change */
668 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd);
669 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53);
670 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d);
671 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
673 /* EEE initialization */
674 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff);
675 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030);
676 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c);
677 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc);
678 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c);
679 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c);
680 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
681 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
683 marvell_of_reg_init(phydev);
685 res = genphy_config_aneg(phydev);
690 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
692 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
697 U_BOOT_PHY_DRIVER(m88e1011s) = {
698 .name = "Marvell 88E1011S",
699 .uid = MARVELL_PHY_ID_88E1101,
700 .mask = MARVELL_PHY_ID_MASK,
701 .features = PHY_GBIT_FEATURES,
702 .config = &m88e1011s_config,
703 .startup = &m88e1011s_startup,
704 .shutdown = &genphy_shutdown,
707 U_BOOT_PHY_DRIVER(m88e1111s) = {
708 .name = "Marvell 88E1111S",
709 .uid = MARVELL_PHY_ID_88E1111,
710 .mask = MARVELL_PHY_ID_MASK,
711 .features = PHY_GBIT_FEATURES,
712 .config = &m88e1111s_config,
713 .startup = &m88e1011s_startup,
714 .shutdown = &genphy_shutdown,
717 U_BOOT_PHY_DRIVER(m88e1118) = {
718 .name = "Marvell 88E1118",
719 .uid = MARVELL_PHY_ID_88E1118,
720 .mask = MARVELL_PHY_ID_MASK,
721 .features = PHY_GBIT_FEATURES,
722 .config = &m88e1118_config,
723 .startup = &m88e1118_startup,
724 .shutdown = &genphy_shutdown,
727 U_BOOT_PHY_DRIVER(m88e1118r) = {
728 .name = "Marvell 88E1118R",
729 .uid = MARVELL_PHY_ID_88E1116R,
730 .mask = MARVELL_PHY_ID_MASK,
731 .features = PHY_GBIT_FEATURES,
732 .config = &m88e1118_config,
733 .startup = &m88e1118_startup,
734 .shutdown = &genphy_shutdown,
737 U_BOOT_PHY_DRIVER(m88e1121r) = {
738 .name = "Marvell 88E1121R",
739 .uid = MARVELL_PHY_ID_88E1121R,
740 .mask = MARVELL_PHY_ID_MASK,
741 .features = PHY_GBIT_FEATURES,
742 .config = &m88e1121_config,
743 .startup = &genphy_startup,
744 .shutdown = &genphy_shutdown,
747 U_BOOT_PHY_DRIVER(m88e1145) = {
748 .name = "Marvell 88E1145",
749 .uid = MARVELL_PHY_ID_88E1145,
750 .mask = MARVELL_PHY_ID_MASK,
751 .features = PHY_GBIT_FEATURES,
752 .config = &m88e1145_config,
753 .startup = &m88e1145_startup,
754 .shutdown = &genphy_shutdown,
757 U_BOOT_PHY_DRIVER(m88e1149s) = {
758 .name = "Marvell 88E1149S",
760 .mask = MARVELL_PHY_ID_MASK,
761 .features = PHY_GBIT_FEATURES,
762 .config = &m88e1149_config,
763 .startup = &m88e1011s_startup,
764 .shutdown = &genphy_shutdown,
767 U_BOOT_PHY_DRIVER(m88e1240) = {
768 .name = "Marvell 88E1240",
769 .uid = MARVELL_PHY_ID_88E1240,
770 .mask = MARVELL_PHY_ID_MASK,
771 .features = PHY_GBIT_FEATURES,
772 .config = &m88e1240_config,
773 .startup = &m88e1011s_startup,
774 .shutdown = &genphy_shutdown,
777 U_BOOT_PHY_DRIVER(m88e151x) = {
778 .name = "Marvell 88E151x",
779 .uid = MARVELL_PHY_ID_88E1510,
780 .mask = MARVELL_PHY_ID_MASK,
781 .features = PHY_GBIT_FEATURES,
782 .config = &m88e151x_config,
783 .startup = &m88e1011s_startup,
784 .shutdown = &genphy_shutdown,
785 .readext = &m88e1xxx_phy_extread,
786 .writeext = &m88e1xxx_phy_extwrite,
789 U_BOOT_PHY_DRIVER(m88e1310) = {
790 .name = "Marvell 88E1310",
791 .uid = MARVELL_PHY_ID_88E1318S,
792 .mask = MARVELL_PHY_ID_MASK,
793 .features = PHY_GBIT_FEATURES,
794 .config = &m88e1310_config,
795 .startup = &m88e1011s_startup,
796 .shutdown = &genphy_shutdown,
799 U_BOOT_PHY_DRIVER(m88e1680) = {
800 .name = "Marvell 88E1680",
802 .mask = MARVELL_PHY_ID_MASK,
803 .features = PHY_GBIT_FEATURES,
804 .config = &m88e1680_config,
805 .startup = &genphy_startup,
806 .shutdown = &genphy_shutdown,