1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/compat.h>
13 #include <dt-bindings/net/ti-dp83867.h>
17 #define DP83867_DEVADDR 0x1f
19 #define MII_DP83867_PHYCTRL 0x10
20 #define MII_DP83867_MICR 0x12
21 #define MII_DP83867_CFG2 0x14
22 #define MII_DP83867_BISCR 0x16
23 #define DP83867_CTRL 0x1f
25 /* Extended Registers */
26 #define DP83867_CFG4 0x0031
27 #define DP83867_RGMIICTL 0x0032
28 #define DP83867_STRAP_STS1 0x006E
29 #define DP83867_STRAP_STS2 0x006f
30 #define DP83867_RGMIIDCTL 0x0086
31 #define DP83867_IO_MUX_CFG 0x0170
33 #define DP83867_SW_RESET BIT(15)
34 #define DP83867_SW_RESTART BIT(14)
36 /* MICR Interrupt bits */
37 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
38 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
39 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
40 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
41 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
42 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
43 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
44 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
45 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
46 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
47 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
48 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
51 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
52 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
55 #define DP83867_STRAP_STS1_RESERVED BIT(11)
58 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
59 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
60 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
61 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
62 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
65 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
66 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
67 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
68 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
69 #define DP83867_MDI_CROSSOVER 5
70 #define DP83867_MDI_CROSSOVER_MDIX 2
71 #define DP83867_PHYCTRL_SGMIIEN 0x0800
72 #define DP83867_PHYCTRL_RXFIFO_SHIFT 12
73 #define DP83867_PHYCTRL_TXFIFO_SHIFT 14
76 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
77 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
78 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
81 #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
82 #define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
83 #define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
84 #define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
85 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
86 #define MII_DP83867_CFG2_MASK 0x003F
88 /* User setting - can be taken from DTS */
89 #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
92 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
94 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
95 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
96 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
97 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
98 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
99 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
102 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
105 DP83867_PORT_MIRRORING_KEEP,
106 DP83867_PORT_MIRRORING_EN,
107 DP83867_PORT_MIRRORING_DIS,
110 struct dp83867_private {
115 bool rxctrl_strap_quirk;
118 unsigned int clk_output_sel;
121 static int dp83867_config_port_mirroring(struct phy_device *phydev)
123 struct dp83867_private *dp83867 =
124 (struct dp83867_private *)phydev->priv;
127 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
129 if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
130 val |= DP83867_CFG4_PORT_MIRROR_EN;
132 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
134 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
139 #if defined(CONFIG_DM_ETH)
141 * dp83867_data_init - Convenience function for setting PHY specific data
143 * @phydev: the phy_device struct
145 static int dp83867_of_init(struct phy_device *phydev)
147 struct dp83867_private *dp83867 = phydev->priv;
151 node = phy_get_ofnode(phydev);
152 if (!ofnode_valid(node))
155 /* Optional configuration */
156 ret = ofnode_read_u32(node, "ti,clk-output-sel",
157 &dp83867->clk_output_sel);
158 /* If not set, keep default */
160 dp83867->set_clk_output = true;
161 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
162 * DP83867_CLK_O_SEL_OFF.
164 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
165 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
166 pr_debug("ti,clk-output-sel value %u out of range\n",
167 dp83867->clk_output_sel);
172 if (ofnode_read_bool(node, "ti,max-output-impedance"))
173 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
174 else if (ofnode_read_bool(node, "ti,min-output-impedance"))
175 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
177 dp83867->io_impedance = -EINVAL;
179 if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
180 dp83867->rxctrl_strap_quirk = true;
182 /* Existing behavior was to use default pin strapping delay in rgmii
183 * mode, but rgmii should have meant no delay. Warn existing users.
185 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
186 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
188 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
189 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
190 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
191 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
193 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
194 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
195 pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
196 "Should be 'rgmii-id' to use internal delays\n");
199 /* RX delay *must* be specified if internal delay of RX is used. */
200 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
201 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
202 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
203 &dp83867->rx_id_delay);
205 pr_debug("ti,rx-internal-delay must be specified\n");
208 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
209 pr_debug("ti,rx-internal-delay value of %u out of range\n",
210 dp83867->rx_id_delay);
215 /* TX delay *must* be specified if internal delay of RX is used. */
216 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
217 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
218 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
219 &dp83867->tx_id_delay);
221 debug("ti,tx-internal-delay must be specified\n");
224 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
225 pr_debug("ti,tx-internal-delay value of %u out of range\n",
226 dp83867->tx_id_delay);
231 dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
233 if (ofnode_read_bool(node, "enet-phy-lane-swap"))
234 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
236 if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
237 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
242 static int dp83867_of_init(struct phy_device *phydev)
244 struct dp83867_private *dp83867 = phydev->priv;
246 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
247 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
248 dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
249 dp83867->io_impedance = -EINVAL;
255 static int dp83867_config(struct phy_device *phydev)
257 struct dp83867_private *dp83867;
258 unsigned int val, delay, cfg2;
261 dp83867 = (struct dp83867_private *)phydev->priv;
263 ret = dp83867_of_init(phydev);
267 /* Restart the PHY. */
268 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
269 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
270 val | DP83867_SW_RESTART);
272 /* Mode 1 or 2 workaround */
273 if (dp83867->rxctrl_strap_quirk) {
274 val = phy_read_mmd(phydev, DP83867_DEVADDR,
277 phy_write_mmd(phydev, DP83867_DEVADDR,
281 if (phy_interface_is_rgmii(phydev)) {
282 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
285 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
286 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
288 /* Do not force link good */
289 val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
291 /* The code below checks if "port mirroring" N/A MODE4 has been
292 * enabled during power on bootstrap.
294 * Such N/A mode enabled by mistake can put PHY IC in some
295 * internal testing mode and disable RGMII transmission.
297 * In this particular case one needs to check STRAP_STS1
298 * register's bit 11 (marked as RESERVED).
301 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
302 if (bs & DP83867_STRAP_STS1_RESERVED)
303 val &= ~DP83867_PHYCR_RESERVED_MASK;
305 ret = phy_write(phydev, MDIO_DEVAD_NONE,
306 MII_DP83867_PHYCTRL, val);
308 val = phy_read_mmd(phydev, DP83867_DEVADDR,
311 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
312 DP83867_RGMII_RX_CLK_DELAY_EN);
313 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
314 val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
315 DP83867_RGMII_RX_CLK_DELAY_EN);
317 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
318 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
320 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
321 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
323 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
325 delay = (dp83867->rx_id_delay |
326 (dp83867->tx_id_delay <<
327 DP83867_RGMII_TX_CLK_DELAY_SHIFT));
329 phy_write_mmd(phydev, DP83867_DEVADDR,
330 DP83867_RGMIIDCTL, delay);
333 if (phy_interface_is_sgmii(phydev)) {
334 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
335 (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
337 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
338 cfg2 &= MII_DP83867_CFG2_MASK;
339 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
340 MII_DP83867_CFG2_SGMII_AUTONEGEN |
341 MII_DP83867_CFG2_SPEEDOPT_ENH |
342 MII_DP83867_CFG2_SPEEDOPT_CNT |
343 MII_DP83867_CFG2_SPEEDOPT_INTLOW);
344 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
346 phy_write_mmd(phydev, DP83867_DEVADDR,
347 DP83867_RGMIICTL, 0x0);
349 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
350 DP83867_PHYCTRL_SGMIIEN |
351 (DP83867_MDI_CROSSOVER_MDIX <<
352 DP83867_MDI_CROSSOVER) |
353 (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
354 (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
355 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
358 if (dp83867->io_impedance >= 0) {
359 val = phy_read_mmd(phydev,
362 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
363 val |= dp83867->io_impedance &
364 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
365 phy_write_mmd(phydev, DP83867_DEVADDR,
366 DP83867_IO_MUX_CFG, val);
369 if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
370 dp83867_config_port_mirroring(phydev);
372 /* Clock output selection if muxing property is set */
373 if (dp83867->set_clk_output) {
374 val = phy_read_mmd(phydev, DP83867_DEVADDR,
377 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
378 val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
380 val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
381 DP83867_IO_MUX_CFG_CLK_O_DISABLE);
382 val |= dp83867->clk_output_sel <<
383 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
385 phy_write_mmd(phydev, DP83867_DEVADDR,
386 DP83867_IO_MUX_CFG, val);
389 genphy_config_aneg(phydev);
396 static int dp83867_probe(struct phy_device *phydev)
398 struct dp83867_private *dp83867;
400 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
404 phydev->priv = dp83867;
408 static struct phy_driver DP83867_driver = {
409 .name = "TI DP83867",
412 .features = PHY_GBIT_FEATURES,
413 .probe = dp83867_probe,
414 .config = &dp83867_config,
415 .startup = &genphy_startup,
416 .shutdown = &genphy_shutdown,
419 int phy_ti_init(void)
421 phy_register(&DP83867_driver);