1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/compat.h>
12 #include <dt-bindings/net/ti-dp83867.h>
16 #define DP83867_DEVADDR 0x1f
18 #define MII_DP83867_PHYCTRL 0x10
19 #define MII_DP83867_MICR 0x12
20 #define MII_DP83867_CFG2 0x14
21 #define MII_DP83867_BISCR 0x16
22 #define DP83867_CTRL 0x1f
24 /* Extended Registers */
25 #define DP83867_CFG4 0x0031
26 #define DP83867_RGMIICTL 0x0032
27 #define DP83867_STRAP_STS1 0x006E
28 #define DP83867_STRAP_STS2 0x006f
29 #define DP83867_RGMIIDCTL 0x0086
30 #define DP83867_IO_MUX_CFG 0x0170
32 #define DP83867_SW_RESET BIT(15)
33 #define DP83867_SW_RESTART BIT(14)
35 /* MICR Interrupt bits */
36 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
37 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
38 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
39 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
40 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
41 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
42 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
43 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
44 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
45 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
46 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
47 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
50 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
51 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
54 #define DP83867_STRAP_STS1_RESERVED BIT(11)
57 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
58 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
59 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
60 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
61 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
64 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
65 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
66 #define DP83867_MDI_CROSSOVER 5
67 #define DP83867_MDI_CROSSOVER_AUTO 2
68 #define DP83867_MDI_CROSSOVER_MDIX 2
69 #define DP83867_PHYCTRL_SGMIIEN 0x0800
70 #define DP83867_PHYCTRL_RXFIFO_SHIFT 12
71 #define DP83867_PHYCTRL_TXFIFO_SHIFT 14
74 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
75 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
76 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
79 #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
80 #define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
81 #define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
82 #define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
83 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
84 #define MII_DP83867_CFG2_MASK 0x003F
86 /* User setting - can be taken from DTS */
87 #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
90 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
92 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
93 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
94 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
95 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
96 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
97 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
100 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
103 DP83867_PORT_MIRRORING_KEEP,
104 DP83867_PORT_MIRRORING_EN,
105 DP83867_PORT_MIRRORING_DIS,
108 struct dp83867_private {
113 bool rxctrl_strap_quirk;
116 unsigned int clk_output_sel;
119 static int dp83867_config_port_mirroring(struct phy_device *phydev)
121 struct dp83867_private *dp83867 =
122 (struct dp83867_private *)phydev->priv;
125 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
127 if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
128 val |= DP83867_CFG4_PORT_MIRROR_EN;
130 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
132 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
137 #if defined(CONFIG_DM_ETH)
139 * dp83867_data_init - Convenience function for setting PHY specific data
141 * @phydev: the phy_device struct
143 static int dp83867_of_init(struct phy_device *phydev)
145 struct dp83867_private *dp83867 = phydev->priv;
149 node = phy_get_ofnode(phydev);
150 if (!ofnode_valid(node))
153 /* Optional configuration */
154 ret = ofnode_read_u32(node, "ti,clk-output-sel",
155 &dp83867->clk_output_sel);
156 /* If not set, keep default */
158 dp83867->set_clk_output = true;
159 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
160 * DP83867_CLK_O_SEL_OFF.
162 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
163 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
164 pr_debug("ti,clk-output-sel value %u out of range\n",
165 dp83867->clk_output_sel);
170 if (ofnode_read_bool(node, "ti,max-output-impedance"))
171 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
172 else if (ofnode_read_bool(node, "ti,min-output-impedance"))
173 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
175 dp83867->io_impedance = -EINVAL;
177 if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
178 dp83867->rxctrl_strap_quirk = true;
180 /* Existing behavior was to use default pin strapping delay in rgmii
181 * mode, but rgmii should have meant no delay. Warn existing users.
183 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
184 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
186 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
187 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
188 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
189 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
191 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
192 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
193 pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
194 "Should be 'rgmii-id' to use internal delays\n");
197 /* RX delay *must* be specified if internal delay of RX is used. */
198 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
199 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
200 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
201 &dp83867->rx_id_delay);
203 pr_debug("ti,rx-internal-delay must be specified\n");
206 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
207 pr_debug("ti,rx-internal-delay value of %u out of range\n",
208 dp83867->rx_id_delay);
213 /* TX delay *must* be specified if internal delay of RX is used. */
214 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
215 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
216 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
217 &dp83867->tx_id_delay);
219 debug("ti,tx-internal-delay must be specified\n");
222 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
223 pr_debug("ti,tx-internal-delay value of %u out of range\n",
224 dp83867->tx_id_delay);
229 dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
231 if (ofnode_read_bool(node, "enet-phy-lane-swap"))
232 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
234 if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
235 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
240 static int dp83867_of_init(struct phy_device *phydev)
242 struct dp83867_private *dp83867 = phydev->priv;
244 dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
245 dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
246 dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
247 dp83867->io_impedance = -EINVAL;
253 static int dp83867_config(struct phy_device *phydev)
255 struct dp83867_private *dp83867;
256 unsigned int val, delay, cfg2;
259 dp83867 = (struct dp83867_private *)phydev->priv;
261 ret = dp83867_of_init(phydev);
265 /* Restart the PHY. */
266 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
267 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
268 val | DP83867_SW_RESTART);
270 /* Mode 1 or 2 workaround */
271 if (dp83867->rxctrl_strap_quirk) {
272 val = phy_read_mmd(phydev, DP83867_DEVADDR,
275 phy_write_mmd(phydev, DP83867_DEVADDR,
279 if (phy_interface_is_rgmii(phydev)) {
280 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
281 (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
282 (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
286 /* The code below checks if "port mirroring" N/A MODE4 has been
287 * enabled during power on bootstrap.
289 * Such N/A mode enabled by mistake can put PHY IC in some
290 * internal testing mode and disable RGMII transmission.
292 * In this particular case one needs to check STRAP_STS1
293 * register's bit 11 (marked as RESERVED).
296 bs = phy_read_mmd(phydev, DP83867_DEVADDR,
298 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
299 if (bs & DP83867_STRAP_STS1_RESERVED) {
300 val &= ~DP83867_PHYCR_RESERVED_MASK;
301 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
305 } else if (phy_interface_is_sgmii(phydev)) {
306 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
307 (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
309 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
310 cfg2 &= MII_DP83867_CFG2_MASK;
311 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
312 MII_DP83867_CFG2_SGMII_AUTONEGEN |
313 MII_DP83867_CFG2_SPEEDOPT_ENH |
314 MII_DP83867_CFG2_SPEEDOPT_CNT |
315 MII_DP83867_CFG2_SPEEDOPT_INTLOW);
316 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
318 phy_write_mmd(phydev, DP83867_DEVADDR,
319 DP83867_RGMIICTL, 0x0);
321 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
322 DP83867_PHYCTRL_SGMIIEN |
323 (DP83867_MDI_CROSSOVER_MDIX <<
324 DP83867_MDI_CROSSOVER) |
325 (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
326 (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
327 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
330 if (phy_interface_is_rgmii(phydev)) {
331 val = phy_read_mmd(phydev, DP83867_DEVADDR,
334 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
335 DP83867_RGMII_RX_CLK_DELAY_EN);
336 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
337 val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
338 DP83867_RGMII_RX_CLK_DELAY_EN);
340 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
341 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
343 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
344 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
346 phy_write_mmd(phydev, DP83867_DEVADDR,
347 DP83867_RGMIICTL, val);
349 delay = (dp83867->rx_id_delay |
350 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
352 phy_write_mmd(phydev, DP83867_DEVADDR,
353 DP83867_RGMIIDCTL, delay);
356 if (dp83867->io_impedance >= 0) {
357 val = phy_read_mmd(phydev,
360 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
361 val |= dp83867->io_impedance &
362 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
363 phy_write_mmd(phydev, DP83867_DEVADDR,
364 DP83867_IO_MUX_CFG, val);
367 if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
368 dp83867_config_port_mirroring(phydev);
370 /* Clock output selection if muxing property is set */
371 if (dp83867->set_clk_output) {
372 val = phy_read_mmd(phydev, DP83867_DEVADDR,
375 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
376 val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
378 val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
379 DP83867_IO_MUX_CFG_CLK_O_DISABLE);
380 val |= dp83867->clk_output_sel <<
381 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
383 phy_write_mmd(phydev, DP83867_DEVADDR,
384 DP83867_IO_MUX_CFG, val);
387 genphy_config_aneg(phydev);
394 static int dp83867_probe(struct phy_device *phydev)
396 struct dp83867_private *dp83867;
398 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
402 phydev->priv = dp83867;
406 static struct phy_driver DP83867_driver = {
407 .name = "TI DP83867",
410 .features = PHY_GBIT_FEATURES,
411 .probe = dp83867_probe,
412 .config = &dp83867_config,
413 .startup = &genphy_startup,
414 .shutdown = &genphy_shutdown,
417 int phy_ti_init(void)
419 phy_register(&DP83867_driver);