drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI PHY drivers
   4  *
   5  */
   6 #include <common.h>
   7 #include <log.h>
   8 #include <phy.h>
   9 #include <dm/devres.h>
  10 #include <linux/bitops.h>
  11 #include <linux/compat.h>
  12 #include <malloc.h>
  13
  14 #include <dm.h>
  15 #include <dt-bindings/net/ti-dp83867.h>
  16
  17 #include "ti_phy_init.h"
  18
  19 /* TI DP83867 */
  20 #define DP83867_DEVADDR         0x1f
  21
  22 #define MII_DP83867_PHYCTRL     0x10
  23 #define MII_DP83867_MICR        0x12
  24 #define MII_DP83867_CFG2        0x14
  25 #define MII_DP83867_BISCR       0x16
  26 #define DP83867_CTRL            0x1f
  27
  28 /* Extended Registers */
  29 #define DP83867_CFG4            0x0031
  30 #define DP83867_RGMIICTL        0x0032
  31 #define DP83867_STRAP_STS1      0x006E
  32 #define DP83867_STRAP_STS2      0x006f
  33 #define DP83867_RGMIIDCTL       0x0086
  34 #define DP83867_IO_MUX_CFG      0x0170
  35 #define DP83867_SGMIICTL        0x00D3
  36
  37 #define DP83867_SW_RESET        BIT(15)
  38 #define DP83867_SW_RESTART      BIT(14)
  39
  40 /* MICR Interrupt bits */
  41 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  42 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  43 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  44 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  45 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  46 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  47 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  48 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  49 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  50 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  51 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  52 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  53
  54 /* RGMIICTL bits */
  55 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  56 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  57
  58 /* STRAP_STS1 bits */
  59 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  60
  61 /* STRAP_STS2 bits */
  62 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  63 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  64 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  65 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  66 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  67
  68 /* PHY CTRL bits */
  69 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  70 #define DP83867_PHYCR_FIFO_DEPTH_MASK           GENMASK(15, 14)
  71 #define DP83867_PHYCR_RESERVED_MASK     BIT(11)
  72 #define DP83867_PHYCR_FORCE_LINK_GOOD   BIT(10)
  73 #define DP83867_MDI_CROSSOVER           5
  74 #define DP83867_MDI_CROSSOVER_MDIX      2
  75 #define DP83867_PHYCTRL_SGMIIEN                 0x0800
  76 #define DP83867_PHYCTRL_RXFIFO_SHIFT    12
  77 #define DP83867_PHYCTRL_TXFIFO_SHIFT    14
  78
  79 /* RGMIIDCTL bits */
  80 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
  81 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  82 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
  83
  84 /* CFG2 bits */
  85 #define MII_DP83867_CFG2_SPEEDOPT_10EN          0x0040
  86 #define MII_DP83867_CFG2_SGMII_AUTONEGEN        0x0080
  87 #define MII_DP83867_CFG2_SPEEDOPT_ENH           0x0100
  88 #define MII_DP83867_CFG2_SPEEDOPT_CNT           0x0800
  89 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW        0x2000
  90 #define MII_DP83867_CFG2_MASK                   0x003F
  91
  92 /* User setting - can be taken from DTS */
  93 #define DEFAULT_FIFO_DEPTH      DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  94
  95 /* IO_MUX_CFG bits */
  96 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  97
  98 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  99 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
 100 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
 101 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 102 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       \
 103                 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
 104
 105 /* CFG4 bits */
 106 #define DP83867_CFG4_PORT_MIRROR_EN             BIT(0)
 107
 108 /* SGMIICTL bits */
 109 #define DP83867_SGMII_TYPE                      BIT(14)
 110
 111 enum {
 112         DP83867_PORT_MIRRORING_KEEP,
 113         DP83867_PORT_MIRRORING_EN,
 114         DP83867_PORT_MIRRORING_DIS,
 115 };
 116
 117 struct dp83867_private {
 118         u32 rx_id_delay;
 119         u32 tx_id_delay;
 120         int fifo_depth;
 121         int io_impedance;
 122         bool rxctrl_strap_quirk;
 123         int port_mirroring;
 124         bool set_clk_output;
 125         unsigned int clk_output_sel;
 126         bool sgmii_ref_clk_en;
 127 };
 128
 129 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 130 {
 131         struct dp83867_private *dp83867 =
 132                 (struct dp83867_private *)phydev->priv;
 133         u16 val;
 134
 135         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 136
 137         if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
 138                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 139         else
 140                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 141
 142         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 143
 144         return 0;
 145 }
 146
 147 #if defined(CONFIG_DM_ETH)
 148 /**
 149  * dp83867_data_init - Convenience function for setting PHY specific data
 150  *
 151  * @phydev: the phy_device struct
 152  */
 153 static int dp83867_of_init(struct phy_device *phydev)
 154 {
 155         struct dp83867_private *dp83867 = phydev->priv;
 156         ofnode node;
 157         int ret;
 158
 159         node = phy_get_ofnode(phydev);
 160         if (!ofnode_valid(node))
 161                 return -EINVAL;
 162
 163         /* Optional configuration */
 164         ret = ofnode_read_u32(node, "ti,clk-output-sel",
 165                               &dp83867->clk_output_sel);
 166         /* If not set, keep default */
 167         if (!ret) {
 168                 dp83867->set_clk_output = true;
 169                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 170                  * DP83867_CLK_O_SEL_OFF.
 171                  */
 172                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 173                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 174                         pr_debug("ti,clk-output-sel value %u out of range\n",
 175                                  dp83867->clk_output_sel);
 176                         return -EINVAL;
 177                 }
 178         }
 179
 180         if (ofnode_read_bool(node, "ti,max-output-impedance"))
 181                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 182         else if (ofnode_read_bool(node, "ti,min-output-impedance"))
 183                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 184         else
 185                 dp83867->io_impedance = -EINVAL;
 186
 187         if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
 188                 dp83867->rxctrl_strap_quirk = true;
 189
 190         /* Existing behavior was to use default pin strapping delay in rgmii
 191          * mode, but rgmii should have meant no delay.  Warn existing users.
 192          */
 193         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 194                 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 195                                        DP83867_STRAP_STS2);
 196                 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 197                              DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 198                 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 199                              DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 200
 201                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 202                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 203                         pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 204                                 "Should be 'rgmii-id' to use internal delays\n");
 205         }
 206
 207         /* RX delay *must* be specified if internal delay of RX is used. */
 208         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 209             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 210                 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
 211                                       &dp83867->rx_id_delay);
 212                 if (ret) {
 213                         pr_debug("ti,rx-internal-delay must be specified\n");
 214                         return ret;
 215                 }
 216                 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 217                         pr_debug("ti,rx-internal-delay value of %u out of range\n",
 218                                  dp83867->rx_id_delay);
 219                         return -EINVAL;
 220                 }
 221         }
 222
 223         /* TX delay *must* be specified if internal delay of RX is used. */
 224         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 225             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 226                 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
 227                                       &dp83867->tx_id_delay);
 228                 if (ret) {
 229                         debug("ti,tx-internal-delay must be specified\n");
 230                         return ret;
 231                 }
 232                 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 233                         pr_debug("ti,tx-internal-delay value of %u out of range\n",
 234                                  dp83867->tx_id_delay);
 235                         return -EINVAL;
 236                 }
 237         }
 238
 239         dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
 240                                                       DEFAULT_FIFO_DEPTH);
 241         if (ofnode_read_bool(node, "enet-phy-lane-swap"))
 242                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
 243
 244         if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 245                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 246
 247         if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
 248                 dp83867->sgmii_ref_clk_en = true;
 249
 250         return 0;
 251 }
 252 #else
 253 static int dp83867_of_init(struct phy_device *phydev)
 254 {
 255         struct dp83867_private *dp83867 = phydev->priv;
 256
 257         dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
 258         dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
 259         dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
 260         dp83867->io_impedance = -EINVAL;
 261
 262         return 0;
 263 }
 264 #endif
 265
 266 static int dp83867_config(struct phy_device *phydev)
 267 {
 268         struct dp83867_private *dp83867;
 269         unsigned int val, delay, cfg2;
 270         int ret, bs;
 271
 272         dp83867 = (struct dp83867_private *)phydev->priv;
 273
 274         ret = dp83867_of_init(phydev);
 275         if (ret)
 276                 return ret;
 277
 278         /* Restart the PHY.  */
 279         val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 280         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 281                   val | DP83867_SW_RESTART);
 282
 283         /* Mode 1 or 2 workaround */
 284         if (dp83867->rxctrl_strap_quirk) {
 285                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 286                                    DP83867_CFG4);
 287                 val &= ~BIT(7);
 288                 phy_write_mmd(phydev, DP83867_DEVADDR,
 289                               DP83867_CFG4, val);
 290         }
 291
 292         if (phy_interface_is_rgmii(phydev)) {
 293                 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
 294                 if (val < 0)
 295                         goto err_out;
 296                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 297                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 298
 299                 /* Do not force link good */
 300                 val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
 301
 302                 /* The code below checks if "port mirroring" N/A MODE4 has been
 303                  * enabled during power on bootstrap.
 304                  *
 305                  * Such N/A mode enabled by mistake can put PHY IC in some
 306                  * internal testing mode and disable RGMII transmission.
 307                  *
 308                  * In this particular case one needs to check STRAP_STS1
 309                  * register's bit 11 (marked as RESERVED).
 310                  */
 311
 312                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 313                 if (bs & DP83867_STRAP_STS1_RESERVED)
 314                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 315
 316                 ret = phy_write(phydev, MDIO_DEVAD_NONE,
 317                                 MII_DP83867_PHYCTRL, val);
 318
 319                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 320                                    DP83867_RGMIICTL);
 321
 322                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
 323                          DP83867_RGMII_RX_CLK_DELAY_EN);
 324                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 325                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
 326                                 DP83867_RGMII_RX_CLK_DELAY_EN);
 327
 328                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 329                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 330
 331                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 332                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 333
 334                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 335
 336                 delay = (dp83867->rx_id_delay |
 337                         (dp83867->tx_id_delay <<
 338                         DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 339
 340                 phy_write_mmd(phydev, DP83867_DEVADDR,
 341                               DP83867_RGMIIDCTL, delay);
 342         }
 343
 344         if (phy_interface_is_sgmii(phydev)) {
 345                 if (dp83867->sgmii_ref_clk_en)
 346                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
 347                                       DP83867_SGMII_TYPE);
 348
 349                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 350                           (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 351
 352                 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
 353                 cfg2 &= MII_DP83867_CFG2_MASK;
 354                 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
 355                          MII_DP83867_CFG2_SGMII_AUTONEGEN |
 356                          MII_DP83867_CFG2_SPEEDOPT_ENH |
 357                          MII_DP83867_CFG2_SPEEDOPT_CNT |
 358                          MII_DP83867_CFG2_SPEEDOPT_INTLOW);
 359                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
 360
 361                 phy_write_mmd(phydev, DP83867_DEVADDR,
 362                               DP83867_RGMIICTL, 0x0);
 363
 364                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 365                           DP83867_PHYCTRL_SGMIIEN |
 366                           (DP83867_MDI_CROSSOVER_MDIX <<
 367                           DP83867_MDI_CROSSOVER) |
 368                           (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
 369                           (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 370                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 371         }
 372
 373         if (dp83867->io_impedance >= 0) {
 374                 val = phy_read_mmd(phydev,
 375                                    DP83867_DEVADDR,
 376                                    DP83867_IO_MUX_CFG);
 377                 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 378                 val |= dp83867->io_impedance &
 379                        DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 380                 phy_write_mmd(phydev, DP83867_DEVADDR,
 381                               DP83867_IO_MUX_CFG, val);
 382         }
 383
 384         if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
 385                 dp83867_config_port_mirroring(phydev);
 386
 387         /* Clock output selection if muxing property is set */
 388         if (dp83867->set_clk_output) {
 389                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 390                                    DP83867_IO_MUX_CFG);
 391
 392                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 393                         val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 394                 } else {
 395                         val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
 396                                  DP83867_IO_MUX_CFG_CLK_O_DISABLE);
 397                         val |= dp83867->clk_output_sel <<
 398                                DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 399                 }
 400                 phy_write_mmd(phydev, DP83867_DEVADDR,
 401                               DP83867_IO_MUX_CFG, val);
 402         }
 403
 404         genphy_config_aneg(phydev);
 405         return 0;
 406
 407 err_out:
 408         return ret;
 409 }
 410
 411 static int dp83867_probe(struct phy_device *phydev)
 412 {
 413         struct dp83867_private *dp83867;
 414
 415         dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
 416         if (!dp83867)
 417                 return -ENOMEM;
 418
 419         phydev->priv = dp83867;
 420         return 0;
 421 }
 422
 423 static struct phy_driver DP83867_driver = {
 424         .name = "TI DP83867",
 425         .uid = 0x2000a231,
 426         .mask = 0xfffffff0,
 427         .features = PHY_GBIT_FEATURES,
 428         .probe = dp83867_probe,
 429         .config = &dp83867_config,
 430         .startup = &genphy_startup,
 431         .shutdown = &genphy_shutdown,
 432 };
 433
 434 int phy_dp83867_init(void)
 435 {
 436         phy_register(&DP83867_driver);
 437         return 0;
 438 }