drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI PHY drivers
   4  *
   5  */
   6 #include <common.h>
   7 #include <log.h>
   8 #include <phy.h>
   9 #include <dm/devres.h>
  10 #include <linux/bitops.h>
  11 #include <linux/compat.h>
  12 #include <malloc.h>
  13
  14 #include <dm.h>
  15 #include <dt-bindings/net/ti-dp83867.h>
  16
  17
  18 /* TI DP83867 */
  19 #define DP83867_DEVADDR         0x1f
  20
  21 #define MII_DP83867_PHYCTRL     0x10
  22 #define MII_DP83867_MICR        0x12
  23 #define MII_DP83867_CFG2        0x14
  24 #define MII_DP83867_BISCR       0x16
  25 #define DP83867_CTRL            0x1f
  26
  27 /* Extended Registers */
  28 #define DP83867_CFG4            0x0031
  29 #define DP83867_RGMIICTL        0x0032
  30 #define DP83867_STRAP_STS1      0x006E
  31 #define DP83867_STRAP_STS2      0x006f
  32 #define DP83867_RGMIIDCTL       0x0086
  33 #define DP83867_IO_MUX_CFG      0x0170
  34 #define DP83867_SGMIICTL        0x00D3
  35
  36 #define DP83867_SW_RESET        BIT(15)
  37 #define DP83867_SW_RESTART      BIT(14)
  38
  39 /* MICR Interrupt bits */
  40 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  41 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  42 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  43 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  44 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  45 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  46 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  47 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  48 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  49 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  50 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  51 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  52
  53 /* RGMIICTL bits */
  54 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  55 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  56
  57 /* STRAP_STS1 bits */
  58 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  59
  60 /* STRAP_STS2 bits */
  61 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  62 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  63 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  64 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  65 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  66
  67 /* PHY CTRL bits */
  68 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  69 #define DP83867_PHYCR_FIFO_DEPTH_MASK           GENMASK(15, 14)
  70 #define DP83867_PHYCR_RESERVED_MASK     BIT(11)
  71 #define DP83867_PHYCR_FORCE_LINK_GOOD   BIT(10)
  72 #define DP83867_MDI_CROSSOVER           5
  73 #define DP83867_MDI_CROSSOVER_MDIX      2
  74 #define DP83867_PHYCTRL_SGMIIEN                 0x0800
  75 #define DP83867_PHYCTRL_RXFIFO_SHIFT    12
  76 #define DP83867_PHYCTRL_TXFIFO_SHIFT    14
  77
  78 /* RGMIIDCTL bits */
  79 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
  80 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  81 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
  82
  83 /* CFG2 bits */
  84 #define MII_DP83867_CFG2_SPEEDOPT_10EN          0x0040
  85 #define MII_DP83867_CFG2_SGMII_AUTONEGEN        0x0080
  86 #define MII_DP83867_CFG2_SPEEDOPT_ENH           0x0100
  87 #define MII_DP83867_CFG2_SPEEDOPT_CNT           0x0800
  88 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW        0x2000
  89 #define MII_DP83867_CFG2_MASK                   0x003F
  90
  91 /* User setting - can be taken from DTS */
  92 #define DEFAULT_FIFO_DEPTH      DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  93
  94 /* IO_MUX_CFG bits */
  95 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  96
  97 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  98 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  99 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
 100 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 101 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       \
 102                 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
 103
 104 /* CFG4 bits */
 105 #define DP83867_CFG4_PORT_MIRROR_EN             BIT(0)
 106
 107 /* SGMIICTL bits */
 108 #define DP83867_SGMII_TYPE                      BIT(14)
 109
 110 enum {
 111         DP83867_PORT_MIRRORING_KEEP,
 112         DP83867_PORT_MIRRORING_EN,
 113         DP83867_PORT_MIRRORING_DIS,
 114 };
 115
 116 struct dp83867_private {
 117         u32 rx_id_delay;
 118         u32 tx_id_delay;
 119         int fifo_depth;
 120         int io_impedance;
 121         bool rxctrl_strap_quirk;
 122         int port_mirroring;
 123         bool set_clk_output;
 124         unsigned int clk_output_sel;
 125         bool sgmii_ref_clk_en;
 126 };
 127
 128 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 129 {
 130         struct dp83867_private *dp83867 =
 131                 (struct dp83867_private *)phydev->priv;
 132         u16 val;
 133
 134         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 135
 136         if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
 137                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 138         else
 139                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 140
 141         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 142
 143         return 0;
 144 }
 145
 146 #if defined(CONFIG_DM_ETH)
 147 /**
 148  * dp83867_data_init - Convenience function for setting PHY specific data
 149  *
 150  * @phydev: the phy_device struct
 151  */
 152 static int dp83867_of_init(struct phy_device *phydev)
 153 {
 154         struct dp83867_private *dp83867 = phydev->priv;
 155         ofnode node;
 156         int ret;
 157
 158         node = phy_get_ofnode(phydev);
 159         if (!ofnode_valid(node))
 160                 return -EINVAL;
 161
 162         /* Optional configuration */
 163         ret = ofnode_read_u32(node, "ti,clk-output-sel",
 164                               &dp83867->clk_output_sel);
 165         /* If not set, keep default */
 166         if (!ret) {
 167                 dp83867->set_clk_output = true;
 168                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 169                  * DP83867_CLK_O_SEL_OFF.
 170                  */
 171                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 172                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 173                         pr_debug("ti,clk-output-sel value %u out of range\n",
 174                                  dp83867->clk_output_sel);
 175                         return -EINVAL;
 176                 }
 177         }
 178
 179         if (ofnode_read_bool(node, "ti,max-output-impedance"))
 180                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 181         else if (ofnode_read_bool(node, "ti,min-output-impedance"))
 182                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 183         else
 184                 dp83867->io_impedance = -EINVAL;
 185
 186         if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
 187                 dp83867->rxctrl_strap_quirk = true;
 188
 189         /* Existing behavior was to use default pin strapping delay in rgmii
 190          * mode, but rgmii should have meant no delay.  Warn existing users.
 191          */
 192         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 193                 u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 194                                        DP83867_STRAP_STS2);
 195                 u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 196                              DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 197                 u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 198                              DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 199
 200                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 201                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 202                         pr_warn("PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 203                                 "Should be 'rgmii-id' to use internal delays\n");
 204         }
 205
 206         /* RX delay *must* be specified if internal delay of RX is used. */
 207         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 208             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 209                 ret = ofnode_read_u32(node, "ti,rx-internal-delay",
 210                                       &dp83867->rx_id_delay);
 211                 if (ret) {
 212                         pr_debug("ti,rx-internal-delay must be specified\n");
 213                         return ret;
 214                 }
 215                 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 216                         pr_debug("ti,rx-internal-delay value of %u out of range\n",
 217                                  dp83867->rx_id_delay);
 218                         return -EINVAL;
 219                 }
 220         }
 221
 222         /* TX delay *must* be specified if internal delay of RX is used. */
 223         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 224             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 225                 ret = ofnode_read_u32(node, "ti,tx-internal-delay",
 226                                       &dp83867->tx_id_delay);
 227                 if (ret) {
 228                         debug("ti,tx-internal-delay must be specified\n");
 229                         return ret;
 230                 }
 231                 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 232                         pr_debug("ti,tx-internal-delay value of %u out of range\n",
 233                                  dp83867->tx_id_delay);
 234                         return -EINVAL;
 235                 }
 236         }
 237
 238         dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
 239                                                       DEFAULT_FIFO_DEPTH);
 240         if (ofnode_read_bool(node, "enet-phy-lane-swap"))
 241                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
 242
 243         if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 244                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 245
 246         if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
 247                 dp83867->sgmii_ref_clk_en = true;
 248
 249         return 0;
 250 }
 251 #else
 252 static int dp83867_of_init(struct phy_device *phydev)
 253 {
 254         struct dp83867_private *dp83867 = phydev->priv;
 255
 256         dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
 257         dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
 258         dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
 259         dp83867->io_impedance = -EINVAL;
 260
 261         return 0;
 262 }
 263 #endif
 264
 265 static int dp83867_config(struct phy_device *phydev)
 266 {
 267         struct dp83867_private *dp83867;
 268         unsigned int val, delay, cfg2;
 269         int ret, bs;
 270
 271         dp83867 = (struct dp83867_private *)phydev->priv;
 272
 273         ret = dp83867_of_init(phydev);
 274         if (ret)
 275                 return ret;
 276
 277         /* Restart the PHY.  */
 278         val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 279         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 280                   val | DP83867_SW_RESTART);
 281
 282         /* Mode 1 or 2 workaround */
 283         if (dp83867->rxctrl_strap_quirk) {
 284                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 285                                    DP83867_CFG4);
 286                 val &= ~BIT(7);
 287                 phy_write_mmd(phydev, DP83867_DEVADDR,
 288                               DP83867_CFG4, val);
 289         }
 290
 291         if (phy_interface_is_rgmii(phydev)) {
 292                 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
 293                 if (val < 0)
 294                         goto err_out;
 295                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 296                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 297
 298                 /* Do not force link good */
 299                 val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
 300
 301                 /* The code below checks if "port mirroring" N/A MODE4 has been
 302                  * enabled during power on bootstrap.
 303                  *
 304                  * Such N/A mode enabled by mistake can put PHY IC in some
 305                  * internal testing mode and disable RGMII transmission.
 306                  *
 307                  * In this particular case one needs to check STRAP_STS1
 308                  * register's bit 11 (marked as RESERVED).
 309                  */
 310
 311                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 312                 if (bs & DP83867_STRAP_STS1_RESERVED)
 313                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 314
 315                 ret = phy_write(phydev, MDIO_DEVAD_NONE,
 316                                 MII_DP83867_PHYCTRL, val);
 317
 318                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 319                                    DP83867_RGMIICTL);
 320
 321                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN |
 322                          DP83867_RGMII_RX_CLK_DELAY_EN);
 323                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 324                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
 325                                 DP83867_RGMII_RX_CLK_DELAY_EN);
 326
 327                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 328                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 329
 330                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 331                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 332
 333                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 334
 335                 delay = (dp83867->rx_id_delay |
 336                         (dp83867->tx_id_delay <<
 337                         DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 338
 339                 phy_write_mmd(phydev, DP83867_DEVADDR,
 340                               DP83867_RGMIIDCTL, delay);
 341         }
 342
 343         if (phy_interface_is_sgmii(phydev)) {
 344                 if (dp83867->sgmii_ref_clk_en)
 345                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
 346                                       DP83867_SGMII_TYPE);
 347
 348                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 349                           (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 350
 351                 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
 352                 cfg2 &= MII_DP83867_CFG2_MASK;
 353                 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
 354                          MII_DP83867_CFG2_SGMII_AUTONEGEN |
 355                          MII_DP83867_CFG2_SPEEDOPT_ENH |
 356                          MII_DP83867_CFG2_SPEEDOPT_CNT |
 357                          MII_DP83867_CFG2_SPEEDOPT_INTLOW);
 358                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
 359
 360                 phy_write_mmd(phydev, DP83867_DEVADDR,
 361                               DP83867_RGMIICTL, 0x0);
 362
 363                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 364                           DP83867_PHYCTRL_SGMIIEN |
 365                           (DP83867_MDI_CROSSOVER_MDIX <<
 366                           DP83867_MDI_CROSSOVER) |
 367                           (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
 368                           (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 369                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 370         }
 371
 372         if (dp83867->io_impedance >= 0) {
 373                 val = phy_read_mmd(phydev,
 374                                    DP83867_DEVADDR,
 375                                    DP83867_IO_MUX_CFG);
 376                 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 377                 val |= dp83867->io_impedance &
 378                        DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 379                 phy_write_mmd(phydev, DP83867_DEVADDR,
 380                               DP83867_IO_MUX_CFG, val);
 381         }
 382
 383         if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
 384                 dp83867_config_port_mirroring(phydev);
 385
 386         /* Clock output selection if muxing property is set */
 387         if (dp83867->set_clk_output) {
 388                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 389                                    DP83867_IO_MUX_CFG);
 390
 391                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 392                         val |= DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 393                 } else {
 394                         val &= ~(DP83867_IO_MUX_CFG_CLK_O_SEL_MASK |
 395                                  DP83867_IO_MUX_CFG_CLK_O_DISABLE);
 396                         val |= dp83867->clk_output_sel <<
 397                                DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 398                 }
 399                 phy_write_mmd(phydev, DP83867_DEVADDR,
 400                               DP83867_IO_MUX_CFG, val);
 401         }
 402
 403         genphy_config_aneg(phydev);
 404         return 0;
 405
 406 err_out:
 407         return ret;
 408 }
 409
 410 static int dp83867_probe(struct phy_device *phydev)
 411 {
 412         struct dp83867_private *dp83867;
 413
 414         dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
 415         if (!dp83867)
 416                 return -ENOMEM;
 417
 418         phydev->priv = dp83867;
 419         return 0;
 420 }
 421
 422 static struct phy_driver DP83867_driver = {
 423         .name = "TI DP83867",
 424         .uid = 0x2000a231,
 425         .mask = 0xfffffff0,
 426         .features = PHY_GBIT_FEATURES,
 427         .probe = dp83867_probe,
 428         .config = &dp83867_config,
 429         .startup = &genphy_startup,
 430         .shutdown = &genphy_shutdown,
 431 };
 432
 433 int phy_ti_init(void)
 434 {
 435         phy_register(&DP83867_driver);
 436         return 0;
 437 }