drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI PHY drivers
   4  *
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <linux/compat.h>
   9 #include <malloc.h>
  10
  11 #include <dm.h>
  12 #include <dt-bindings/net/ti-dp83867.h>
  13
  14
  15 /* TI DP83867 */
  16 #define DP83867_DEVADDR         0x1f
  17
  18 #define MII_DP83867_PHYCTRL     0x10
  19 #define MII_DP83867_MICR        0x12
  20 #define MII_DP83867_CFG2        0x14
  21 #define MII_DP83867_BISCR       0x16
  22 #define DP83867_CTRL            0x1f
  23
  24 /* Extended Registers */
  25 #define DP83867_CFG4            0x0031
  26 #define DP83867_RGMIICTL        0x0032
  27 #define DP83867_STRAP_STS1      0x006E
  28 #define DP83867_RGMIIDCTL       0x0086
  29 #define DP83867_IO_MUX_CFG      0x0170
  30
  31 #define DP83867_SW_RESET        BIT(15)
  32 #define DP83867_SW_RESTART      BIT(14)
  33
  34 /* MICR Interrupt bits */
  35 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  36 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  37 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  38 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  39 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  40 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  41 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  42 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  43 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  44 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  45 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  46 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  47
  48 /* RGMIICTL bits */
  49 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  50 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  51
  52 /* STRAP_STS1 bits */
  53 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  54
  55 /* PHY CTRL bits */
  56 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  57 #define DP83867_PHYCR_RESERVED_MASK     BIT(11)
  58 #define DP83867_MDI_CROSSOVER           5
  59 #define DP83867_MDI_CROSSOVER_AUTO      2
  60 #define DP83867_MDI_CROSSOVER_MDIX      2
  61 #define DP83867_PHYCTRL_SGMIIEN                 0x0800
  62 #define DP83867_PHYCTRL_RXFIFO_SHIFT    12
  63 #define DP83867_PHYCTRL_TXFIFO_SHIFT    14
  64
  65 /* RGMIIDCTL bits */
  66 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  67
  68 /* CFG2 bits */
  69 #define MII_DP83867_CFG2_SPEEDOPT_10EN          0x0040
  70 #define MII_DP83867_CFG2_SGMII_AUTONEGEN        0x0080
  71 #define MII_DP83867_CFG2_SPEEDOPT_ENH           0x0100
  72 #define MII_DP83867_CFG2_SPEEDOPT_CNT           0x0800
  73 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW        0x2000
  74 #define MII_DP83867_CFG2_MASK                   0x003F
  75
  76 /* User setting - can be taken from DTS */
  77 #define DEFAULT_RX_ID_DELAY     DP83867_RGMIIDCTL_2_25_NS
  78 #define DEFAULT_TX_ID_DELAY     DP83867_RGMIIDCTL_2_75_NS
  79 #define DEFAULT_FIFO_DEPTH      DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  80
  81 /* IO_MUX_CFG bits */
  82 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  83
  84 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  85 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  86 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  87 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       \
  88                 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
  89
  90 /* CFG4 bits */
  91 #define DP83867_CFG4_PORT_MIRROR_EN             BIT(0)
  92
  93 enum {
  94         DP83867_PORT_MIRRORING_KEEP,
  95         DP83867_PORT_MIRRORING_EN,
  96         DP83867_PORT_MIRRORING_DIS,
  97 };
  98
  99 struct dp83867_private {
 100         int rx_id_delay;
 101         int tx_id_delay;
 102         int fifo_depth;
 103         int io_impedance;
 104         bool rxctrl_strap_quirk;
 105         int port_mirroring;
 106         unsigned int clk_output_sel;
 107 };
 108
 109 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 110 {
 111         struct dp83867_private *dp83867 =
 112                 (struct dp83867_private *)phydev->priv;
 113         u16 val;
 114
 115         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 116
 117         if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
 118                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 119         else
 120                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 121
 122         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 123
 124         return 0;
 125 }
 126
 127 #if defined(CONFIG_DM_ETH)
 128 /**
 129  * dp83867_data_init - Convenience function for setting PHY specific data
 130  *
 131  * @phydev: the phy_device struct
 132  */
 133 static int dp83867_of_init(struct phy_device *phydev)
 134 {
 135         struct dp83867_private *dp83867 = phydev->priv;
 136         ofnode node;
 137         u16 val;
 138
 139         node = phy_get_ofnode(phydev);
 140         if (!ofnode_valid(node))
 141                 return -EINVAL;
 142
 143         /* Keep the default value if ti,clk-output-sel is not set */
 144         dp83867->clk_output_sel =
 145                 ofnode_read_u32_default(node, "ti,clk-output-sel",
 146                                         DP83867_CLK_O_SEL_REF_CLK);
 147
 148         if (ofnode_read_bool(node, "ti,max-output-impedance"))
 149                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 150         else if (ofnode_read_bool(node, "ti,min-output-impedance"))
 151                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 152         else
 153                 dp83867->io_impedance = -EINVAL;
 154
 155         if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
 156                 dp83867->rxctrl_strap_quirk = true;
 157         dp83867->rx_id_delay = ofnode_read_u32_default(node,
 158                                                        "ti,rx-internal-delay",
 159                                                        DEFAULT_RX_ID_DELAY);
 160
 161         dp83867->tx_id_delay = ofnode_read_u32_default(node,
 162                                                        "ti,tx-internal-delay",
 163                                                        DEFAULT_TX_ID_DELAY);
 164
 165         dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
 166                                                       DEFAULT_FIFO_DEPTH);
 167         if (ofnode_read_bool(node, "enet-phy-lane-swap"))
 168                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
 169
 170         if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 171                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 172
 173
 174         /* Clock output selection if muxing property is set */
 175         if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
 176                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 177                                    DP83867_IO_MUX_CFG);
 178                 val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 179                 val |= (dp83867->clk_output_sel <<
 180                         DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 181                 phy_write_mmd(phydev, DP83867_DEVADDR,
 182                               DP83867_IO_MUX_CFG, val);
 183         }
 184
 185         return 0;
 186 }
 187 #else
 188 static int dp83867_of_init(struct phy_device *phydev)
 189 {
 190         struct dp83867_private *dp83867 = phydev->priv;
 191
 192         dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
 193         dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
 194         dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
 195         dp83867->io_impedance = -EINVAL;
 196
 197         return 0;
 198 }
 199 #endif
 200
 201 static int dp83867_config(struct phy_device *phydev)
 202 {
 203         struct dp83867_private *dp83867;
 204         unsigned int val, delay, cfg2;
 205         int ret, bs;
 206
 207         dp83867 = (struct dp83867_private *)phydev->priv;
 208
 209         ret = dp83867_of_init(phydev);
 210         if (ret)
 211                 return ret;
 212
 213         /* Restart the PHY.  */
 214         val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 215         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 216                   val | DP83867_SW_RESTART);
 217
 218         /* Mode 1 or 2 workaround */
 219         if (dp83867->rxctrl_strap_quirk) {
 220                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 221                                    DP83867_CFG4);
 222                 val &= ~BIT(7);
 223                 phy_write_mmd(phydev, DP83867_DEVADDR,
 224                               DP83867_CFG4, val);
 225         }
 226
 227         if (phy_interface_is_rgmii(phydev)) {
 228                 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 229                         (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
 230                         (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 231                 if (ret)
 232                         goto err_out;
 233
 234                 /* The code below checks if "port mirroring" N/A MODE4 has been
 235                  * enabled during power on bootstrap.
 236                  *
 237                  * Such N/A mode enabled by mistake can put PHY IC in some
 238                  * internal testing mode and disable RGMII transmission.
 239                  *
 240                  * In this particular case one needs to check STRAP_STS1
 241                  * register's bit 11 (marked as RESERVED).
 242                  */
 243
 244                 bs = phy_read_mmd(phydev, DP83867_DEVADDR,
 245                                   DP83867_STRAP_STS1);
 246                 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
 247                 if (bs & DP83867_STRAP_STS1_RESERVED) {
 248                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 249                         phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 250                                   val);
 251                 }
 252
 253         } else if (phy_interface_is_sgmii(phydev)) {
 254                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 255                           (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 256
 257                 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
 258                 cfg2 &= MII_DP83867_CFG2_MASK;
 259                 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
 260                          MII_DP83867_CFG2_SGMII_AUTONEGEN |
 261                          MII_DP83867_CFG2_SPEEDOPT_ENH |
 262                          MII_DP83867_CFG2_SPEEDOPT_CNT |
 263                          MII_DP83867_CFG2_SPEEDOPT_INTLOW);
 264                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
 265
 266                 phy_write_mmd(phydev, DP83867_DEVADDR,
 267                               DP83867_RGMIICTL, 0x0);
 268
 269                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 270                           DP83867_PHYCTRL_SGMIIEN |
 271                           (DP83867_MDI_CROSSOVER_MDIX <<
 272                           DP83867_MDI_CROSSOVER) |
 273                           (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
 274                           (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 275                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 276         }
 277
 278         if (phy_interface_is_rgmii(phydev)) {
 279                 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 280                                    DP83867_RGMIICTL);
 281
 282                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 283                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
 284                                 DP83867_RGMII_RX_CLK_DELAY_EN);
 285
 286                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 287                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 288
 289                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 290                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 291
 292                 phy_write_mmd(phydev, DP83867_DEVADDR,
 293                               DP83867_RGMIICTL, val);
 294
 295                 delay = (dp83867->rx_id_delay |
 296                          (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 297
 298                 phy_write_mmd(phydev, DP83867_DEVADDR,
 299                               DP83867_RGMIIDCTL, delay);
 300
 301                 if (dp83867->io_impedance >= 0) {
 302                         val = phy_read_mmd(phydev,
 303                                            DP83867_DEVADDR,
 304                                            DP83867_IO_MUX_CFG);
 305                         val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 306                         val |= dp83867->io_impedance &
 307                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 308                         phy_write_mmd(phydev, DP83867_DEVADDR,
 309                                       DP83867_IO_MUX_CFG, val);
 310                 }
 311         }
 312
 313         if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
 314                 dp83867_config_port_mirroring(phydev);
 315
 316         genphy_config_aneg(phydev);
 317         return 0;
 318
 319 err_out:
 320         return ret;
 321 }
 322
 323 static int dp83867_probe(struct phy_device *phydev)
 324 {
 325         struct dp83867_private *dp83867;
 326
 327         dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
 328         if (!dp83867)
 329                 return -ENOMEM;
 330
 331         phydev->priv = dp83867;
 332         return 0;
 333 }
 334
 335 static struct phy_driver DP83867_driver = {
 336         .name = "TI DP83867",
 337         .uid = 0x2000a231,
 338         .mask = 0xfffffff0,
 339         .features = PHY_GBIT_FEATURES,
 340         .probe = dp83867_probe,
 341         .config = &dp83867_config,
 342         .startup = &genphy_startup,
 343         .shutdown = &genphy_shutdown,
 344 };
 345
 346 int phy_ti_init(void)
 347 {
 348         phy_register(&DP83867_driver);
 349         return 0;
 350 }