drivers/net/phy/cortina.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cortina CS4315/CS4340 10G PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018, 2020 NXP
   7  *
   8  */
   9
  10 #include <config.h>
  11 #include <common.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <linux/ctype.h>
  15 #include <linux/delay.h>
  16 #include <linux/string.h>
  17 #include <linux/err.h>
  18 #include <phy.h>
  19 #include <cortina.h>
  20 #include <nand.h>
  21 #include <spi_flash.h>
  22 #include <mmc.h>
  23 #ifdef CONFIG_ARM64
  24 #include <asm/arch/cpu.h>
  25 #endif
  26
  27 #ifndef CONFIG_PHYLIB_10G
  28 #error The Cortina PHY needs 10G support
  29 #endif
  30
  31 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
  32 struct cortina_reg_config cortina_reg_cfg[] = {
  33         /* CS4315_enable_sr_mode */
  34         {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  35         {VILLA_MSEQ_OPTIONS, 0xf},
  36         {VILLA_MSEQ_PC, 0x0},
  37         {VILLA_MSEQ_BANKSELECT,    0x4},
  38         {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
  39         {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
  40         {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
  41         {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
  42         {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
  43         {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
  44         {VILLA_MSEQ_ENABLE_MSB, 0x0000},
  45         {VILLA_MSEQ_SPARE21_LSB, 0x6},
  46         {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
  47         {VILLA_MSEQ_SPARE12_MSB, 0x0000},
  48         /*
  49          * to invert the receiver path, uncomment the next line
  50          * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
  51          *
  52          * SPARE2_LSB is used to configure the device while in sr mode to
  53          * enable power savings and to use the optical module LOS signal.
  54          * in power savings mode, the internal prbs checker can not be used.
  55          * if the optical module LOS signal is used as an input to the micro
  56          * code, then the micro code will wait until the optical module
  57          * LOS = 0 before turning on the adaptive equalizer.
  58          * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
  59          * while setting bit 0 to 0 disables power savings mode.
  60          * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
  61          * optical module LOS signal while setting bit 2 to 1 configures the
  62          * device so that it will ignore the optical module LOS SPARE2_LSB = 0
  63          */
  64
  65         /* enable power savings, ignore optical module LOS */
  66         {VILLA_MSEQ_SPARE2_LSB, 0x5},
  67
  68         {VILLA_MSEQ_SPARE7_LSB, 0x1e},
  69         {VILLA_MSEQ_BANKSELECT, 0x4},
  70         {VILLA_MSEQ_SPARE9_LSB, 0x2},
  71         {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
  72         {VILLA_MSEQ_SPARE3_MSB, 0x2006},
  73         {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
  74         {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
  75         {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
  76         {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
  77         {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
  78         {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
  79         {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
  80         {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
  81         {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
  82         {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
  83         {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
  84         {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
  85         {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
  86         {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
  87         {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
  88         {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
  89         {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
  90         {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
  91         {VILLA_MSEQ_OPTIONS, 0x7},
  92
  93         /* set up min value for ffe1 */
  94         {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
  95         {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
  96
  97         /* CS4315_sr_rx_pre_eq_set_4in */
  98         {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  99         {VILLA_MSEQ_OPTIONS, 0xf},
 100         {VILLA_MSEQ_BANKSELECT, 0x4},
 101         {VILLA_MSEQ_PC, 0x0},
 102
 103         /* for lengths from 3.5 to 4.5inches */
 104         {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
 105         {VILLA_MSEQ_SPARE25_LSB, 0x0306},
 106         {VILLA_MSEQ_SPARE21_LSB, 0x2},
 107         {VILLA_MSEQ_SPARE23_LSB, 0x2},
 108         {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
 109
 110         {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
 111         {VILLA_MSEQ_OPTIONS, 0x7},
 112
 113         /* CS4315_rx_drive_4inch */
 114         /* for length  4inches */
 115         {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
 116         {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
 117         {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
 118
 119         /* CS4315_tx_drive_4inch */
 120         /* for length  4inches */
 121         {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
 122         {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
 123         {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
 124 };
 125
 126 __weak ulong *cs4340_get_fw_addr(void)
 127 {
 128         return (ulong *)CONFIG_CORTINA_FW_ADDR;
 129 }
 130
 131 void cs4340_upload_firmware(struct phy_device *phydev)
 132 {
 133         char line_temp[0x50] = {0};
 134         char reg_addr[0x50] = {0};
 135         char reg_data[0x50] = {0};
 136         int i, line_cnt = 0, column_cnt = 0;
 137         struct cortina_reg_config fw_temp;
 138         char *addr = NULL;
 139         ulong cortina_fw_addr = (ulong)cs4340_get_fw_addr();
 140
 141 #ifdef CONFIG_TFABOOT
 142         enum boot_src src = get_boot_src();
 143
 144         if (src == BOOT_SOURCE_IFC_NOR) {
 145                 addr = (char *)cortina_fw_addr;
 146         } else if (src == BOOT_SOURCE_IFC_NAND) {
 147                 int ret;
 148                 size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
 149
 150                 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 151                 ret = nand_read(get_nand_dev_by_index(0),
 152                                            (loff_t)cortina_fw_addr,     &fw_length, (u_char *)addr);
 153                 if (ret == -EUCLEAN) {
 154                         printf("NAND read of Cortina firmware at 0x%lx failed %d\n",
 155                                    cortina_fw_addr, ret);
 156                 }
 157         } else if (src == BOOT_SOURCE_QSPI_NOR) {
 158                 int ret;
 159                 struct spi_flash *ucode_flash;
 160
 161                 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 162                 ucode_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
 163                                                                          CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
 164                 if (!ucode_flash) {
 165                         puts("SF: probe for Cortina ucode failed\n");
 166                 } else {
 167                         ret = spi_flash_read(ucode_flash, cortina_fw_addr,
 168                                                                 CONFIG_CORTINA_FW_LENGTH, addr);
 169                         if (ret)
 170                                 puts("SF: read for Cortina ucode failed\n");
 171                         spi_flash_free(ucode_flash);
 172                 }
 173         } else if (src == BOOT_SOURCE_SD_MMC) {
 174                 int dev = CONFIG_SYS_MMC_ENV_DEV;
 175                 u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
 176                 u32 blk = cortina_fw_addr / 512;
 177                 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
 178
 179                 if (!mmc) {
 180                         puts("Failed to find MMC device for Cortina ucode\n");
 181                 } else {
 182                         addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 183                         printf("MMC read: dev # %u, block # %u, count %u ...\n",
 184                                   dev, blk, cnt);
 185                         mmc_init(mmc);
 186 #ifdef CONFIG_BLK
 187                         (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
 188 #else
 189                         (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr);
 190 #endif
 191                 }
 192         }
 193 #else /* CONFIG_TFABOOT */
 194 #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
 195         defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
 196
 197         addr = (char *)cortina_fw_addr;
 198 #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
 199         int ret;
 200         size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
 201
 202         addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 203         ret = nand_read(get_nand_dev_by_index(0),
 204                         (loff_t)cortina_fw_addr,
 205                         &fw_length, (u_char *)addr);
 206         if (ret == -EUCLEAN) {
 207                 printf("NAND read of Cortina firmware at 0x%lx failed %d\n",
 208                        cortina_fw_addr, ret);
 209         }
 210 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
 211         int ret;
 212         struct spi_flash *ucode_flash;
 213
 214         addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 215         ucode_flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
 216                                 CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
 217         if (!ucode_flash) {
 218                 puts("SF: probe for Cortina ucode failed\n");
 219         } else {
 220                 ret = spi_flash_read(ucode_flash, cortina_fw_addr,
 221                                      CONFIG_CORTINA_FW_LENGTH, addr);
 222                 if (ret)
 223                         puts("SF: read for Cortina ucode failed\n");
 224                 spi_flash_free(ucode_flash);
 225         }
 226 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
 227         int dev = CONFIG_SYS_MMC_ENV_DEV;
 228         u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
 229         u32 blk = cortina_fw_addr / 512;
 230         struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
 231
 232         if (!mmc) {
 233                 puts("Failed to find MMC device for Cortina ucode\n");
 234         } else {
 235                 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
 236                 printf("MMC read: dev # %u, block # %u, count %u ...\n",
 237                        dev, blk, cnt);
 238                 mmc_init(mmc);
 239 #ifdef CONFIG_BLK
 240                 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
 241                                                 addr);
 242 #else
 243                 (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
 244                                                 addr);
 245 #endif
 246         }
 247 #endif
 248 #endif
 249
 250         while (*addr != 'Q') {
 251                 i = 0;
 252
 253                 while (*addr != 0x0a) {
 254                         line_temp[i++] = *addr++;
 255                         if (0x50 < i) {
 256                                 printf("Not found Cortina PHY ucode at 0x%p\n",
 257                                        (char *)cortina_fw_addr);
 258                                 return;
 259                         }
 260                 }
 261
 262                 addr++;  /* skip '\n' */
 263                 line_cnt++;
 264                 column_cnt = i;
 265                 line_temp[column_cnt] = '\0';
 266
 267                 if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
 268                         return;
 269
 270                 for (i = 0; i < column_cnt; i++) {
 271                         if (isspace(line_temp[i++]))
 272                                 break;
 273                 }
 274
 275                 memcpy(reg_addr, line_temp, i);
 276                 memcpy(reg_data, &line_temp[i], column_cnt - i);
 277                 strim(reg_addr);
 278                 strim(reg_data);
 279                 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
 280                 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
 281                                      0xffff;
 282                 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
 283         }
 284 }
 285 #endif
 286
 287 int cs4340_phy_init(struct phy_device *phydev)
 288 {
 289 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
 290         int timeout = 100;  /* 100ms */
 291 #endif
 292         int reg_value;
 293
 294         /*
 295          * Cortina phy has provision to store
 296          * phy firmware in attached dedicated EEPROM.
 297          * Boards designed with EEPROM attached to Cortina
 298          * does not require FW upload.
 299          */
 300 #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
 301         /* step1: BIST test */
 302         phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL,     0x0004);
 303         phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
 304         phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL,    0x0001);
 305         while (--timeout) {
 306                 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
 307                 if (reg_value & mseq_edc_bist_done) {
 308                         if (0 == (reg_value & mseq_edc_bist_fail))
 309                                 break;
 310                 }
 311                 udelay(1000);
 312         }
 313
 314         if (!timeout) {
 315                 printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
 316                 return -1;
 317         }
 318
 319         /* setp2: upload ucode */
 320         cs4340_upload_firmware(phydev);
 321 #endif
 322         reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
 323         if (reg_value) {
 324                 debug("%s checksum status failed.\n", __func__);
 325                 return -1;
 326         }
 327
 328         return 0;
 329 }
 330
 331 int cs4340_config(struct phy_device *phydev)
 332 {
 333         cs4340_phy_init(phydev);
 334         return 0;
 335 }
 336
 337 int cs4340_probe(struct phy_device *phydev)
 338 {
 339         phydev->flags = PHY_FLAG_BROKEN_RESET;
 340         return 0;
 341 }
 342
 343 int cs4340_startup(struct phy_device *phydev)
 344 {
 345         phydev->link = 1;
 346
 347         /* For now just lie and say it's 10G all the time */
 348         phydev->speed = SPEED_10000;
 349         phydev->duplex = DUPLEX_FULL;
 350         return 0;
 351 }
 352
 353 int cs4223_phy_init(struct phy_device *phydev)
 354 {
 355         int reg_value;
 356
 357         reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
 358         if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
 359                 printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
 360                 return -ENOSYS;
 361         }
 362
 363         return 0;
 364 }
 365
 366 int cs4223_config(struct phy_device *phydev)
 367 {
 368         return cs4223_phy_init(phydev);
 369 }
 370
 371 int cs4223_probe(struct phy_device *phydev)
 372 {
 373         phydev->flags = PHY_FLAG_BROKEN_RESET;
 374         return 0;
 375 }
 376
 377 int cs4223_startup(struct phy_device *phydev)
 378 {
 379         phydev->link = 1;
 380         phydev->speed = SPEED_10000;
 381         phydev->duplex = DUPLEX_FULL;
 382         return 0;
 383 }
 384
 385 struct phy_driver cs4340_driver = {
 386         .name = "Cortina CS4315/CS4340",
 387         .uid = PHY_UID_CS4340,
 388         .mask = 0xfffffff0,
 389         .features = PHY_10G_FEATURES,
 390         .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
 391                  MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
 392                  MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
 393         .config = &cs4340_config,
 394         .probe  = &cs4340_probe,
 395         .startup = &cs4340_startup,
 396         .shutdown = &gen10g_shutdown,
 397 };
 398
 399 struct phy_driver cs4223_driver = {
 400         .name = "Cortina CS4223",
 401         .uid = PHY_UID_CS4223,
 402         .mask = 0x0ffff00f,
 403         .features = PHY_10G_FEATURES,
 404         .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
 405                  MDIO_DEVS_AN),
 406         .config = &cs4223_config,
 407         .probe  = &cs4223_probe,
 408         .startup = &cs4223_startup,
 409         .shutdown = &gen10g_shutdown,
 410 };
 411
 412 int phy_cortina_init(void)
 413 {
 414         phy_register(&cs4340_driver);
 415         phy_register(&cs4223_driver);
 416         return 0;
 417 }
 418
 419 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 420 {
 421         int phy_reg;
 422
 423         /* Cortina PHY has non-standard offset of PHY ID registers */
 424         phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
 425         if (phy_reg < 0)
 426                 return -EIO;
 427         *phy_id = (phy_reg & 0xffff) << 16;
 428
 429         phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
 430         if (phy_reg < 0)
 431                 return -EIO;
 432         *phy_id |= (phy_reg & 0xffff);
 433
 434         if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
 435                 return 0;
 436
 437         /*
 438          * If Cortina PHY not detected,
 439          * try generic way to find PHY ID registers
 440          */
 441         phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
 442         if (phy_reg < 0)
 443                 return -EIO;
 444         *phy_id = (phy_reg & 0xffff) << 16;
 445
 446         phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
 447         if (phy_reg < 0)
 448                 return -EIO;
 449         *phy_id |= (phy_reg & 0xffff);
 450
 451         return 0;
 452 }