drivers/net/phy/broadcom.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *      drivers/net/phy/broadcom.c
   4  *
   5  *      Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
   6  *      transceivers.
   7  *
   8  *      Copyright (c) 2006  Maciej W. Rozycki
   9  *
  10  *      Inspired by code written by Amy Fong.
  11  */
  12
  13 #include "bcm-phy-lib.h"
  14 #include <linux/delay.h>
  15 #include <linux/module.h>
  16 #include <linux/phy.h>
  17 #include <linux/brcmphy.h>
  18 #include <linux/of.h>
  19
  20 #define BRCM_PHY_MODEL(phydev) \
  21         ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
  22
  23 #define BRCM_PHY_REV(phydev) \
  24         ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
  25
  26 MODULE_DESCRIPTION("Broadcom PHY driver");
  27 MODULE_AUTHOR("Maciej W. Rozycki");
  28 MODULE_LICENSE("GPL");
  29
  30 struct bcm54xx_phy_priv {
  31         u64     *stats;
  32         struct bcm_ptp_private *ptp;
  33 };
  34
  35 static int bcm54xx_config_clock_delay(struct phy_device *phydev)
  36 {
  37         int rc, val;
  38
  39         /* handling PHY's internal RX clock delay */
  40         val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  41         val |= MII_BCM54XX_AUXCTL_MISC_WREN;
  42         if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
  43             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  44                 /* Disable RGMII RXC-RXD skew */
  45                 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  46         }
  47         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  48             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  49                 /* Enable RGMII RXC-RXD skew */
  50                 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  51         }
  52         rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  53                                   val);
  54         if (rc < 0)
  55                 return rc;
  56
  57         /* handling PHY's internal TX clock delay */
  58         val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
  59         if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
  60             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  61                 /* Disable internal TX clock delay */
  62                 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
  63         }
  64         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  65             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  66                 /* Enable internal TX clock delay */
  67                 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
  68         }
  69         rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
  70         if (rc < 0)
  71                 return rc;
  72
  73         return 0;
  74 }
  75
  76 static int bcm54210e_config_init(struct phy_device *phydev)
  77 {
  78         int val;
  79
  80         bcm54xx_config_clock_delay(phydev);
  81
  82         if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
  83                 val = phy_read(phydev, MII_CTRL1000);
  84                 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
  85                 phy_write(phydev, MII_CTRL1000, val);
  86         }
  87
  88         return 0;
  89 }
  90
  91 static int bcm54213pe_config_init(struct phy_device *phydev)
  92 {
  93         return bcm54210e_config_init(phydev);
  94 }
  95
  96 static int bcm54612e_config_init(struct phy_device *phydev)
  97 {
  98         int reg;
  99
 100         bcm54xx_config_clock_delay(phydev);
 101
 102         /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
 103         if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
 104                 int err;
 105
 106                 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
 107                 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
 108                                         BCM54612E_LED4_CLK125OUT_EN | reg);
 109
 110                 if (err < 0)
 111                         return err;
 112         }
 113
 114         return 0;
 115 }
 116
 117 static int bcm54616s_config_init(struct phy_device *phydev)
 118 {
 119         int rc, val;
 120
 121         if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
 122             phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
 123                 return 0;
 124
 125         /* Ensure proper interface mode is selected. */
 126         /* Disable RGMII mode */
 127         val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
 128         if (val < 0)
 129                 return val;
 130         val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
 131         val |= MII_BCM54XX_AUXCTL_MISC_WREN;
 132         rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
 133                                   val);
 134         if (rc < 0)
 135                 return rc;
 136
 137         /* Select 1000BASE-X register set (primary SerDes) */
 138         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
 139         if (val < 0)
 140                 return val;
 141         val |= BCM54XX_SHD_MODE_1000BX;
 142         rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
 143         if (rc < 0)
 144                 return rc;
 145
 146         /* Power down SerDes interface */
 147         rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
 148         if (rc < 0)
 149                 return rc;
 150
 151         /* Select proper interface mode */
 152         val &= ~BCM54XX_SHD_INTF_SEL_MASK;
 153         val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
 154                 BCM54XX_SHD_INTF_SEL_SGMII :
 155                 BCM54XX_SHD_INTF_SEL_GBIC;
 156         rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
 157         if (rc < 0)
 158                 return rc;
 159
 160         /* Power up SerDes interface */
 161         rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
 162         if (rc < 0)
 163                 return rc;
 164
 165         /* Select copper register set */
 166         val &= ~BCM54XX_SHD_MODE_1000BX;
 167         rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
 168         if (rc < 0)
 169                 return rc;
 170
 171         /* Power up copper interface */
 172         return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
 173 }
 174
 175 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
 176 static int bcm50610_a0_workaround(struct phy_device *phydev)
 177 {
 178         int err;
 179
 180         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
 181                                 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
 182                                 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
 183         if (err < 0)
 184                 return err;
 185
 186         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
 187                                 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
 188         if (err < 0)
 189                 return err;
 190
 191         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
 192                                 MII_BCM54XX_EXP_EXP75_VDACCTRL);
 193         if (err < 0)
 194                 return err;
 195
 196         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
 197                                 MII_BCM54XX_EXP_EXP96_MYST);
 198         if (err < 0)
 199                 return err;
 200
 201         err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
 202                                 MII_BCM54XX_EXP_EXP97_MYST);
 203
 204         return err;
 205 }
 206
 207 static int bcm54xx_phydsp_config(struct phy_device *phydev)
 208 {
 209         int err, err2;
 210
 211         /* Enable the SMDSP clock */
 212         err = bcm54xx_auxctl_write(phydev,
 213                                    MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
 214                                    MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
 215                                    MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
 216         if (err < 0)
 217                 return err;
 218
 219         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 220             BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
 221                 /* Clear bit 9 to fix a phy interop issue. */
 222                 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
 223                                         MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
 224                 if (err < 0)
 225                         goto error;
 226
 227                 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
 228                         err = bcm50610_a0_workaround(phydev);
 229                         if (err < 0)
 230                                 goto error;
 231                 }
 232         }
 233
 234         if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
 235                 int val;
 236
 237                 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
 238                 if (val < 0)
 239                         goto error;
 240
 241                 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
 242                 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
 243         }
 244
 245 error:
 246         /* Disable the SMDSP clock */
 247         err2 = bcm54xx_auxctl_write(phydev,
 248                                     MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
 249                                     MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
 250
 251         /* Return the first error reported. */
 252         return err ? err : err2;
 253 }
 254
 255 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
 256 {
 257         u32 orig;
 258         int val;
 259         bool clk125en = true;
 260
 261         /* Abort if we are using an untested phy. */
 262         if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
 263             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
 264             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
 265             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E &&
 266             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
 267             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811 &&
 268             BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54213PE)
 269                 return;
 270
 271         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
 272         if (val < 0)
 273                 return;
 274
 275         orig = val;
 276
 277         if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 278              BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
 279             BRCM_PHY_REV(phydev) >= 0x3) {
 280                 /*
 281                  * Here, bit 0 _disables_ CLK125 when set.
 282                  * This bit is set by default.
 283                  */
 284                 clk125en = false;
 285         } else {
 286                 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
 287                         if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
 288                                 /* Here, bit 0 _enables_ CLK125 when set */
 289                                 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
 290                         }
 291                         clk125en = false;
 292                 }
 293         }
 294
 295         if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 296                 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
 297         else
 298                 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
 299
 300         if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
 301                 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E ||
 302                     BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
 303                     BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
 304                         val |= BCM54XX_SHD_SCR3_RXCTXC_DIS;
 305                 else
 306                         val |= BCM54XX_SHD_SCR3_TRDDAPD;
 307         }
 308
 309         if (orig != val)
 310                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
 311
 312         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
 313         if (val < 0)
 314                 return;
 315
 316         orig = val;
 317
 318         if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 319                 val |= BCM54XX_SHD_APD_EN;
 320         else
 321                 val &= ~BCM54XX_SHD_APD_EN;
 322
 323         if (orig != val)
 324                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
 325 }
 326
 327 static void bcm54xx_ptp_stop(struct phy_device *phydev)
 328 {
 329         struct bcm54xx_phy_priv *priv = phydev->priv;
 330
 331         if (priv->ptp)
 332                 bcm_ptp_stop(priv->ptp);
 333 }
 334
 335 static void bcm54xx_ptp_config_init(struct phy_device *phydev)
 336 {
 337         struct bcm54xx_phy_priv *priv = phydev->priv;
 338
 339         if (priv->ptp)
 340                 bcm_ptp_config_init(phydev);
 341 }
 342
 343 static int bcm54xx_config_init(struct phy_device *phydev)
 344 {
 345         int reg, err, val;
 346         u32 led_modes[] = {BCM_LED_MULTICOLOR_LINK_ACT,
 347                            BCM_LED_MULTICOLOR_LINK};
 348         struct device_node *np = phydev->mdio.dev.of_node;
 349
 350         reg = phy_read(phydev, MII_BCM54XX_ECR);
 351         if (reg < 0)
 352                 return reg;
 353
 354         /* Mask interrupts globally.  */
 355         reg |= MII_BCM54XX_ECR_IM;
 356         err = phy_write(phydev, MII_BCM54XX_ECR, reg);
 357         if (err < 0)
 358                 return err;
 359
 360         /* Unmask events we are interested in.  */
 361         reg = ~(MII_BCM54XX_INT_DUPLEX |
 362                 MII_BCM54XX_INT_SPEED |
 363                 MII_BCM54XX_INT_LINK);
 364         err = phy_write(phydev, MII_BCM54XX_IMR, reg);
 365         if (err < 0)
 366                 return err;
 367
 368         if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
 369              BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
 370             (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
 371                 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
 372
 373         bcm54xx_adjust_rxrefclk(phydev);
 374
 375         switch (BRCM_PHY_MODEL(phydev)) {
 376         case PHY_ID_BCM50610:
 377         case PHY_ID_BCM50610M:
 378                 err = bcm54xx_config_clock_delay(phydev);
 379                 break;
 380         case PHY_ID_BCM54210E:
 381                 err = bcm54210e_config_init(phydev);
 382                 break;
 383         case PHY_ID_BCM54612E:
 384                 err = bcm54612e_config_init(phydev);
 385                 break;
 386         case PHY_ID_BCM54213PE:
 387                 err = bcm54213pe_config_init(phydev);
 388                 break;
 389         case PHY_ID_BCM54616S:
 390                 err = bcm54616s_config_init(phydev);
 391                 break;
 392         case PHY_ID_BCM54810:
 393                 /* For BCM54810, we need to disable BroadR-Reach function */
 394                 val = bcm_phy_read_exp(phydev,
 395                                        BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
 396                 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
 397                 err = bcm_phy_write_exp(phydev,
 398                                         BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
 399                                         val);
 400                 break;
 401         }
 402         if (err)
 403                 return err;
 404
 405         bcm54xx_phydsp_config(phydev);
 406
 407         of_property_read_u32_array(np, "led-modes", led_modes, 2);
 408
 409         /* For non-SFP setups, encode link speed into LED1 and LED3 pair
 410          * (green/amber).
 411          * Don't do this for devices on an SFP module, since some of these
 412          * use the LED outputs to control the SFP LOS signal, and changing
 413          * these settings will cause LOS to malfunction.
 414          */
 415         if (!phy_on_sfp(phydev)) {
 416                 val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
 417                         BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
 418                 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
 419
 420                 val = BCM_LED_MULTICOLOR_IN_PHASE |
 421                         BCM5482_SHD_LEDS1_LED1(led_modes[0]) |
 422                         BCM5482_SHD_LEDS1_LED3(led_modes[1]);
 423                 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
 424         }
 425
 426         bcm54xx_ptp_config_init(phydev);
 427
 428         return 0;
 429 }
 430
 431 static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable)
 432 {
 433         int ret = 0;
 434
 435         if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND))
 436                 return ret;
 437
 438         ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL);
 439         if (ret < 0)
 440                 goto out;
 441
 442         if (enable)
 443                 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP;
 444         else
 445                 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP);
 446
 447         ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret);
 448 out:
 449         return ret;
 450 }
 451
 452 static int bcm54xx_suspend(struct phy_device *phydev)
 453 {
 454         int ret;
 455
 456         bcm54xx_ptp_stop(phydev);
 457
 458         /* We cannot use a read/modify/write here otherwise the PHY gets into
 459          * a bad state where its LEDs keep flashing, thus defeating the purpose
 460          * of low power mode.
 461          */
 462         ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
 463         if (ret < 0)
 464                 return ret;
 465
 466         return bcm54xx_iddq_set(phydev, true);
 467 }
 468
 469 static int bcm54xx_resume(struct phy_device *phydev)
 470 {
 471         int ret;
 472
 473         ret = bcm54xx_iddq_set(phydev, false);
 474         if (ret < 0)
 475                 return ret;
 476
 477         /* Writes to register other than BMCR would be ignored
 478          * unless we clear the PDOWN bit first
 479          */
 480         ret = genphy_resume(phydev);
 481         if (ret < 0)
 482                 return ret;
 483
 484         /* Upon exiting power down, the PHY remains in an internal reset state
 485          * for 40us
 486          */
 487         fsleep(40);
 488
 489         /* Issue a soft reset after clearing the power down bit
 490          * and before doing any other configuration.
 491          */
 492         if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) {
 493                 ret = genphy_soft_reset(phydev);
 494                 if (ret < 0)
 495                         return ret;
 496         }
 497
 498         return bcm54xx_config_init(phydev);
 499 }
 500
 501 static int bcm54811_config_init(struct phy_device *phydev)
 502 {
 503         int err, reg;
 504
 505         /* Disable BroadR-Reach function. */
 506         reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
 507         reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
 508         err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
 509                                 reg);
 510         if (err < 0)
 511                 return err;
 512
 513         err = bcm54xx_config_init(phydev);
 514
 515         /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
 516         if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
 517                 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
 518                 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
 519                                         BCM54612E_LED4_CLK125OUT_EN | reg);
 520                 if (err < 0)
 521                         return err;
 522         }
 523
 524         return err;
 525 }
 526
 527 static int bcm5481_config_aneg(struct phy_device *phydev)
 528 {
 529         struct device_node *np = phydev->mdio.dev.of_node;
 530         int ret;
 531
 532         /* Aneg firstly. */
 533         ret = genphy_config_aneg(phydev);
 534
 535         /* Then we can set up the delay. */
 536         bcm54xx_config_clock_delay(phydev);
 537
 538         if (of_property_read_bool(np, "enet-phy-lane-swap")) {
 539                 /* Lane Swap - Undocumented register...magic! */
 540                 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
 541                                         0x11B);
 542                 if (ret < 0)
 543                         return ret;
 544         }
 545
 546         return ret;
 547 }
 548
 549 struct bcm54616s_phy_priv {
 550         bool mode_1000bx_en;
 551 };
 552
 553 static int bcm54616s_probe(struct phy_device *phydev)
 554 {
 555         struct bcm54616s_phy_priv *priv;
 556         int val;
 557
 558         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 559         if (!priv)
 560                 return -ENOMEM;
 561
 562         phydev->priv = priv;
 563
 564         val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
 565         if (val < 0)
 566                 return val;
 567
 568         /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
 569          * is 01b, and the link between PHY and its link partner can be
 570          * either 1000Base-X or 100Base-FX.
 571          * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
 572          * support is still missing as of now.
 573          */
 574         if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
 575                 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
 576                 if (val < 0)
 577                         return val;
 578
 579                 /* Bit 0 of the SerDes 100-FX Control register, when set
 580                  * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
 581                  * When this bit is set to 0, it sets the GMII/RGMII ->
 582                  * 1000BASE-X configuration.
 583                  */
 584                 if (!(val & BCM54616S_100FX_MODE))
 585                         priv->mode_1000bx_en = true;
 586
 587                 phydev->port = PORT_FIBRE;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int bcm54616s_config_aneg(struct phy_device *phydev)
 594 {
 595         struct bcm54616s_phy_priv *priv = phydev->priv;
 596         int ret;
 597
 598         /* Aneg firstly. */
 599         if (priv->mode_1000bx_en)
 600                 ret = genphy_c37_config_aneg(phydev);
 601         else
 602                 ret = genphy_config_aneg(phydev);
 603
 604         /* Then we can set up the delay. */
 605         bcm54xx_config_clock_delay(phydev);
 606
 607         return ret;
 608 }
 609
 610 static int bcm54616s_read_status(struct phy_device *phydev)
 611 {
 612         struct bcm54616s_phy_priv *priv = phydev->priv;
 613         int err;
 614
 615         if (priv->mode_1000bx_en)
 616                 err = genphy_c37_read_status(phydev);
 617         else
 618                 err = genphy_read_status(phydev);
 619
 620         return err;
 621 }
 622
 623 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
 624 {
 625         int val;
 626
 627         val = phy_read(phydev, reg);
 628         if (val < 0)
 629                 return val;
 630
 631         return phy_write(phydev, reg, val | set);
 632 }
 633
 634 static int brcm_fet_config_init(struct phy_device *phydev)
 635 {
 636         int reg, err, err2, brcmtest;
 637
 638         /* Reset the PHY to bring it to a known state. */
 639         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 640         if (err < 0)
 641                 return err;
 642
 643         /* The datasheet indicates the PHY needs up to 1us to complete a reset,
 644          * build some slack here.
 645          */
 646         usleep_range(1000, 2000);
 647
 648         /* The PHY requires 65 MDC clock cycles to complete a write operation
 649          * and turnaround the line properly.
 650          *
 651          * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
 652          * may flag the lack of turn-around as a read failure. This is
 653          * particularly true with this combination since the MDIO controller
 654          * only used 64 MDC cycles. This is not a critical failure in this
 655          * specific case and it has no functional impact otherwise, so we let
 656          * that one go through. If there is a genuine bus error, the next read
 657          * of MII_BRCM_FET_INTREG will error out.
 658          */
 659         err = phy_read(phydev, MII_BMCR);
 660         if (err < 0 && err != -EIO)
 661                 return err;
 662
 663         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 664         if (reg < 0)
 665                 return reg;
 666
 667         /* Unmask events we are interested in and mask interrupts globally. */
 668         reg = MII_BRCM_FET_IR_DUPLEX_EN |
 669               MII_BRCM_FET_IR_SPEED_EN |
 670               MII_BRCM_FET_IR_LINK_EN |
 671               MII_BRCM_FET_IR_ENABLE |
 672               MII_BRCM_FET_IR_MASK;
 673
 674         err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 675         if (err < 0)
 676                 return err;
 677
 678         /* Enable shadow register access */
 679         brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
 680         if (brcmtest < 0)
 681                 return brcmtest;
 682
 683         reg = brcmtest | MII_BRCM_FET_BT_SRE;
 684
 685         err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
 686         if (err < 0)
 687                 return err;
 688
 689         /* Set the LED mode */
 690         reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
 691         if (reg < 0) {
 692                 err = reg;
 693                 goto done;
 694         }
 695
 696         reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
 697         reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
 698
 699         err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
 700         if (err < 0)
 701                 goto done;
 702
 703         /* Enable auto MDIX */
 704         err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
 705                                        MII_BRCM_FET_SHDW_MC_FAME);
 706         if (err < 0)
 707                 goto done;
 708
 709         if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
 710                 /* Enable auto power down */
 711                 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
 712                                                MII_BRCM_FET_SHDW_AS2_APDE);
 713         }
 714
 715 done:
 716         /* Disable shadow register access */
 717         err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
 718         if (!err)
 719                 err = err2;
 720
 721         return err;
 722 }
 723
 724 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
 725 {
 726         int reg;
 727
 728         /* Clear pending interrupts.  */
 729         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 730         if (reg < 0)
 731                 return reg;
 732
 733         return 0;
 734 }
 735
 736 static int brcm_fet_config_intr(struct phy_device *phydev)
 737 {
 738         int reg, err;
 739
 740         reg = phy_read(phydev, MII_BRCM_FET_INTREG);
 741         if (reg < 0)
 742                 return reg;
 743
 744         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 745                 err = brcm_fet_ack_interrupt(phydev);
 746                 if (err)
 747                         return err;
 748
 749                 reg &= ~MII_BRCM_FET_IR_MASK;
 750                 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 751         } else {
 752                 reg |= MII_BRCM_FET_IR_MASK;
 753                 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
 754                 if (err)
 755                         return err;
 756
 757                 err = brcm_fet_ack_interrupt(phydev);
 758         }
 759
 760         return err;
 761 }
 762
 763 static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev)
 764 {
 765         int irq_status;
 766
 767         irq_status = phy_read(phydev, MII_BRCM_FET_INTREG);
 768         if (irq_status < 0) {
 769                 phy_error(phydev);
 770                 return IRQ_NONE;
 771         }
 772
 773         if (irq_status == 0)
 774                 return IRQ_NONE;
 775
 776         phy_trigger_machine(phydev);
 777
 778         return IRQ_HANDLED;
 779 }
 780
 781 static int bcm54xx_phy_probe(struct phy_device *phydev)
 782 {
 783         struct bcm54xx_phy_priv *priv;
 784
 785         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 786         if (!priv)
 787                 return -ENOMEM;
 788
 789         phydev->priv = priv;
 790
 791         priv->stats = devm_kcalloc(&phydev->mdio.dev,
 792                                    bcm_phy_get_sset_count(phydev), sizeof(u64),
 793                                    GFP_KERNEL);
 794         if (!priv->stats)
 795                 return -ENOMEM;
 796
 797         priv->ptp = bcm_ptp_probe(phydev);
 798         if (IS_ERR(priv->ptp))
 799                 return PTR_ERR(priv->ptp);
 800
 801         return 0;
 802 }
 803
 804 static void bcm54xx_get_stats(struct phy_device *phydev,
 805                               struct ethtool_stats *stats, u64 *data)
 806 {
 807         struct bcm54xx_phy_priv *priv = phydev->priv;
 808
 809         bcm_phy_get_stats(phydev, priv->stats, stats, data);
 810 }
 811
 812 static void bcm54xx_link_change_notify(struct phy_device *phydev)
 813 {
 814         u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE |
 815                    MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE;
 816         int ret;
 817
 818         if (phydev->state != PHY_RUNNING)
 819                 return;
 820
 821         /* Don't change the DAC wake settings if auto power down
 822          * is not requested.
 823          */
 824         if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
 825                 return;
 826
 827         ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08);
 828         if (ret < 0)
 829                 return;
 830
 831         /* Enable/disable 10BaseT auto and forced early DAC wake depending
 832          * on the negotiated speed, those settings should only be done
 833          * for 10Mbits/sec.
 834          */
 835         if (phydev->speed == SPEED_10)
 836                 ret |= mask;
 837         else
 838                 ret &= ~mask;
 839         bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret);
 840 }
 841
 842 static struct phy_driver broadcom_drivers[] = {
 843 {
 844         .phy_id         = PHY_ID_BCM5411,
 845         .phy_id_mask    = 0xfffffff0,
 846         .name           = "Broadcom BCM5411",
 847         /* PHY_GBIT_FEATURES */
 848         .get_sset_count = bcm_phy_get_sset_count,
 849         .get_strings    = bcm_phy_get_strings,
 850         .get_stats      = bcm54xx_get_stats,
 851         .probe          = bcm54xx_phy_probe,
 852         .config_init    = bcm54xx_config_init,
 853         .config_intr    = bcm_phy_config_intr,
 854         .handle_interrupt = bcm_phy_handle_interrupt,
 855         .link_change_notify     = bcm54xx_link_change_notify,
 856 }, {
 857         .phy_id         = PHY_ID_BCM5421,
 858         .phy_id_mask    = 0xfffffff0,
 859         .name           = "Broadcom BCM5421",
 860         /* PHY_GBIT_FEATURES */
 861         .get_sset_count = bcm_phy_get_sset_count,
 862         .get_strings    = bcm_phy_get_strings,
 863         .get_stats      = bcm54xx_get_stats,
 864         .probe          = bcm54xx_phy_probe,
 865         .config_init    = bcm54xx_config_init,
 866         .config_intr    = bcm_phy_config_intr,
 867         .handle_interrupt = bcm_phy_handle_interrupt,
 868         .link_change_notify     = bcm54xx_link_change_notify,
 869 }, {
 870         .phy_id         = PHY_ID_BCM54210E,
 871         .phy_id_mask    = 0xffffffff,
 872         .name           = "Broadcom BCM54210E",
 873         /* PHY_GBIT_FEATURES */
 874         .get_sset_count = bcm_phy_get_sset_count,
 875         .get_strings    = bcm_phy_get_strings,
 876         .get_stats      = bcm54xx_get_stats,
 877         .probe          = bcm54xx_phy_probe,
 878         .config_init    = bcm54xx_config_init,
 879         .config_intr    = bcm_phy_config_intr,
 880         .handle_interrupt = bcm_phy_handle_interrupt,
 881         .link_change_notify     = bcm54xx_link_change_notify,
 882         .suspend        = bcm54xx_suspend,
 883         .resume         = bcm54xx_resume,
 884 }, {
 885         .phy_id         = PHY_ID_BCM54213PE,
 886         .phy_id_mask    = 0xffffffff,
 887         .name           = "Broadcom BCM54213PE",
 888         /* PHY_GBIT_FEATURES */
 889         .get_sset_count = bcm_phy_get_sset_count,
 890         .get_strings    = bcm_phy_get_strings,
 891         .get_stats      = bcm54xx_get_stats,
 892         .probe          = bcm54xx_phy_probe,
 893         .config_init    = bcm54xx_config_init,
 894         .config_intr    = bcm_phy_config_intr,
 895         .suspend        = bcm54xx_suspend,
 896         .resume         = bcm54xx_resume,
 897 }, {
 898         .phy_id         = PHY_ID_BCM5461,
 899         .phy_id_mask    = 0xfffffff0,
 900         .name           = "Broadcom BCM5461",
 901         /* PHY_GBIT_FEATURES */
 902         .get_sset_count = bcm_phy_get_sset_count,
 903         .get_strings    = bcm_phy_get_strings,
 904         .get_stats      = bcm54xx_get_stats,
 905         .probe          = bcm54xx_phy_probe,
 906         .config_init    = bcm54xx_config_init,
 907         .config_intr    = bcm_phy_config_intr,
 908         .handle_interrupt = bcm_phy_handle_interrupt,
 909         .link_change_notify     = bcm54xx_link_change_notify,
 910 }, {
 911         .phy_id         = PHY_ID_BCM54612E,
 912         .phy_id_mask    = 0xfffffff0,
 913         .name           = "Broadcom BCM54612E",
 914         /* PHY_GBIT_FEATURES */
 915         .get_sset_count = bcm_phy_get_sset_count,
 916         .get_strings    = bcm_phy_get_strings,
 917         .get_stats      = bcm54xx_get_stats,
 918         .probe          = bcm54xx_phy_probe,
 919         .config_init    = bcm54xx_config_init,
 920         .config_intr    = bcm_phy_config_intr,
 921         .handle_interrupt = bcm_phy_handle_interrupt,
 922         .link_change_notify     = bcm54xx_link_change_notify,
 923 }, {
 924         .phy_id         = PHY_ID_BCM54616S,
 925         .phy_id_mask    = 0xfffffff0,
 926         .name           = "Broadcom BCM54616S",
 927         /* PHY_GBIT_FEATURES */
 928         .soft_reset     = genphy_soft_reset,
 929         .config_init    = bcm54xx_config_init,
 930         .config_aneg    = bcm54616s_config_aneg,
 931         .config_intr    = bcm_phy_config_intr,
 932         .handle_interrupt = bcm_phy_handle_interrupt,
 933         .read_status    = bcm54616s_read_status,
 934         .probe          = bcm54616s_probe,
 935         .link_change_notify     = bcm54xx_link_change_notify,
 936 }, {
 937         .phy_id         = PHY_ID_BCM5464,
 938         .phy_id_mask    = 0xfffffff0,
 939         .name           = "Broadcom BCM5464",
 940         /* PHY_GBIT_FEATURES */
 941         .get_sset_count = bcm_phy_get_sset_count,
 942         .get_strings    = bcm_phy_get_strings,
 943         .get_stats      = bcm54xx_get_stats,
 944         .probe          = bcm54xx_phy_probe,
 945         .config_init    = bcm54xx_config_init,
 946         .config_intr    = bcm_phy_config_intr,
 947         .handle_interrupt = bcm_phy_handle_interrupt,
 948         .suspend        = genphy_suspend,
 949         .resume         = genphy_resume,
 950         .link_change_notify     = bcm54xx_link_change_notify,
 951 }, {
 952         .phy_id         = PHY_ID_BCM5481,
 953         .phy_id_mask    = 0xfffffff0,
 954         .name           = "Broadcom BCM5481",
 955         /* PHY_GBIT_FEATURES */
 956         .get_sset_count = bcm_phy_get_sset_count,
 957         .get_strings    = bcm_phy_get_strings,
 958         .get_stats      = bcm54xx_get_stats,
 959         .probe          = bcm54xx_phy_probe,
 960         .config_init    = bcm54xx_config_init,
 961         .config_aneg    = bcm5481_config_aneg,
 962         .config_intr    = bcm_phy_config_intr,
 963         .handle_interrupt = bcm_phy_handle_interrupt,
 964         .link_change_notify     = bcm54xx_link_change_notify,
 965 }, {
 966         .phy_id         = PHY_ID_BCM54810,
 967         .phy_id_mask    = 0xfffffff0,
 968         .name           = "Broadcom BCM54810",
 969         /* PHY_GBIT_FEATURES */
 970         .get_sset_count = bcm_phy_get_sset_count,
 971         .get_strings    = bcm_phy_get_strings,
 972         .get_stats      = bcm54xx_get_stats,
 973         .probe          = bcm54xx_phy_probe,
 974         .config_init    = bcm54xx_config_init,
 975         .config_aneg    = bcm5481_config_aneg,
 976         .config_intr    = bcm_phy_config_intr,
 977         .handle_interrupt = bcm_phy_handle_interrupt,
 978         .suspend        = bcm54xx_suspend,
 979         .resume         = bcm54xx_resume,
 980         .link_change_notify     = bcm54xx_link_change_notify,
 981 }, {
 982         .phy_id         = PHY_ID_BCM54811,
 983         .phy_id_mask    = 0xfffffff0,
 984         .name           = "Broadcom BCM54811",
 985         /* PHY_GBIT_FEATURES */
 986         .get_sset_count = bcm_phy_get_sset_count,
 987         .get_strings    = bcm_phy_get_strings,
 988         .get_stats      = bcm54xx_get_stats,
 989         .probe          = bcm54xx_phy_probe,
 990         .config_init    = bcm54811_config_init,
 991         .config_aneg    = bcm5481_config_aneg,
 992         .config_intr    = bcm_phy_config_intr,
 993         .handle_interrupt = bcm_phy_handle_interrupt,
 994         .suspend        = bcm54xx_suspend,
 995         .resume         = bcm54xx_resume,
 996         .link_change_notify     = bcm54xx_link_change_notify,
 997 }, {
 998         .phy_id         = PHY_ID_BCM5482,
 999         .phy_id_mask    = 0xfffffff0,
1000         .name           = "Broadcom BCM5482",
1001         /* PHY_GBIT_FEATURES */
1002         .get_sset_count = bcm_phy_get_sset_count,
1003         .get_strings    = bcm_phy_get_strings,
1004         .get_stats      = bcm54xx_get_stats,
1005         .probe          = bcm54xx_phy_probe,
1006         .config_init    = bcm54xx_config_init,
1007         .config_intr    = bcm_phy_config_intr,
1008         .handle_interrupt = bcm_phy_handle_interrupt,
1009         .link_change_notify     = bcm54xx_link_change_notify,
1010 }, {
1011         .phy_id         = PHY_ID_BCM50610,
1012         .phy_id_mask    = 0xfffffff0,
1013         .name           = "Broadcom BCM50610",
1014         /* PHY_GBIT_FEATURES */
1015         .get_sset_count = bcm_phy_get_sset_count,
1016         .get_strings    = bcm_phy_get_strings,
1017         .get_stats      = bcm54xx_get_stats,
1018         .probe          = bcm54xx_phy_probe,
1019         .config_init    = bcm54xx_config_init,
1020         .config_intr    = bcm_phy_config_intr,
1021         .handle_interrupt = bcm_phy_handle_interrupt,
1022         .link_change_notify     = bcm54xx_link_change_notify,
1023         .suspend        = bcm54xx_suspend,
1024         .resume         = bcm54xx_resume,
1025 }, {
1026         .phy_id         = PHY_ID_BCM50610M,
1027         .phy_id_mask    = 0xfffffff0,
1028         .name           = "Broadcom BCM50610M",
1029         /* PHY_GBIT_FEATURES */
1030         .get_sset_count = bcm_phy_get_sset_count,
1031         .get_strings    = bcm_phy_get_strings,
1032         .get_stats      = bcm54xx_get_stats,
1033         .probe          = bcm54xx_phy_probe,
1034         .config_init    = bcm54xx_config_init,
1035         .config_intr    = bcm_phy_config_intr,
1036         .handle_interrupt = bcm_phy_handle_interrupt,
1037         .link_change_notify     = bcm54xx_link_change_notify,
1038         .suspend        = bcm54xx_suspend,
1039         .resume         = bcm54xx_resume,
1040 }, {
1041         .phy_id         = PHY_ID_BCM57780,
1042         .phy_id_mask    = 0xfffffff0,
1043         .name           = "Broadcom BCM57780",
1044         /* PHY_GBIT_FEATURES */
1045         .get_sset_count = bcm_phy_get_sset_count,
1046         .get_strings    = bcm_phy_get_strings,
1047         .get_stats      = bcm54xx_get_stats,
1048         .probe          = bcm54xx_phy_probe,
1049         .config_init    = bcm54xx_config_init,
1050         .config_intr    = bcm_phy_config_intr,
1051         .handle_interrupt = bcm_phy_handle_interrupt,
1052         .link_change_notify     = bcm54xx_link_change_notify,
1053 }, {
1054         .phy_id         = PHY_ID_BCMAC131,
1055         .phy_id_mask    = 0xfffffff0,
1056         .name           = "Broadcom BCMAC131",
1057         /* PHY_BASIC_FEATURES */
1058         .config_init    = brcm_fet_config_init,
1059         .config_intr    = brcm_fet_config_intr,
1060         .handle_interrupt = brcm_fet_handle_interrupt,
1061 }, {
1062         .phy_id         = PHY_ID_BCM5241,
1063         .phy_id_mask    = 0xfffffff0,
1064         .name           = "Broadcom BCM5241",
1065         /* PHY_BASIC_FEATURES */
1066         .config_init    = brcm_fet_config_init,
1067         .config_intr    = brcm_fet_config_intr,
1068         .handle_interrupt = brcm_fet_handle_interrupt,
1069 }, {
1070         .phy_id         = PHY_ID_BCM5395,
1071         .phy_id_mask    = 0xfffffff0,
1072         .name           = "Broadcom BCM5395",
1073         .flags          = PHY_IS_INTERNAL,
1074         /* PHY_GBIT_FEATURES */
1075         .get_sset_count = bcm_phy_get_sset_count,
1076         .get_strings    = bcm_phy_get_strings,
1077         .get_stats      = bcm54xx_get_stats,
1078         .probe          = bcm54xx_phy_probe,
1079         .link_change_notify     = bcm54xx_link_change_notify,
1080 }, {
1081         .phy_id         = PHY_ID_BCM53125,
1082         .phy_id_mask    = 0xfffffff0,
1083         .name           = "Broadcom BCM53125",
1084         .flags          = PHY_IS_INTERNAL,
1085         /* PHY_GBIT_FEATURES */
1086         .get_sset_count = bcm_phy_get_sset_count,
1087         .get_strings    = bcm_phy_get_strings,
1088         .get_stats      = bcm54xx_get_stats,
1089         .probe          = bcm54xx_phy_probe,
1090         .config_init    = bcm54xx_config_init,
1091         .config_intr    = bcm_phy_config_intr,
1092         .handle_interrupt = bcm_phy_handle_interrupt,
1093         .link_change_notify     = bcm54xx_link_change_notify,
1094 }, {
1095         .phy_id         = PHY_ID_BCM89610,
1096         .phy_id_mask    = 0xfffffff0,
1097         .name           = "Broadcom BCM89610",
1098         /* PHY_GBIT_FEATURES */
1099         .get_sset_count = bcm_phy_get_sset_count,
1100         .get_strings    = bcm_phy_get_strings,
1101         .get_stats      = bcm54xx_get_stats,
1102         .probe          = bcm54xx_phy_probe,
1103         .config_init    = bcm54xx_config_init,
1104         .config_intr    = bcm_phy_config_intr,
1105         .handle_interrupt = bcm_phy_handle_interrupt,
1106         .link_change_notify     = bcm54xx_link_change_notify,
1107 } };
1108
1109 module_phy_driver(broadcom_drivers);
1110
1111 static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
1112         { PHY_ID_BCM5411, 0xfffffff0 },
1113         { PHY_ID_BCM5421, 0xfffffff0 },
1114         { PHY_ID_BCM54210E, 0xffffffff },
1115         { PHY_ID_BCM54213PE, 0xffffffff },
1116         { PHY_ID_BCM5461, 0xfffffff0 },
1117         { PHY_ID_BCM54612E, 0xfffffff0 },
1118         { PHY_ID_BCM54616S, 0xfffffff0 },
1119         { PHY_ID_BCM5464, 0xfffffff0 },
1120         { PHY_ID_BCM5481, 0xfffffff0 },
1121         { PHY_ID_BCM54810, 0xfffffff0 },
1122         { PHY_ID_BCM54811, 0xfffffff0 },
1123         { PHY_ID_BCM5482, 0xfffffff0 },
1124         { PHY_ID_BCM50610, 0xfffffff0 },
1125         { PHY_ID_BCM50610M, 0xfffffff0 },
1126         { PHY_ID_BCM57780, 0xfffffff0 },
1127         { PHY_ID_BCMAC131, 0xfffffff0 },
1128         { PHY_ID_BCM5241, 0xfffffff0 },
1129         { PHY_ID_BCM5395, 0xfffffff0 },
1130         { PHY_ID_BCM53125, 0xfffffff0 },
1131         { PHY_ID_BCM89610, 0xfffffff0 },
1132         { }
1133 };
1134
1135 MODULE_DEVICE_TABLE(mdio, broadcom_tbl);