1 // SPDX-License-Identifier: GPL-2.0
2 // Broadcom BCM84881 NBASE-T PHY driver, as found on a SFP+ module.
3 // Copyright (C) 2019 Russell King, Deep Blue Solutions Ltd.
5 // Like the Marvell 88x3310, the Broadcom 84881 changes its host-side
6 // interface according to the operating speed between 10GBASE-R,
7 // 2500BASE-X and SGMII (but unlike the 88x3310, without the control
10 // This driver only supports those aspects of the PHY that I'm able to
11 // observe and test with the SFP+ module, which is an incomplete subset
12 // of what this PHY is able to support. For example, I only assume it
13 // supports a single lane Serdes connection, but it may be that the PHY
14 // is able to support more than that.
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/phy.h>
23 static int bcm84881_wait_init(struct phy_device *phydev)
27 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
28 val, !(val & MDIO_CTRL1_RESET),
29 100000, 2000000, false);
32 static int bcm84881_config_init(struct phy_device *phydev)
34 switch (phydev->interface) {
35 case PHY_INTERFACE_MODE_SGMII:
36 case PHY_INTERFACE_MODE_2500BASEX:
37 case PHY_INTERFACE_MODE_10GBASER:
45 static int bcm84881_probe(struct phy_device *phydev)
47 /* This driver requires PMAPMD and AN blocks */
48 const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
50 if (!phydev->is_c45 ||
51 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
57 static int bcm84881_get_features(struct phy_device *phydev)
61 ret = genphy_c45_pma_read_abilities(phydev);
65 /* Although the PHY sets bit 1.11.8, it does not support 10M modes */
66 linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
68 linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
74 static int bcm84881_config_aneg(struct phy_device *phydev)
80 /* Wait for the PHY to finish initialising, otherwise our
81 * advertisement may be overwritten.
83 ret = bcm84881_wait_init(phydev);
87 /* We don't support manual MDI control */
88 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
90 /* disabled autoneg doesn't seem to work with this PHY */
91 if (phydev->autoneg == AUTONEG_DISABLE)
94 ret = genphy_c45_an_config_aneg(phydev);
100 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
101 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
102 MDIO_AN_C22 + MII_CTRL1000,
103 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
110 return genphy_c45_check_and_restart_aneg(phydev, changed);
113 static int bcm84881_aneg_done(struct phy_device *phydev)
117 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
121 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
125 return !!(val & MDIO_AN_STAT1_COMPLETE) &&
126 !!(bmsr & BMSR_ANEGCOMPLETE);
129 static int bcm84881_read_status(struct phy_device *phydev)
134 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
138 if (val & MDIO_AN_CTRL1_RESTART) {
143 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
147 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR);
151 phydev->autoneg_complete = !!(val & MDIO_AN_STAT1_COMPLETE) &&
152 !!(bmsr & BMSR_ANEGCOMPLETE);
153 phydev->link = !!(val & MDIO_STAT1_LSTATUS) &&
154 !!(bmsr & BMSR_LSTATUS);
155 if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
156 phydev->link = false;
158 linkmode_zero(phydev->lp_advertising);
159 phydev->speed = SPEED_UNKNOWN;
160 phydev->duplex = DUPLEX_UNKNOWN;
162 phydev->asym_pause = 0;
168 if (phydev->autoneg_complete) {
169 val = genphy_c45_read_lpa(phydev);
173 val = phy_read_mmd(phydev, MDIO_MMD_AN,
174 MDIO_AN_C22 + MII_STAT1000);
178 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
180 if (phydev->autoneg == AUTONEG_ENABLE)
181 phy_resolve_aneg_linkmode(phydev);
184 if (phydev->autoneg == AUTONEG_DISABLE) {
185 /* disabled autoneg doesn't seem to work, so force the link
192 /* Set the host link mode - we set the phy interface mode and
193 * the speed according to this register so that downshift works.
194 * We leave the duplex setting as per the resolution from the
197 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
198 mode = (val & 0x1e) >> 1;
199 if (mode == 1 || mode == 2)
200 phydev->interface = PHY_INTERFACE_MODE_SGMII;
202 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
204 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
207 phydev->speed = SPEED_100;
210 phydev->speed = SPEED_1000;
213 phydev->speed = SPEED_10000;
216 phydev->speed = SPEED_2500;
219 phydev->speed = SPEED_5000;
223 return genphy_c45_read_mdix(phydev);
226 static struct phy_driver bcm84881_drivers[] = {
228 .phy_id = 0xae025150,
229 .phy_id_mask = 0xfffffff0,
230 .name = "Broadcom BCM84881",
231 .config_init = bcm84881_config_init,
232 .probe = bcm84881_probe,
233 .get_features = bcm84881_get_features,
234 .config_aneg = bcm84881_config_aneg,
235 .aneg_done = bcm84881_aneg_done,
236 .read_status = bcm84881_read_status,
240 module_phy_driver(bcm84881_drivers);
242 /* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
243 static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
244 { 0xae025150, 0xfffffff0 },
247 MODULE_AUTHOR("Russell King");
248 MODULE_DESCRIPTION("Broadcom BCM84881 PHY driver");
249 MODULE_DEVICE_TABLE(mdio, bcm84881_tbl);
250 MODULE_LICENSE("GPL");