1 // SPDX-License-Identifier: GPL-2.0+
5 * Florian Fainelli <f.fainelli@gmail.com>
9 * PHY driver for Broadcom BCM53xx (roboswitch) Ethernet switches.
11 * This driver configures the b53 for basic use as a PHY. The switch supports
12 * vendor tags and VLAN configuration that can affect the switching decisions.
13 * This driver uses a simple configuration in which all ports are only allowed
14 * to send frames to the CPU port and receive frames from the CPU port this
15 * providing port isolation (no cross talk).
17 * The configuration determines which PHY ports to activate using the
18 * CONFIG_B53_PHY_PORTS bitmask. Set bit N will active port N and so on.
20 * This driver was written primarily for the Lamobo R1 platform using a BCM53152
21 * switch but the BCM53xx being largely register compatible, extending it to
22 * cover other switches would be trivial.
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
35 /* Pseudo-PHY address (non configurable) to access internal registers */
36 #define BRCM_PSEUDO_PHY_ADDR 30
38 /* Maximum number of ports possible */
41 #define B53_CTRL_PAGE 0x00 /* Control */
42 #define B53_MGMT_PAGE 0x02 /* Management Mode */
44 #define B53_PVLAN_PAGE 0x31
46 /* Control Page registers */
47 #define B53_PORT_CTRL(i) (0x00 + (i))
48 #define PORT_CTRL_RX_DISABLE BIT(0)
49 #define PORT_CTRL_TX_DISABLE BIT(1)
50 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
51 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
52 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
54 /* Switch Mode Control Register (8 bit) */
55 #define B53_SWITCH_MODE 0x0b
56 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
57 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
59 /* IMP Port state override register (8 bit) */
60 #define B53_PORT_OVERRIDE_CTRL 0x0e
61 #define PORT_OVERRIDE_LINK BIT(0)
62 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
63 #define PORT_OVERRIDE_SPEED_S 2
64 #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
65 #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
66 #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
68 #define PORT_OVERRIDE_RV_MII_25 BIT(4)
69 #define PORT_OVERRIDE_RX_FLOW BIT(4)
70 #define PORT_OVERRIDE_TX_FLOW BIT(5)
71 /* BCM5301X only, requires setting 1000M */
72 #define PORT_OVERRIDE_SPEED_2000M BIT(6)
73 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
75 #define B53_RGMII_CTRL_IMP 0x60
76 #define RGMII_CTRL_ENABLE_GMII BIT(7)
77 #define RGMII_CTRL_TIMING_SEL BIT(2)
78 #define RGMII_CTRL_DLL_RXC BIT(1)
79 #define RGMII_CTRL_DLL_TXC BIT(0)
81 /* Switch control (8 bit) */
82 #define B53_SWITCH_CTRL 0x22
83 #define B53_MII_DUMB_FWDG_EN BIT(6)
85 /* Software reset register (8 bit) */
86 #define B53_SOFTRESET 0x79
88 #define EN_CH_RST BIT(6)
89 #define EN_SW_RST BIT(4)
91 /* Fast Aging Control register (8 bit) */
92 #define B53_FAST_AGE_CTRL 0x88
93 #define FAST_AGE_STATIC BIT(0)
94 #define FAST_AGE_DYNAMIC BIT(1)
95 #define FAST_AGE_PORT BIT(2)
96 #define FAST_AGE_VLAN BIT(3)
97 #define FAST_AGE_STP BIT(4)
98 #define FAST_AGE_MC BIT(5)
99 #define FAST_AGE_DONE BIT(7)
101 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
102 #define B53_PVLAN_PORT_MASK(i) ((i) * 2)
105 #define REG_MII_PAGE 0x10 /* MII Page register */
106 #define REG_MII_ADDR 0x11 /* MII Address register */
107 #define REG_MII_DATA0 0x18 /* MII Data register 0 */
108 #define REG_MII_DATA1 0x19 /* MII Data register 1 */
109 #define REG_MII_DATA2 0x1a /* MII Data register 2 */
110 #define REG_MII_DATA3 0x1b /* MII Data register 3 */
112 #define REG_MII_PAGE_ENABLE BIT(0)
113 #define REG_MII_ADDR_WRITE BIT(0)
114 #define REG_MII_ADDR_READ BIT(1)
118 unsigned int cpu_port;
121 static int b53_mdio_op(struct mii_dev *bus, u8 page, u8 reg, u16 op)
127 /* set page number */
128 v = (page << 8) | REG_MII_PAGE_ENABLE;
129 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
134 /* set register address */
136 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
141 /* check if operation completed */
142 for (i = 0; i < 5; ++i) {
143 v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
145 if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))
157 static int b53_mdio_read8(struct mii_dev *bus, u8 page, u8 reg, u8 *val)
161 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
165 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
166 REG_MII_DATA0) & 0xff;
171 static int b53_mdio_read16(struct mii_dev *bus, u8 page, u8 reg, u16 *val)
175 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
179 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
185 static int b53_mdio_read32(struct mii_dev *bus, u8 page, u8 reg, u32 *val)
189 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
193 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
195 *val |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
196 REG_MII_DATA1) << 16;
201 static int b53_mdio_read48(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
207 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
211 for (i = 2; i >= 0; i--) {
213 temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
222 static int b53_mdio_read64(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
228 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
232 for (i = 3; i >= 0; i--) {
234 temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
243 static int b53_mdio_write8(struct mii_dev *bus, u8 page, u8 reg, u8 value)
247 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
248 REG_MII_DATA0, value);
252 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
255 static int b53_mdio_write16(struct mii_dev *bus, u8 page, u8 reg,
260 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
261 REG_MII_DATA0, value);
265 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
268 static int b53_mdio_write32(struct mii_dev *bus, u8 page, u8 reg,
274 for (i = 0; i < 2; i++) {
275 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
277 REG_MII_DATA0 + i, temp & 0xffff);
283 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
286 static int b53_mdio_write48(struct mii_dev *bus, u8 page, u8 reg,
292 for (i = 0; i < 3; i++) {
293 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
295 REG_MII_DATA0 + i, temp & 0xffff);
301 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
304 static int b53_mdio_write64(struct mii_dev *bus, u8 page, u8 reg,
310 for (i = 0; i < 4; i++) {
311 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
313 REG_MII_DATA0 + i, temp & 0xffff);
319 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
322 static inline int b53_read8(struct b53_device *dev, u8 page,
325 return b53_mdio_read8(dev->bus, page, reg, value);
328 static inline int b53_read16(struct b53_device *dev, u8 page,
331 return b53_mdio_read16(dev->bus, page, reg, value);
334 static inline int b53_read32(struct b53_device *dev, u8 page,
337 return b53_mdio_read32(dev->bus, page, reg, value);
340 static inline int b53_read48(struct b53_device *dev, u8 page,
343 return b53_mdio_read48(dev->bus, page, reg, value);
346 static inline int b53_read64(struct b53_device *dev, u8 page,
349 return b53_mdio_read64(dev->bus, page, reg, value);
352 static inline int b53_write8(struct b53_device *dev, u8 page,
355 return b53_mdio_write8(dev->bus, page, reg, value);
358 static inline int b53_write16(struct b53_device *dev, u8 page,
361 return b53_mdio_write16(dev->bus, page, reg, value);
364 static inline int b53_write32(struct b53_device *dev, u8 page,
367 return b53_mdio_write32(dev->bus, page, reg, value);
370 static inline int b53_write48(struct b53_device *dev, u8 page,
373 return b53_mdio_write48(dev->bus, page, reg, value);
376 static inline int b53_write64(struct b53_device *dev, u8 page,
379 return b53_mdio_write64(dev->bus, page, reg, value);
382 static int b53_flush_arl(struct b53_device *dev, u8 mask)
386 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
387 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
389 for (i = 0; i < 10; i++) {
392 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
395 if (!(fast_age_ctrl & FAST_AGE_DONE))
403 /* Only age dynamic entries (default behavior) */
404 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
408 static int b53_switch_reset(struct phy_device *phydev)
410 struct b53_device *dev = phydev->priv;
411 unsigned int timeout = 1000;
415 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
416 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
417 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
420 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
425 } while (timeout-- > 0);
430 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
432 if (!(mgmt & SM_SW_FWD_EN)) {
433 mgmt &= ~SM_SW_FWD_MODE;
434 mgmt |= SM_SW_FWD_EN;
436 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
437 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
439 if (!(mgmt & SM_SW_FWD_EN)) {
440 printf("Failed to enable switch!\n");
445 /* Include IMP port in dumb forwarding mode when no tagging protocol
448 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
449 mgmt |= B53_MII_DUMB_FWDG_EN;
450 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
452 return b53_flush_arl(dev, FAST_AGE_STATIC);
455 static void b53_enable_cpu_port(struct phy_device *phydev)
457 struct b53_device *dev = phydev->priv;
460 port_ctrl = PORT_CTRL_RX_BCST_EN |
461 PORT_CTRL_RX_MCST_EN |
462 PORT_CTRL_RX_UCST_EN;
463 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(dev->cpu_port), port_ctrl);
465 port_ctrl = PORT_OVERRIDE_EN | PORT_OVERRIDE_LINK |
466 PORT_OVERRIDE_FULL_DUPLEX | PORT_OVERRIDE_SPEED_1000M;
467 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, port_ctrl);
469 b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_IMP, &port_ctrl);
472 static void b53_imp_vlan_setup(struct b53_device *dev, int cpu_port)
477 /* Enable the IMP port to be in the same VLAN as the other ports
478 * on a per-port basis such that we only have Port i and IMP in
481 for (port = 0; port < B53_N_PORTS; port++) {
482 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
485 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
487 pvlan |= BIT(cpu_port);
488 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
493 static int b53_port_enable(struct phy_device *phydev, unsigned int port)
495 struct b53_device *dev = phydev->priv;
496 unsigned int cpu_port = dev->cpu_port;
499 /* Clear the Rx and Tx disable bits and set to no spanning tree */
500 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
502 /* Set this port, and only this one to be in the default VLAN */
503 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
506 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
508 b53_imp_vlan_setup(dev, cpu_port);
513 static int b53_switch_init(struct phy_device *phydev)
521 ret = b53_switch_reset(phydev);
525 b53_enable_cpu_port(phydev);
532 static int b53_probe(struct phy_device *phydev)
534 struct b53_device *dev;
537 dev = malloc(sizeof(*dev));
541 memset(dev, 0, sizeof(*dev));
544 dev->bus = phydev->bus;
545 dev->cpu_port = CONFIG_B53_CPU_PORT;
547 ret = b53_switch_reset(phydev);
554 static int b53_phy_config(struct phy_device *phydev)
559 res = b53_switch_init(phydev);
563 for (port = 0; port < B53_N_PORTS; port++) {
564 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
567 res = b53_port_enable(phydev, port);
569 printf("Error enabling port %i\n", port);
573 res = genphy_config_aneg(phydev);
575 printf("Error setting PHY %i autoneg\n", port);
585 static int b53_phy_startup(struct phy_device *phydev)
590 for (port = 0; port < B53_N_PORTS; port++) {
591 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
596 res = genphy_startup(phydev);
603 /* Since we are connected directly to the switch, hardcode the link
604 * parameters to match those of the CPU port configured in
605 * b53_enable_cpu_port, we cannot be dependent on the user-facing port
606 * settings (e.g: 100Mbits/sec would not work here)
608 phydev->speed = 1000;
615 static struct phy_driver b53_driver = {
616 .name = "Broadcom BCM53125",
619 .features = PHY_GBIT_FEATURES,
621 .config = b53_phy_config,
622 .startup = b53_phy_startup,
623 .shutdown = &genphy_shutdown,
626 int phy_b53_init(void)
628 phy_register(&b53_driver);
633 int do_b53_reg_read(const char *name, int argc, char *const argv[])
635 u8 page, offset, width;
643 bus = miiphy_get_dev_by_name(name);
645 printf("unable to find MDIO bus: %s\n", name);
649 page = hextoul(argv[1], NULL);
650 offset = hextoul(argv[2], NULL);
651 width = dectoul(argv[3], NULL);
655 ret = b53_mdio_read8(bus, page, offset, &value8);
656 printf("page=0x%02x, offset=0x%02x, value=0x%02x\n",
657 page, offset, value8);
660 ret = b53_mdio_read16(bus, page, offset, &value16);
661 printf("page=0x%02x, offset=0x%02x, value=0x%04x\n",
662 page, offset, value16);
665 ret = b53_mdio_read32(bus, page, offset, &value32);
666 printf("page=0x%02x, offset=0x%02x, value=0x%08x\n",
667 page, offset, value32);
670 ret = b53_mdio_read48(bus, page, offset, &value64);
671 printf("page=0x%02x, offset=0x%02x, value=0x%012llx\n",
672 page, offset, value64);
675 ret = b53_mdio_read48(bus, page, offset, &value64);
676 printf("page=0x%02x, offset=0x%02x, value=0x%016llx\n",
677 page, offset, value64);
680 printf("Unsupported width: %d\n", width);
687 int do_b53_reg_write(const char *name, int argc, char *const argv[])
689 u8 page, offset, width;
695 bus = miiphy_get_dev_by_name(name);
697 printf("unable to find MDIO bus: %s\n", name);
701 page = hextoul(argv[1], NULL);
702 offset = hextoul(argv[2], NULL);
703 width = dectoul(argv[3], NULL);
704 if (width == 48 || width == 64)
705 value64 = simple_strtoull(argv[4], NULL, 16);
707 value = hextoul(argv[4], NULL);
711 ret = b53_mdio_write8(bus, page, offset, value & 0xff);
714 ret = b53_mdio_write16(bus, page, offset, value);
717 ret = b53_mdio_write32(bus, page, offset, value);
720 ret = b53_mdio_write48(bus, page, offset, value64);
723 ret = b53_mdio_write64(bus, page, offset, value64);
726 printf("Unsupported width: %d\n", width);
733 int do_b53_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
735 const char *cmd, *mdioname;
739 return cmd_usage(cmdtp);
745 if (!strcmp(cmd, "write")) {
747 return cmd_usage(cmdtp);
751 ret = do_b53_reg_write(mdioname, argc, argv);
752 } else if (!strcmp(cmd, "read")) {
754 return cmd_usage(cmdtp);
758 ret = do_b53_reg_read(mdioname, argc, argv);
760 return cmd_usage(cmdtp);
766 U_BOOT_CMD(b53_reg, 7, 1, do_b53_reg,
767 "Broadcom B53 switch register access",
768 "write mdioname page (hex) offset (hex) width (dec) value (hex)\n"
769 "read mdioname page (hex) offset (hex) width (dec)\n"