1 // SPDX-License-Identifier: GPL-2.0+
5 * Florian Fainelli <f.fainelli@gmail.com>
9 * PHY driver for Broadcom BCM53xx (roboswitch) Ethernet switches.
11 * This driver configures the b53 for basic use as a PHY. The switch supports
12 * vendor tags and VLAN configuration that can affect the switching decisions.
13 * This driver uses a simple configuration in which all ports are only allowed
14 * to send frames to the CPU port and receive frames from the CPU port this
15 * providing port isolation (no cross talk).
17 * The configuration determines which PHY ports to activate using the
18 * CONFIG_B53_PHY_PORTS bitmask. Set bit N will active port N and so on.
20 * This driver was written primarily for the Lamobo R1 platform using a BCM53152
21 * switch but the BCM53xx being largely register compatible, extending it to
22 * cover other switches would be trivial.
27 #include <linux/delay.h>
34 /* Pseudo-PHY address (non configurable) to access internal registers */
35 #define BRCM_PSEUDO_PHY_ADDR 30
37 /* Maximum number of ports possible */
40 #define B53_CTRL_PAGE 0x00 /* Control */
41 #define B53_MGMT_PAGE 0x02 /* Management Mode */
43 #define B53_PVLAN_PAGE 0x31
45 /* Control Page registers */
46 #define B53_PORT_CTRL(i) (0x00 + (i))
47 #define PORT_CTRL_RX_DISABLE BIT(0)
48 #define PORT_CTRL_TX_DISABLE BIT(1)
49 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
50 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
51 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
53 /* Switch Mode Control Register (8 bit) */
54 #define B53_SWITCH_MODE 0x0b
55 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
56 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
58 /* IMP Port state override register (8 bit) */
59 #define B53_PORT_OVERRIDE_CTRL 0x0e
60 #define PORT_OVERRIDE_LINK BIT(0)
61 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
62 #define PORT_OVERRIDE_SPEED_S 2
63 #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
64 #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
65 #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
67 #define PORT_OVERRIDE_RV_MII_25 BIT(4)
68 #define PORT_OVERRIDE_RX_FLOW BIT(4)
69 #define PORT_OVERRIDE_TX_FLOW BIT(5)
70 /* BCM5301X only, requires setting 1000M */
71 #define PORT_OVERRIDE_SPEED_2000M BIT(6)
72 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
74 #define B53_RGMII_CTRL_IMP 0x60
75 #define RGMII_CTRL_ENABLE_GMII BIT(7)
76 #define RGMII_CTRL_TIMING_SEL BIT(2)
77 #define RGMII_CTRL_DLL_RXC BIT(1)
78 #define RGMII_CTRL_DLL_TXC BIT(0)
80 /* Switch control (8 bit) */
81 #define B53_SWITCH_CTRL 0x22
82 #define B53_MII_DUMB_FWDG_EN BIT(6)
84 /* Software reset register (8 bit) */
85 #define B53_SOFTRESET 0x79
87 #define EN_CH_RST BIT(6)
88 #define EN_SW_RST BIT(4)
90 /* Fast Aging Control register (8 bit) */
91 #define B53_FAST_AGE_CTRL 0x88
92 #define FAST_AGE_STATIC BIT(0)
93 #define FAST_AGE_DYNAMIC BIT(1)
94 #define FAST_AGE_PORT BIT(2)
95 #define FAST_AGE_VLAN BIT(3)
96 #define FAST_AGE_STP BIT(4)
97 #define FAST_AGE_MC BIT(5)
98 #define FAST_AGE_DONE BIT(7)
100 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
101 #define B53_PVLAN_PORT_MASK(i) ((i) * 2)
104 #define REG_MII_PAGE 0x10 /* MII Page register */
105 #define REG_MII_ADDR 0x11 /* MII Address register */
106 #define REG_MII_DATA0 0x18 /* MII Data register 0 */
107 #define REG_MII_DATA1 0x19 /* MII Data register 1 */
108 #define REG_MII_DATA2 0x1a /* MII Data register 2 */
109 #define REG_MII_DATA3 0x1b /* MII Data register 3 */
111 #define REG_MII_PAGE_ENABLE BIT(0)
112 #define REG_MII_ADDR_WRITE BIT(0)
113 #define REG_MII_ADDR_READ BIT(1)
117 unsigned int cpu_port;
120 static int b53_mdio_op(struct mii_dev *bus, u8 page, u8 reg, u16 op)
126 /* set page number */
127 v = (page << 8) | REG_MII_PAGE_ENABLE;
128 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
133 /* set register address */
135 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
140 /* check if operation completed */
141 for (i = 0; i < 5; ++i) {
142 v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
144 if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))
156 static int b53_mdio_read8(struct mii_dev *bus, u8 page, u8 reg, u8 *val)
160 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
164 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
165 REG_MII_DATA0) & 0xff;
170 static int b53_mdio_read16(struct mii_dev *bus, u8 page, u8 reg, u16 *val)
174 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
178 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
184 static int b53_mdio_read32(struct mii_dev *bus, u8 page, u8 reg, u32 *val)
188 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
192 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
194 *val |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
195 REG_MII_DATA1) << 16;
200 static int b53_mdio_read48(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
206 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
210 for (i = 2; i >= 0; i--) {
212 temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
221 static int b53_mdio_read64(struct mii_dev *bus, u8 page, u8 reg, u64 *val)
227 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ);
231 for (i = 3; i >= 0; i--) {
233 temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
242 static int b53_mdio_write8(struct mii_dev *bus, u8 page, u8 reg, u8 value)
246 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
247 REG_MII_DATA0, value);
251 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
254 static int b53_mdio_write16(struct mii_dev *bus, u8 page, u8 reg,
259 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE,
260 REG_MII_DATA0, value);
264 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
267 static int b53_mdio_write32(struct mii_dev *bus, u8 page, u8 reg,
273 for (i = 0; i < 2; i++) {
274 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
276 REG_MII_DATA0 + i, temp & 0xffff);
282 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
285 static int b53_mdio_write48(struct mii_dev *bus, u8 page, u8 reg,
291 for (i = 0; i < 3; i++) {
292 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
294 REG_MII_DATA0 + i, temp & 0xffff);
300 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
303 static int b53_mdio_write64(struct mii_dev *bus, u8 page, u8 reg,
309 for (i = 0; i < 4; i++) {
310 int ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR,
312 REG_MII_DATA0 + i, temp & 0xffff);
318 return b53_mdio_op(bus, page, reg, REG_MII_ADDR_WRITE);
321 static inline int b53_read8(struct b53_device *dev, u8 page,
324 return b53_mdio_read8(dev->bus, page, reg, value);
327 static inline int b53_read16(struct b53_device *dev, u8 page,
330 return b53_mdio_read16(dev->bus, page, reg, value);
333 static inline int b53_read32(struct b53_device *dev, u8 page,
336 return b53_mdio_read32(dev->bus, page, reg, value);
339 static inline int b53_read48(struct b53_device *dev, u8 page,
342 return b53_mdio_read48(dev->bus, page, reg, value);
345 static inline int b53_read64(struct b53_device *dev, u8 page,
348 return b53_mdio_read64(dev->bus, page, reg, value);
351 static inline int b53_write8(struct b53_device *dev, u8 page,
354 return b53_mdio_write8(dev->bus, page, reg, value);
357 static inline int b53_write16(struct b53_device *dev, u8 page,
360 return b53_mdio_write16(dev->bus, page, reg, value);
363 static inline int b53_write32(struct b53_device *dev, u8 page,
366 return b53_mdio_write32(dev->bus, page, reg, value);
369 static inline int b53_write48(struct b53_device *dev, u8 page,
372 return b53_mdio_write48(dev->bus, page, reg, value);
375 static inline int b53_write64(struct b53_device *dev, u8 page,
378 return b53_mdio_write64(dev->bus, page, reg, value);
381 static int b53_flush_arl(struct b53_device *dev, u8 mask)
385 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
386 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
388 for (i = 0; i < 10; i++) {
391 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
394 if (!(fast_age_ctrl & FAST_AGE_DONE))
402 /* Only age dynamic entries (default behavior) */
403 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
407 static int b53_switch_reset(struct phy_device *phydev)
409 struct b53_device *dev = phydev->priv;
410 unsigned int timeout = 1000;
414 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
415 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
416 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
419 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
424 } while (timeout-- > 0);
429 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
431 if (!(mgmt & SM_SW_FWD_EN)) {
432 mgmt &= ~SM_SW_FWD_MODE;
433 mgmt |= SM_SW_FWD_EN;
435 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
436 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
438 if (!(mgmt & SM_SW_FWD_EN)) {
439 printf("Failed to enable switch!\n");
444 /* Include IMP port in dumb forwarding mode when no tagging protocol
447 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
448 mgmt |= B53_MII_DUMB_FWDG_EN;
449 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
451 return b53_flush_arl(dev, FAST_AGE_STATIC);
454 static void b53_enable_cpu_port(struct phy_device *phydev)
456 struct b53_device *dev = phydev->priv;
459 port_ctrl = PORT_CTRL_RX_BCST_EN |
460 PORT_CTRL_RX_MCST_EN |
461 PORT_CTRL_RX_UCST_EN;
462 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(dev->cpu_port), port_ctrl);
464 port_ctrl = PORT_OVERRIDE_EN | PORT_OVERRIDE_LINK |
465 PORT_OVERRIDE_FULL_DUPLEX | PORT_OVERRIDE_SPEED_1000M;
466 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, port_ctrl);
468 b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_IMP, &port_ctrl);
471 static void b53_imp_vlan_setup(struct b53_device *dev, int cpu_port)
476 /* Enable the IMP port to be in the same VLAN as the other ports
477 * on a per-port basis such that we only have Port i and IMP in
480 for (port = 0; port < B53_N_PORTS; port++) {
481 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
484 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
486 pvlan |= BIT(cpu_port);
487 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port),
492 static int b53_port_enable(struct phy_device *phydev, unsigned int port)
494 struct b53_device *dev = phydev->priv;
495 unsigned int cpu_port = dev->cpu_port;
498 /* Clear the Rx and Tx disable bits and set to no spanning tree */
499 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
501 /* Set this port, and only this one to be in the default VLAN */
502 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
505 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
507 b53_imp_vlan_setup(dev, cpu_port);
512 static int b53_switch_init(struct phy_device *phydev)
520 ret = b53_switch_reset(phydev);
524 b53_enable_cpu_port(phydev);
531 static int b53_probe(struct phy_device *phydev)
533 struct b53_device *dev;
536 dev = malloc(sizeof(*dev));
540 memset(dev, 0, sizeof(*dev));
543 dev->bus = phydev->bus;
544 dev->cpu_port = CONFIG_B53_CPU_PORT;
546 ret = b53_switch_reset(phydev);
553 static int b53_phy_config(struct phy_device *phydev)
558 res = b53_switch_init(phydev);
562 for (port = 0; port < B53_N_PORTS; port++) {
563 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
566 res = b53_port_enable(phydev, port);
568 printf("Error enabling port %i\n", port);
572 res = genphy_config_aneg(phydev);
574 printf("Error setting PHY %i autoneg\n", port);
584 static int b53_phy_startup(struct phy_device *phydev)
589 for (port = 0; port < B53_N_PORTS; port++) {
590 if (!((1 << port) & CONFIG_B53_PHY_PORTS))
595 res = genphy_startup(phydev);
602 /* Since we are connected directly to the switch, hardcode the link
603 * parameters to match those of the CPU port configured in
604 * b53_enable_cpu_port, we cannot be dependent on the user-facing port
605 * settings (e.g: 100Mbits/sec would not work here)
607 phydev->speed = 1000;
614 static struct phy_driver b53_driver = {
615 .name = "Broadcom BCM53125",
618 .features = PHY_GBIT_FEATURES,
620 .config = b53_phy_config,
621 .startup = b53_phy_startup,
622 .shutdown = &genphy_shutdown,
625 int phy_b53_init(void)
627 phy_register(&b53_driver);
632 int do_b53_reg_read(const char *name, int argc, char *const argv[])
634 u8 page, offset, width;
642 bus = miiphy_get_dev_by_name(name);
644 printf("unable to find MDIO bus: %s\n", name);
648 page = simple_strtoul(argv[1], NULL, 16);
649 offset = simple_strtoul(argv[2], NULL, 16);
650 width = simple_strtoul(argv[3], NULL, 10);
654 ret = b53_mdio_read8(bus, page, offset, &value8);
655 printf("page=0x%02x, offset=0x%02x, value=0x%02x\n",
656 page, offset, value8);
659 ret = b53_mdio_read16(bus, page, offset, &value16);
660 printf("page=0x%02x, offset=0x%02x, value=0x%04x\n",
661 page, offset, value16);
664 ret = b53_mdio_read32(bus, page, offset, &value32);
665 printf("page=0x%02x, offset=0x%02x, value=0x%08x\n",
666 page, offset, value32);
669 ret = b53_mdio_read48(bus, page, offset, &value64);
670 printf("page=0x%02x, offset=0x%02x, value=0x%012llx\n",
671 page, offset, value64);
674 ret = b53_mdio_read48(bus, page, offset, &value64);
675 printf("page=0x%02x, offset=0x%02x, value=0x%016llx\n",
676 page, offset, value64);
679 printf("Unsupported width: %d\n", width);
686 int do_b53_reg_write(const char *name, int argc, char *const argv[])
688 u8 page, offset, width;
694 bus = miiphy_get_dev_by_name(name);
696 printf("unable to find MDIO bus: %s\n", name);
700 page = simple_strtoul(argv[1], NULL, 16);
701 offset = simple_strtoul(argv[2], NULL, 16);
702 width = simple_strtoul(argv[3], NULL, 10);
703 if (width == 48 || width == 64)
704 value64 = simple_strtoull(argv[4], NULL, 16);
706 value = simple_strtoul(argv[4], NULL, 16);
710 ret = b53_mdio_write8(bus, page, offset, value & 0xff);
713 ret = b53_mdio_write16(bus, page, offset, value);
716 ret = b53_mdio_write32(bus, page, offset, value);
719 ret = b53_mdio_write48(bus, page, offset, value64);
722 ret = b53_mdio_write64(bus, page, offset, value64);
725 printf("Unsupported width: %d\n", width);
732 int do_b53_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
734 const char *cmd, *mdioname;
738 return cmd_usage(cmdtp);
744 if (!strcmp(cmd, "write")) {
746 return cmd_usage(cmdtp);
750 ret = do_b53_reg_write(mdioname, argc, argv);
751 } else if (!strcmp(cmd, "read")) {
753 return cmd_usage(cmdtp);
757 ret = do_b53_reg_read(mdioname, argc, argv);
759 return cmd_usage(cmdtp);
765 U_BOOT_CMD(b53_reg, 7, 1, do_b53_reg,
766 "Broadcom B53 switch register access",
767 "write mdioname page (hex) offset (hex) width (dec) value (hex)\n"
768 "read mdioname page (hex) offset (hex) width (dec)\n"