1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2011, 2013 Freescale Semiconductor, Inc.
7 * Copyright (c) 2019 Michael Walle <michael@walle.cc>
11 #include <dm/device_compat.h>
12 #include <linux/bitfield.h>
13 #include <linux/bitops.h>
14 #include <dt-bindings/net/qca-ar803x.h>
16 #define AR803x_PHY_DEBUG_ADDR_REG 0x1d
17 #define AR803x_PHY_DEBUG_DATA_REG 0x1e
20 #define AR803x_DEBUG_REG_0 0x0
21 #define AR803x_RGMII_RX_CLK_DLY BIT(15)
23 #define AR803x_DEBUG_REG_5 0x5
24 #define AR803x_RGMII_TX_CLK_DLY BIT(8)
26 #define AR803x_DEBUG_REG_1F 0x1f
27 #define AR803x_PLL_ON BIT(2)
28 #define AR803x_RGMII_1V8 BIT(3)
30 /* CLK_25M register is at MMD 7, address 0x8016 */
31 #define AR803x_CLK_25M_SEL_REG 0x8016
33 #define AR803x_CLK_25M_MASK GENMASK(4, 2)
34 #define AR803x_CLK_25M_25MHZ_XTAL 0
35 #define AR803x_CLK_25M_25MHZ_DSP 1
36 #define AR803x_CLK_25M_50MHZ_PLL 2
37 #define AR803x_CLK_25M_50MHZ_DSP 3
38 #define AR803x_CLK_25M_62_5MHZ_PLL 4
39 #define AR803x_CLK_25M_62_5MHZ_DSP 5
40 #define AR803x_CLK_25M_125MHZ_PLL 6
41 #define AR803x_CLK_25M_125MHZ_DSP 7
42 #define AR8035_CLK_25M_MASK GENMASK(4, 3)
44 #define AR803x_CLK_25M_DR_MASK GENMASK(8, 7)
45 #define AR803x_CLK_25M_DR_FULL 0
46 #define AR803x_CLK_25M_DR_HALF 1
47 #define AR803x_CLK_25M_DR_QUARTER 2
49 #define AR8021_PHY_ID 0x004dd040
50 #define AR8031_PHY_ID 0x004dd074
51 #define AR8035_PHY_ID 0x004dd072
55 #define AR803x_FLAG_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
56 #define AR803x_FLAG_RGMII_1V8 BIT(1) /* use 1.8V RGMII I/O voltage */
61 static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg)
65 ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
70 return phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
73 static int ar803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
78 val = ar803x_debug_reg_read(phydev, reg);
86 return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
90 static int ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
92 u16 clear = 0, set = 0;
95 set = AR803x_RGMII_RX_CLK_DLY;
97 clear = AR803x_RGMII_RX_CLK_DLY;
99 return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0, clear, set);
102 static int ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
104 u16 clear = 0, set = 0;
107 set = AR803x_RGMII_TX_CLK_DLY;
109 clear = AR803x_RGMII_TX_CLK_DLY;
111 return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, clear, set);
114 static int ar8021_config(struct phy_device *phydev)
116 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
117 BMCR_ANENABLE | BMCR_ANRESTART);
119 ar803x_enable_tx_delay(phydev, true);
121 phydev->supported = phydev->drv->features;
125 static int ar803x_delay_config(struct phy_device *phydev)
129 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
130 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
131 ret = ar803x_enable_tx_delay(phydev, true);
133 ret = ar803x_enable_tx_delay(phydev, false);
135 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
136 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
137 ret = ar803x_enable_rx_delay(phydev, true);
139 ret = ar803x_enable_rx_delay(phydev, false);
144 static int ar803x_regs_config(struct phy_device *phydev)
146 struct ar803x_priv *priv = phydev->priv;
147 u16 set = 0, clear = 0;
151 /* no configuration available */
156 * Only supported on the AR8031, AR8035 has strappings for the PLL mode
157 * as well as the RGMII voltage.
159 if (phydev->drv->uid == AR8031_PHY_ID) {
160 if (priv->flags & AR803x_FLAG_KEEP_PLL_ENABLED)
161 set |= AR803x_PLL_ON;
163 clear |= AR803x_PLL_ON;
165 if (priv->flags & AR803x_FLAG_RGMII_1V8)
166 set |= AR803x_RGMII_1V8;
168 clear |= AR803x_RGMII_1V8;
170 ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_1F, clear,
176 /* save the write access if the mask is empty */
177 if (priv->clk_25m_mask) {
178 val = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
181 val &= ~priv->clk_25m_mask;
182 val |= priv->clk_25m_reg;
183 ret = phy_write_mmd(phydev, MDIO_MMD_AN,
184 AR803x_CLK_25M_SEL_REG, val);
192 static int ar803x_of_init(struct phy_device *phydev)
194 #if defined(CONFIG_DM_ETH)
195 struct ar803x_priv *priv;
196 ofnode node, vddio_reg_node;
197 u32 strength, freq, min_uV, max_uV;
200 node = phy_get_ofnode(phydev);
201 if (!ofnode_valid(node))
204 priv = malloc(sizeof(*priv));
207 memset(priv, 0, sizeof(*priv));
211 debug("%s: found PHY node: %s\n", __func__, ofnode_get_name(node));
213 if (ofnode_read_bool(node, "qca,keep-pll-enabled"))
214 priv->flags |= AR803x_FLAG_KEEP_PLL_ENABLED;
217 * We can't use the regulator framework because the regulator is
218 * a subnode of the PHY. So just read the two properties we are
221 vddio_reg_node = ofnode_find_subnode(node, "vddio-regulator");
222 if (ofnode_valid(vddio_reg_node)) {
223 min_uV = ofnode_read_u32_default(vddio_reg_node,
224 "regulator-min-microvolt", 0);
225 max_uV = ofnode_read_u32_default(vddio_reg_node,
226 "regulator-max-microvolt", 0);
228 if (min_uV != max_uV) {
237 priv->flags |= AR803x_FLAG_RGMII_1V8;
246 * Get the CLK_25M frequency from the device tree. Only XTAL and PLL
247 * sources are supported right now. There is also the possibilty to use
248 * the DSP as frequency reference, this is used for synchronous
251 if (!ofnode_read_u32(node, "qca,clk-out-frequency", &freq)) {
254 sel = AR803x_CLK_25M_25MHZ_XTAL;
257 sel = AR803x_CLK_25M_50MHZ_PLL;
260 sel = AR803x_CLK_25M_62_5MHZ_PLL;
263 sel = AR803x_CLK_25M_125MHZ_PLL;
267 "invalid qca,clk-out-frequency\n");
272 priv->clk_25m_mask |= AR803x_CLK_25M_MASK;
273 priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_MASK, sel);
275 * Fixup for the AR8035 which only has two bits. The two
276 * remaining bits map to the same frequencies.
279 if (phydev->drv->uid == AR8035_PHY_ID) {
280 priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
281 priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
285 if (phydev->drv->uid == AR8031_PHY_ID &&
286 !ofnode_read_u32(node, "qca,clk-out-strength", &strength)) {
288 case AR803X_STRENGTH_FULL:
289 sel = AR803x_CLK_25M_DR_FULL;
291 case AR803X_STRENGTH_HALF:
292 sel = AR803x_CLK_25M_DR_HALF;
294 case AR803X_STRENGTH_QUARTER:
295 sel = AR803x_CLK_25M_DR_QUARTER;
299 "invalid qca,clk-out-strength\n");
303 priv->clk_25m_mask |= AR803x_CLK_25M_DR_MASK;
304 priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_DR_MASK, sel);
307 debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__,
308 priv->flags, priv->clk_25m_reg, priv->clk_25m_mask);
314 static int ar803x_config(struct phy_device *phydev)
318 ret = ar803x_of_init(phydev);
322 ret = ar803x_delay_config(phydev);
326 ret = ar803x_regs_config(phydev);
330 phydev->supported = phydev->drv->features;
332 genphy_config_aneg(phydev);
333 genphy_restart_aneg(phydev);
338 static struct phy_driver AR8021_driver = {
340 .uid = AR8021_PHY_ID,
342 .features = PHY_GBIT_FEATURES,
343 .config = ar8021_config,
344 .startup = genphy_startup,
345 .shutdown = genphy_shutdown,
348 static struct phy_driver AR8031_driver = {
349 .name = "AR8031/AR8033",
350 .uid = AR8031_PHY_ID,
352 .features = PHY_GBIT_FEATURES,
353 .config = ar803x_config,
354 .startup = genphy_startup,
355 .shutdown = genphy_shutdown,
358 static struct phy_driver AR8035_driver = {
360 .uid = AR8035_PHY_ID,
362 .features = PHY_GBIT_FEATURES,
363 .config = ar803x_config,
364 .startup = genphy_startup,
365 .shutdown = genphy_shutdown,
368 int phy_atheros_init(void)
370 phy_register(&AR8021_driver);
371 phy_register(&AR8031_driver);
372 phy_register(&AR8035_driver);