drivers/net/phy/at803x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/at803x.c
   4  *
   5  * Driver for Qualcomm Atheros AR803x PHY
   6  *
   7  * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
   8  */
   9
  10 #include <linux/phy.h>
  11 #include <linux/module.h>
  12 #include <linux/string.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/ethtool_netlink.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/bitfield.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/regulator/of_regulator.h>
  20 #include <linux/regulator/driver.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/phylink.h>
  23 #include <linux/sfp.h>
  24 #include <dt-bindings/net/qca-ar803x.h>
  25
  26 #define AT803X_SPECIFIC_FUNCTION_CONTROL        0x10
  27 #define AT803X_SFC_ASSERT_CRS                   BIT(11)
  28 #define AT803X_SFC_FORCE_LINK                   BIT(10)
  29 #define AT803X_SFC_MDI_CROSSOVER_MODE_M         GENMASK(6, 5)
  30 #define AT803X_SFC_AUTOMATIC_CROSSOVER          0x3
  31 #define AT803X_SFC_MANUAL_MDIX                  0x1
  32 #define AT803X_SFC_MANUAL_MDI                   0x0
  33 #define AT803X_SFC_SQE_TEST                     BIT(2)
  34 #define AT803X_SFC_POLARITY_REVERSAL            BIT(1)
  35 #define AT803X_SFC_DISABLE_JABBER               BIT(0)
  36
  37 #define AT803X_SPECIFIC_STATUS                  0x11
  38 #define AT803X_SS_SPEED_MASK                    GENMASK(15, 14)
  39 #define AT803X_SS_SPEED_1000                    2
  40 #define AT803X_SS_SPEED_100                     1
  41 #define AT803X_SS_SPEED_10                      0
  42 #define AT803X_SS_DUPLEX                        BIT(13)
  43 #define AT803X_SS_SPEED_DUPLEX_RESOLVED         BIT(11)
  44 #define AT803X_SS_MDIX                          BIT(6)
  45
  46 #define QCA808X_SS_SPEED_MASK                   GENMASK(9, 7)
  47 #define QCA808X_SS_SPEED_2500                   4
  48
  49 #define AT803X_INTR_ENABLE                      0x12
  50 #define AT803X_INTR_ENABLE_AUTONEG_ERR          BIT(15)
  51 #define AT803X_INTR_ENABLE_SPEED_CHANGED        BIT(14)
  52 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED       BIT(13)
  53 #define AT803X_INTR_ENABLE_PAGE_RECEIVED        BIT(12)
  54 #define AT803X_INTR_ENABLE_LINK_FAIL            BIT(11)
  55 #define AT803X_INTR_ENABLE_LINK_SUCCESS         BIT(10)
  56 #define AT803X_INTR_ENABLE_LINK_FAIL_BX         BIT(8)
  57 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX      BIT(7)
  58 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE  BIT(5)
  59 #define AT803X_INTR_ENABLE_POLARITY_CHANGED     BIT(1)
  60 #define AT803X_INTR_ENABLE_WOL                  BIT(0)
  61
  62 #define AT803X_INTR_STATUS                      0x13
  63
  64 #define AT803X_SMART_SPEED                      0x14
  65 #define AT803X_SMART_SPEED_ENABLE               BIT(5)
  66 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK     GENMASK(4, 2)
  67 #define AT803X_SMART_SPEED_BYPASS_TIMER         BIT(1)
  68 #define AT803X_CDT                              0x16
  69 #define AT803X_CDT_MDI_PAIR_MASK                GENMASK(9, 8)
  70 #define AT803X_CDT_ENABLE_TEST                  BIT(0)
  71 #define AT803X_CDT_STATUS                       0x1c
  72 #define AT803X_CDT_STATUS_STAT_NORMAL           0
  73 #define AT803X_CDT_STATUS_STAT_SHORT            1
  74 #define AT803X_CDT_STATUS_STAT_OPEN             2
  75 #define AT803X_CDT_STATUS_STAT_FAIL             3
  76 #define AT803X_CDT_STATUS_STAT_MASK             GENMASK(9, 8)
  77 #define AT803X_CDT_STATUS_DELTA_TIME_MASK       GENMASK(7, 0)
  78 #define AT803X_LED_CONTROL                      0x18
  79
  80 #define AT803X_PHY_MMD3_WOL_CTRL                0x8012
  81 #define AT803X_WOL_EN                           BIT(5)
  82 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET         0x804C
  83 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET        0x804B
  84 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET        0x804A
  85 #define AT803X_REG_CHIP_CONFIG                  0x1f
  86 #define AT803X_BT_BX_REG_SEL                    0x8000
  87
  88 #define AT803X_DEBUG_ADDR                       0x1D
  89 #define AT803X_DEBUG_DATA                       0x1E
  90
  91 #define AT803X_MODE_CFG_MASK                    0x0F
  92 #define AT803X_MODE_CFG_BASET_RGMII             0x00
  93 #define AT803X_MODE_CFG_BASET_SGMII             0x01
  94 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM      0x02
  95 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM      0x03
  96 #define AT803X_MODE_CFG_BX1000_CONV_50OHM       0x04
  97 #define AT803X_MODE_CFG_BX1000_CONV_75OHM       0x05
  98 #define AT803X_MODE_CFG_FX100_RGMII_50OHM       0x06
  99 #define AT803X_MODE_CFG_FX100_CONV_50OHM        0x07
 100 #define AT803X_MODE_CFG_RGMII_AUTO_MDET         0x0B
 101 #define AT803X_MODE_CFG_FX100_RGMII_75OHM       0x0E
 102 #define AT803X_MODE_CFG_FX100_CONV_75OHM        0x0F
 103
 104 #define AT803X_PSSR                             0x11    /*PHY-Specific Status Register*/
 105 #define AT803X_PSSR_MR_AN_COMPLETE              0x0200
 106
 107 #define AT803X_DEBUG_ANALOG_TEST_CTRL           0x00
 108 #define QCA8327_DEBUG_MANU_CTRL_EN              BIT(2)
 109 #define QCA8337_DEBUG_MANU_CTRL_EN              GENMASK(3, 2)
 110 #define AT803X_DEBUG_RX_CLK_DLY_EN              BIT(15)
 111
 112 #define AT803X_DEBUG_SYSTEM_CTRL_MODE           0x05
 113 #define AT803X_DEBUG_TX_CLK_DLY_EN              BIT(8)
 114
 115 #define AT803X_DEBUG_REG_HIB_CTRL               0x0b
 116 #define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U     BIT(10)
 117 #define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE   BIT(13)
 118
 119 #define AT803X_DEBUG_REG_3C                     0x3C
 120
 121 #define AT803X_DEBUG_REG_GREEN                  0x3D
 122 #define   AT803X_DEBUG_GATE_CLK_IN1000          BIT(6)
 123
 124 #define AT803X_DEBUG_REG_1F                     0x1F
 125 #define AT803X_DEBUG_PLL_ON                     BIT(2)
 126 #define AT803X_DEBUG_RGMII_1V8                  BIT(3)
 127
 128 #define MDIO_AZ_DEBUG                           0x800D
 129
 130 /* AT803x supports either the XTAL input pad, an internal PLL or the
 131  * DSP as clock reference for the clock output pad. The XTAL reference
 132  * is only used for 25 MHz output, all other frequencies need the PLL.
 133  * The DSP as a clock reference is used in synchronous ethernet
 134  * applications.
 135  *
 136  * By default the PLL is only enabled if there is a link. Otherwise
 137  * the PHY will go into low power state and disabled the PLL. You can
 138  * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
 139  * enabled.
 140  */
 141 #define AT803X_MMD7_CLK25M                      0x8016
 142 #define AT803X_CLK_OUT_MASK                     GENMASK(4, 2)
 143 #define AT803X_CLK_OUT_25MHZ_XTAL               0
 144 #define AT803X_CLK_OUT_25MHZ_DSP                1
 145 #define AT803X_CLK_OUT_50MHZ_PLL                2
 146 #define AT803X_CLK_OUT_50MHZ_DSP                3
 147 #define AT803X_CLK_OUT_62_5MHZ_PLL              4
 148 #define AT803X_CLK_OUT_62_5MHZ_DSP              5
 149 #define AT803X_CLK_OUT_125MHZ_PLL               6
 150 #define AT803X_CLK_OUT_125MHZ_DSP               7
 151
 152 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
 153  * but doesn't support choosing between XTAL/PLL and DSP.
 154  */
 155 #define AT8035_CLK_OUT_MASK                     GENMASK(4, 3)
 156
 157 #define AT803X_CLK_OUT_STRENGTH_MASK            GENMASK(8, 7)
 158 #define AT803X_CLK_OUT_STRENGTH_FULL            0
 159 #define AT803X_CLK_OUT_STRENGTH_HALF            1
 160 #define AT803X_CLK_OUT_STRENGTH_QUARTER         2
 161
 162 #define AT803X_DEFAULT_DOWNSHIFT                5
 163 #define AT803X_MIN_DOWNSHIFT                    2
 164 #define AT803X_MAX_DOWNSHIFT                    9
 165
 166 #define AT803X_MMD3_SMARTEEE_CTL1               0x805b
 167 #define AT803X_MMD3_SMARTEEE_CTL2               0x805c
 168 #define AT803X_MMD3_SMARTEEE_CTL3               0x805d
 169 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN        BIT(8)
 170
 171 #define ATH9331_PHY_ID                          0x004dd041
 172 #define ATH8030_PHY_ID                          0x004dd076
 173 #define ATH8031_PHY_ID                          0x004dd074
 174 #define ATH8032_PHY_ID                          0x004dd023
 175 #define ATH8035_PHY_ID                          0x004dd072
 176 #define AT8030_PHY_ID_MASK                      0xffffffef
 177
 178 #define QCA8081_PHY_ID                          0x004dd101
 179
 180 #define QCA8327_A_PHY_ID                        0x004dd033
 181 #define QCA8327_B_PHY_ID                        0x004dd034
 182 #define QCA8337_PHY_ID                          0x004dd036
 183 #define QCA9561_PHY_ID                          0x004dd042
 184 #define QCA8K_PHY_ID_MASK                       0xffffffff
 185
 186 #define QCA8K_DEVFLAGS_REVISION_MASK            GENMASK(2, 0)
 187
 188 #define AT803X_PAGE_FIBER                       0
 189 #define AT803X_PAGE_COPPER                      1
 190
 191 /* don't turn off internal PLL */
 192 #define AT803X_KEEP_PLL_ENABLED                 BIT(0)
 193 #define AT803X_DISABLE_SMARTEEE                 BIT(1)
 194
 195 /* ADC threshold */
 196 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD         0x2c80
 197 #define QCA808X_ADC_THRESHOLD_MASK              GENMASK(7, 0)
 198 #define QCA808X_ADC_THRESHOLD_80MV              0
 199 #define QCA808X_ADC_THRESHOLD_100MV             0xf0
 200 #define QCA808X_ADC_THRESHOLD_200MV             0x0f
 201 #define QCA808X_ADC_THRESHOLD_300MV             0xff
 202
 203 /* CLD control */
 204 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7         0x8007
 205 #define QCA808X_8023AZ_AFE_CTRL_MASK            GENMASK(8, 4)
 206 #define QCA808X_8023AZ_AFE_EN                   0x90
 207
 208 /* AZ control */
 209 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL       0x8008
 210 #define QCA808X_MMD3_AZ_TRAINING_VAL            0x1c32
 211
 212 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB     0x8014
 213 #define QCA808X_MSE_THRESHOLD_20DB_VALUE        0x529
 214
 215 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB     0x800E
 216 #define QCA808X_MSE_THRESHOLD_17DB_VALUE        0x341
 217
 218 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB     0x801E
 219 #define QCA808X_MSE_THRESHOLD_27DB_VALUE        0x419
 220
 221 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB     0x8020
 222 #define QCA808X_MSE_THRESHOLD_28DB_VALUE        0x341
 223
 224 #define QCA808X_PHY_MMD7_TOP_OPTION1            0x901c
 225 #define QCA808X_TOP_OPTION1_DATA                0x0
 226
 227 #define QCA808X_PHY_MMD3_DEBUG_1                0xa100
 228 #define QCA808X_MMD3_DEBUG_1_VALUE              0x9203
 229 #define QCA808X_PHY_MMD3_DEBUG_2                0xa101
 230 #define QCA808X_MMD3_DEBUG_2_VALUE              0x48ad
 231 #define QCA808X_PHY_MMD3_DEBUG_3                0xa103
 232 #define QCA808X_MMD3_DEBUG_3_VALUE              0x1698
 233 #define QCA808X_PHY_MMD3_DEBUG_4                0xa105
 234 #define QCA808X_MMD3_DEBUG_4_VALUE              0x8001
 235 #define QCA808X_PHY_MMD3_DEBUG_5                0xa106
 236 #define QCA808X_MMD3_DEBUG_5_VALUE              0x1111
 237 #define QCA808X_PHY_MMD3_DEBUG_6                0xa011
 238 #define QCA808X_MMD3_DEBUG_6_VALUE              0x5f85
 239
 240 /* master/slave seed config */
 241 #define QCA808X_PHY_DEBUG_LOCAL_SEED            9
 242 #define QCA808X_MASTER_SLAVE_SEED_ENABLE        BIT(1)
 243 #define QCA808X_MASTER_SLAVE_SEED_CFG           GENMASK(12, 2)
 244 #define QCA808X_MASTER_SLAVE_SEED_RANGE         0x32
 245
 246 /* Hibernation yields lower power consumpiton in contrast with normal operation mode.
 247  * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
 248  */
 249 #define QCA808X_DBG_AN_TEST                     0xb
 250 #define QCA808X_HIBERNATION_EN                  BIT(15)
 251
 252 #define QCA808X_CDT_ENABLE_TEST                 BIT(15)
 253 #define QCA808X_CDT_INTER_CHECK_DIS             BIT(13)
 254 #define QCA808X_CDT_LENGTH_UNIT                 BIT(10)
 255
 256 #define QCA808X_MMD3_CDT_STATUS                 0x8064
 257 #define QCA808X_MMD3_CDT_DIAG_PAIR_A            0x8065
 258 #define QCA808X_MMD3_CDT_DIAG_PAIR_B            0x8066
 259 #define QCA808X_MMD3_CDT_DIAG_PAIR_C            0x8067
 260 #define QCA808X_MMD3_CDT_DIAG_PAIR_D            0x8068
 261 #define QCA808X_CDT_DIAG_LENGTH                 GENMASK(7, 0)
 262
 263 #define QCA808X_CDT_CODE_PAIR_A                 GENMASK(15, 12)
 264 #define QCA808X_CDT_CODE_PAIR_B                 GENMASK(11, 8)
 265 #define QCA808X_CDT_CODE_PAIR_C                 GENMASK(7, 4)
 266 #define QCA808X_CDT_CODE_PAIR_D                 GENMASK(3, 0)
 267 #define QCA808X_CDT_STATUS_STAT_FAIL            0
 268 #define QCA808X_CDT_STATUS_STAT_NORMAL          1
 269 #define QCA808X_CDT_STATUS_STAT_OPEN            2
 270 #define QCA808X_CDT_STATUS_STAT_SHORT           3
 271
 272 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
 273 MODULE_AUTHOR("Matus Ujhelyi");
 274 MODULE_LICENSE("GPL");
 275
 276 enum stat_access_type {
 277         PHY,
 278         MMD
 279 };
 280
 281 struct at803x_hw_stat {
 282         const char *string;
 283         u8 reg;
 284         u32 mask;
 285         enum stat_access_type access_type;
 286 };
 287
 288 static struct at803x_hw_stat at803x_hw_stats[] = {
 289         { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
 290         { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
 291         { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
 292 };
 293
 294 struct at803x_priv {
 295         int flags;
 296         u16 clk_25m_reg;
 297         u16 clk_25m_mask;
 298         u8 smarteee_lpi_tw_1g;
 299         u8 smarteee_lpi_tw_100m;
 300         bool is_fiber;
 301         bool is_1000basex;
 302         struct regulator_dev *vddio_rdev;
 303         struct regulator_dev *vddh_rdev;
 304         struct regulator *vddio;
 305         u64 stats[ARRAY_SIZE(at803x_hw_stats)];
 306 };
 307
 308 struct at803x_context {
 309         u16 bmcr;
 310         u16 advertise;
 311         u16 control1000;
 312         u16 int_enable;
 313         u16 smart_speed;
 314         u16 led_control;
 315 };
 316
 317 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
 318 {
 319         int ret;
 320
 321         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
 322         if (ret < 0)
 323                 return ret;
 324
 325         return phy_write(phydev, AT803X_DEBUG_DATA, data);
 326 }
 327
 328 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
 329 {
 330         int ret;
 331
 332         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
 333         if (ret < 0)
 334                 return ret;
 335
 336         return phy_read(phydev, AT803X_DEBUG_DATA);
 337 }
 338
 339 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
 340                                  u16 clear, u16 set)
 341 {
 342         u16 val;
 343         int ret;
 344
 345         ret = at803x_debug_reg_read(phydev, reg);
 346         if (ret < 0)
 347                 return ret;
 348
 349         val = ret & 0xffff;
 350         val &= ~clear;
 351         val |= set;
 352
 353         return phy_write(phydev, AT803X_DEBUG_DATA, val);
 354 }
 355
 356 static int at803x_write_page(struct phy_device *phydev, int page)
 357 {
 358         int mask;
 359         int set;
 360
 361         if (page == AT803X_PAGE_COPPER) {
 362                 set = AT803X_BT_BX_REG_SEL;
 363                 mask = 0;
 364         } else {
 365                 set = 0;
 366                 mask = AT803X_BT_BX_REG_SEL;
 367         }
 368
 369         return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
 370 }
 371
 372 static int at803x_read_page(struct phy_device *phydev)
 373 {
 374         int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 375
 376         if (ccr < 0)
 377                 return ccr;
 378
 379         if (ccr & AT803X_BT_BX_REG_SEL)
 380                 return AT803X_PAGE_COPPER;
 381
 382         return AT803X_PAGE_FIBER;
 383 }
 384
 385 static int at803x_enable_rx_delay(struct phy_device *phydev)
 386 {
 387         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
 388                                      AT803X_DEBUG_RX_CLK_DLY_EN);
 389 }
 390
 391 static int at803x_enable_tx_delay(struct phy_device *phydev)
 392 {
 393         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
 394                                      AT803X_DEBUG_TX_CLK_DLY_EN);
 395 }
 396
 397 static int at803x_disable_rx_delay(struct phy_device *phydev)
 398 {
 399         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
 400                                      AT803X_DEBUG_RX_CLK_DLY_EN, 0);
 401 }
 402
 403 static int at803x_disable_tx_delay(struct phy_device *phydev)
 404 {
 405         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
 406                                      AT803X_DEBUG_TX_CLK_DLY_EN, 0);
 407 }
 408
 409 /* save relevant PHY registers to private copy */
 410 static void at803x_context_save(struct phy_device *phydev,
 411                                 struct at803x_context *context)
 412 {
 413         context->bmcr = phy_read(phydev, MII_BMCR);
 414         context->advertise = phy_read(phydev, MII_ADVERTISE);
 415         context->control1000 = phy_read(phydev, MII_CTRL1000);
 416         context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
 417         context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
 418         context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
 419 }
 420
 421 /* restore relevant PHY registers from private copy */
 422 static void at803x_context_restore(struct phy_device *phydev,
 423                                    const struct at803x_context *context)
 424 {
 425         phy_write(phydev, MII_BMCR, context->bmcr);
 426         phy_write(phydev, MII_ADVERTISE, context->advertise);
 427         phy_write(phydev, MII_CTRL1000, context->control1000);
 428         phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
 429         phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
 430         phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
 431 }
 432
 433 static int at803x_set_wol(struct phy_device *phydev,
 434                           struct ethtool_wolinfo *wol)
 435 {
 436         struct net_device *ndev = phydev->attached_dev;
 437         const u8 *mac;
 438         int ret, irq_enabled;
 439         unsigned int i;
 440         static const unsigned int offsets[] = {
 441                 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
 442                 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
 443                 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
 444         };
 445
 446         if (!ndev)
 447                 return -ENODEV;
 448
 449         if (wol->wolopts & WAKE_MAGIC) {
 450                 mac = (const u8 *) ndev->dev_addr;
 451
 452                 if (!is_valid_ether_addr(mac))
 453                         return -EINVAL;
 454
 455                 for (i = 0; i < 3; i++)
 456                         phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
 457                                       mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
 458
 459                 /* Enable WOL function */
 460                 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,
 461                                 0, AT803X_WOL_EN);
 462                 if (ret)
 463                         return ret;
 464                 /* Enable WOL interrupt */
 465                 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
 466                 if (ret)
 467                         return ret;
 468         } else {
 469                 /* Disable WoL function */
 470                 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,
 471                                 AT803X_WOL_EN, 0);
 472                 if (ret)
 473                         return ret;
 474                 /* Disable WOL interrupt */
 475                 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
 476                 if (ret)
 477                         return ret;
 478         }
 479
 480         /* Clear WOL status */
 481         ret = phy_read(phydev, AT803X_INTR_STATUS);
 482         if (ret < 0)
 483                 return ret;
 484
 485         /* Check if there are other interrupts except for WOL triggered when PHY is
 486          * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
 487          * be passed up to the interrupt PIN.
 488          */
 489         irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
 490         if (irq_enabled < 0)
 491                 return irq_enabled;
 492
 493         irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
 494         if (ret & irq_enabled && !phy_polling_mode(phydev))
 495                 phy_trigger_machine(phydev);
 496
 497         return 0;
 498 }
 499
 500 static void at803x_get_wol(struct phy_device *phydev,
 501                            struct ethtool_wolinfo *wol)
 502 {
 503         int value;
 504
 505         wol->supported = WAKE_MAGIC;
 506         wol->wolopts = 0;
 507
 508         value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL);
 509         if (value < 0)
 510                 return;
 511
 512         if (value & AT803X_WOL_EN)
 513                 wol->wolopts |= WAKE_MAGIC;
 514 }
 515
 516 static int at803x_get_sset_count(struct phy_device *phydev)
 517 {
 518         return ARRAY_SIZE(at803x_hw_stats);
 519 }
 520
 521 static void at803x_get_strings(struct phy_device *phydev, u8 *data)
 522 {
 523         int i;
 524
 525         for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
 526                 strscpy(data + i * ETH_GSTRING_LEN,
 527                         at803x_hw_stats[i].string, ETH_GSTRING_LEN);
 528         }
 529 }
 530
 531 static u64 at803x_get_stat(struct phy_device *phydev, int i)
 532 {
 533         struct at803x_hw_stat stat = at803x_hw_stats[i];
 534         struct at803x_priv *priv = phydev->priv;
 535         int val;
 536         u64 ret;
 537
 538         if (stat.access_type == MMD)
 539                 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
 540         else
 541                 val = phy_read(phydev, stat.reg);
 542
 543         if (val < 0) {
 544                 ret = U64_MAX;
 545         } else {
 546                 val = val & stat.mask;
 547                 priv->stats[i] += val;
 548                 ret = priv->stats[i];
 549         }
 550
 551         return ret;
 552 }
 553
 554 static void at803x_get_stats(struct phy_device *phydev,
 555                              struct ethtool_stats *stats, u64 *data)
 556 {
 557         int i;
 558
 559         for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
 560                 data[i] = at803x_get_stat(phydev, i);
 561 }
 562
 563 static int at803x_suspend(struct phy_device *phydev)
 564 {
 565         int value;
 566         int wol_enabled;
 567
 568         value = phy_read(phydev, AT803X_INTR_ENABLE);
 569         wol_enabled = value & AT803X_INTR_ENABLE_WOL;
 570
 571         if (wol_enabled)
 572                 value = BMCR_ISOLATE;
 573         else
 574                 value = BMCR_PDOWN;
 575
 576         phy_modify(phydev, MII_BMCR, 0, value);
 577
 578         return 0;
 579 }
 580
 581 static int at803x_resume(struct phy_device *phydev)
 582 {
 583         return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
 584 }
 585
 586 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
 587                                             unsigned int selector)
 588 {
 589         struct phy_device *phydev = rdev_get_drvdata(rdev);
 590
 591         if (selector)
 592                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 593                                              0, AT803X_DEBUG_RGMII_1V8);
 594         else
 595                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 596                                              AT803X_DEBUG_RGMII_1V8, 0);
 597 }
 598
 599 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
 600 {
 601         struct phy_device *phydev = rdev_get_drvdata(rdev);
 602         int val;
 603
 604         val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
 605         if (val < 0)
 606                 return val;
 607
 608         return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
 609 }
 610
 611 static const struct regulator_ops vddio_regulator_ops = {
 612         .list_voltage = regulator_list_voltage_table,
 613         .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
 614         .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
 615 };
 616
 617 static const unsigned int vddio_voltage_table[] = {
 618         1500000,
 619         1800000,
 620 };
 621
 622 static const struct regulator_desc vddio_desc = {
 623         .name = "vddio",
 624         .of_match = of_match_ptr("vddio-regulator"),
 625         .n_voltages = ARRAY_SIZE(vddio_voltage_table),
 626         .volt_table = vddio_voltage_table,
 627         .ops = &vddio_regulator_ops,
 628         .type = REGULATOR_VOLTAGE,
 629         .owner = THIS_MODULE,
 630 };
 631
 632 static const struct regulator_ops vddh_regulator_ops = {
 633 };
 634
 635 static const struct regulator_desc vddh_desc = {
 636         .name = "vddh",
 637         .of_match = of_match_ptr("vddh-regulator"),
 638         .n_voltages = 1,
 639         .fixed_uV = 2500000,
 640         .ops = &vddh_regulator_ops,
 641         .type = REGULATOR_VOLTAGE,
 642         .owner = THIS_MODULE,
 643 };
 644
 645 static int at8031_register_regulators(struct phy_device *phydev)
 646 {
 647         struct at803x_priv *priv = phydev->priv;
 648         struct device *dev = &phydev->mdio.dev;
 649         struct regulator_config config = { };
 650
 651         config.dev = dev;
 652         config.driver_data = phydev;
 653
 654         priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
 655         if (IS_ERR(priv->vddio_rdev)) {
 656                 phydev_err(phydev, "failed to register VDDIO regulator\n");
 657                 return PTR_ERR(priv->vddio_rdev);
 658         }
 659
 660         priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
 661         if (IS_ERR(priv->vddh_rdev)) {
 662                 phydev_err(phydev, "failed to register VDDH regulator\n");
 663                 return PTR_ERR(priv->vddh_rdev);
 664         }
 665
 666         return 0;
 667 }
 668
 669 static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
 670 {
 671         struct phy_device *phydev = upstream;
 672         __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
 673         __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
 674         phy_interface_t iface;
 675
 676         linkmode_zero(phy_support);
 677         phylink_set(phy_support, 1000baseX_Full);
 678         phylink_set(phy_support, 1000baseT_Full);
 679         phylink_set(phy_support, Autoneg);
 680         phylink_set(phy_support, Pause);
 681         phylink_set(phy_support, Asym_Pause);
 682
 683         linkmode_zero(sfp_support);
 684         sfp_parse_support(phydev->sfp_bus, id, sfp_support);
 685         /* Some modules support 10G modes as well as others we support.
 686          * Mask out non-supported modes so the correct interface is picked.
 687          */
 688         linkmode_and(sfp_support, phy_support, sfp_support);
 689
 690         if (linkmode_empty(sfp_support)) {
 691                 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
 692                 return -EINVAL;
 693         }
 694
 695         iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
 696
 697         /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
 698          * interface for use with SFP modules.
 699          * However, some copper modules detected as having a preferred SGMII
 700          * interface do default to and function in 1000Base-X mode, so just
 701          * print a warning and allow such modules, as they may have some chance
 702          * of working.
 703          */
 704         if (iface == PHY_INTERFACE_MODE_SGMII)
 705                 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
 706         else if (iface != PHY_INTERFACE_MODE_1000BASEX)
 707                 return -EINVAL;
 708
 709         return 0;
 710 }
 711
 712 static const struct sfp_upstream_ops at803x_sfp_ops = {
 713         .attach = phy_sfp_attach,
 714         .detach = phy_sfp_detach,
 715         .module_insert = at803x_sfp_insert,
 716 };
 717
 718 static int at803x_parse_dt(struct phy_device *phydev)
 719 {
 720         struct device_node *node = phydev->mdio.dev.of_node;
 721         struct at803x_priv *priv = phydev->priv;
 722         u32 freq, strength, tw;
 723         unsigned int sel;
 724         int ret;
 725
 726         if (!IS_ENABLED(CONFIG_OF_MDIO))
 727                 return 0;
 728
 729         if (of_property_read_bool(node, "qca,disable-smarteee"))
 730                 priv->flags |= AT803X_DISABLE_SMARTEEE;
 731
 732         if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
 733                 if (!tw || tw > 255) {
 734                         phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
 735                         return -EINVAL;
 736                 }
 737                 priv->smarteee_lpi_tw_1g = tw;
 738         }
 739
 740         if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
 741                 if (!tw || tw > 255) {
 742                         phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
 743                         return -EINVAL;
 744                 }
 745                 priv->smarteee_lpi_tw_100m = tw;
 746         }
 747
 748         ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
 749         if (!ret) {
 750                 switch (freq) {
 751                 case 25000000:
 752                         sel = AT803X_CLK_OUT_25MHZ_XTAL;
 753                         break;
 754                 case 50000000:
 755                         sel = AT803X_CLK_OUT_50MHZ_PLL;
 756                         break;
 757                 case 62500000:
 758                         sel = AT803X_CLK_OUT_62_5MHZ_PLL;
 759                         break;
 760                 case 125000000:
 761                         sel = AT803X_CLK_OUT_125MHZ_PLL;
 762                         break;
 763                 default:
 764                         phydev_err(phydev, "invalid qca,clk-out-frequency\n");
 765                         return -EINVAL;
 766                 }
 767
 768                 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
 769                 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
 770
 771                 /* Fixup for the AR8030/AR8035. This chip has another mask and
 772                  * doesn't support the DSP reference. Eg. the lowest bit of the
 773                  * mask. The upper two bits select the same frequencies. Mask
 774                  * the lowest bit here.
 775                  *
 776                  * Warning:
 777                  *   There was no datasheet for the AR8030 available so this is
 778                  *   just a guess. But the AR8035 is listed as pin compatible
 779                  *   to the AR8030 so there might be a good chance it works on
 780                  *   the AR8030 too.
 781                  */
 782                 if (phydev->drv->phy_id == ATH8030_PHY_ID ||
 783                     phydev->drv->phy_id == ATH8035_PHY_ID) {
 784                         priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
 785                         priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
 786                 }
 787         }
 788
 789         ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
 790         if (!ret) {
 791                 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
 792                 switch (strength) {
 793                 case AR803X_STRENGTH_FULL:
 794                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
 795                         break;
 796                 case AR803X_STRENGTH_HALF:
 797                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
 798                         break;
 799                 case AR803X_STRENGTH_QUARTER:
 800                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
 801                         break;
 802                 default:
 803                         phydev_err(phydev, "invalid qca,clk-out-strength\n");
 804                         return -EINVAL;
 805                 }
 806         }
 807
 808         /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
 809          * options.
 810          */
 811         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
 812                 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
 813                         priv->flags |= AT803X_KEEP_PLL_ENABLED;
 814
 815                 ret = at8031_register_regulators(phydev);
 816                 if (ret < 0)
 817                         return ret;
 818
 819                 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
 820                                                           "vddio");
 821                 if (IS_ERR(priv->vddio)) {
 822                         phydev_err(phydev, "failed to get VDDIO regulator\n");
 823                         return PTR_ERR(priv->vddio);
 824                 }
 825
 826                 /* Only AR8031/8033 support 1000Base-X for SFP modules */
 827                 ret = phy_sfp_probe(phydev, &at803x_sfp_ops);
 828                 if (ret < 0)
 829                         return ret;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int at803x_probe(struct phy_device *phydev)
 836 {
 837         struct device *dev = &phydev->mdio.dev;
 838         struct at803x_priv *priv;
 839         int ret;
 840
 841         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 842         if (!priv)
 843                 return -ENOMEM;
 844
 845         phydev->priv = priv;
 846
 847         ret = at803x_parse_dt(phydev);
 848         if (ret)
 849                 return ret;
 850
 851         if (priv->vddio) {
 852                 ret = regulator_enable(priv->vddio);
 853                 if (ret < 0)
 854                         return ret;
 855         }
 856
 857         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
 858                 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 859                 int mode_cfg;
 860
 861                 if (ccr < 0)
 862                         goto err;
 863                 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
 864
 865                 switch (mode_cfg) {
 866                 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
 867                 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
 868                         priv->is_1000basex = true;
 869                         fallthrough;
 870                 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
 871                 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
 872                         priv->is_fiber = true;
 873                         break;
 874                 }
 875         }
 876
 877         return 0;
 878
 879 err:
 880         if (priv->vddio)
 881                 regulator_disable(priv->vddio);
 882
 883         return ret;
 884 }
 885
 886 static void at803x_remove(struct phy_device *phydev)
 887 {
 888         struct at803x_priv *priv = phydev->priv;
 889
 890         if (priv->vddio)
 891                 regulator_disable(priv->vddio);
 892 }
 893
 894 static int at803x_get_features(struct phy_device *phydev)
 895 {
 896         struct at803x_priv *priv = phydev->priv;
 897         int err;
 898
 899         err = genphy_read_abilities(phydev);
 900         if (err)
 901                 return err;
 902
 903         if (phydev->drv->phy_id == QCA8081_PHY_ID) {
 904                 err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE);
 905                 if (err < 0)
 906                         return err;
 907
 908                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported,
 909                                 err & MDIO_PMA_NG_EXTABLE_2_5GBT);
 910         }
 911
 912         if (phydev->drv->phy_id != ATH8031_PHY_ID)
 913                 return 0;
 914
 915         /* AR8031/AR8033 have different status registers
 916          * for copper and fiber operation. However, the
 917          * extended status register is the same for both
 918          * operation modes.
 919          *
 920          * As a result of that, ESTATUS_1000_XFULL is set
 921          * to 1 even when operating in copper TP mode.
 922          *
 923          * Remove this mode from the supported link modes
 924          * when not operating in 1000BaseX mode.
 925          */
 926         if (!priv->is_1000basex)
 927                 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 928                                    phydev->supported);
 929
 930         return 0;
 931 }
 932
 933 static int at803x_smarteee_config(struct phy_device *phydev)
 934 {
 935         struct at803x_priv *priv = phydev->priv;
 936         u16 mask = 0, val = 0;
 937         int ret;
 938
 939         if (priv->flags & AT803X_DISABLE_SMARTEEE)
 940                 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
 941                                       AT803X_MMD3_SMARTEEE_CTL3,
 942                                       AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
 943
 944         if (priv->smarteee_lpi_tw_1g) {
 945                 mask |= 0xff00;
 946                 val |= priv->smarteee_lpi_tw_1g << 8;
 947         }
 948         if (priv->smarteee_lpi_tw_100m) {
 949                 mask |= 0x00ff;
 950                 val |= priv->smarteee_lpi_tw_100m;
 951         }
 952         if (!mask)
 953                 return 0;
 954
 955         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
 956                              mask, val);
 957         if (ret)
 958                 return ret;
 959
 960         return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
 961                               AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
 962                               AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
 963 }
 964
 965 static int at803x_clk_out_config(struct phy_device *phydev)
 966 {
 967         struct at803x_priv *priv = phydev->priv;
 968
 969         if (!priv->clk_25m_mask)
 970                 return 0;
 971
 972         return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
 973                               priv->clk_25m_mask, priv->clk_25m_reg);
 974 }
 975
 976 static int at8031_pll_config(struct phy_device *phydev)
 977 {
 978         struct at803x_priv *priv = phydev->priv;
 979
 980         /* The default after hardware reset is PLL OFF. After a soft reset, the
 981          * values are retained.
 982          */
 983         if (priv->flags & AT803X_KEEP_PLL_ENABLED)
 984                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 985                                              0, AT803X_DEBUG_PLL_ON);
 986         else
 987                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 988                                              AT803X_DEBUG_PLL_ON, 0);
 989 }
 990
 991 static int at803x_config_init(struct phy_device *phydev)
 992 {
 993         struct at803x_priv *priv = phydev->priv;
 994         int ret;
 995
 996         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
 997                 /* Some bootloaders leave the fiber page selected.
 998                  * Switch to the appropriate page (fiber or copper), as otherwise we
 999                  * read the PHY capabilities from the wrong page.
1000                  */
1001                 phy_lock_mdio_bus(phydev);
1002                 ret = at803x_write_page(phydev,
1003                                         priv->is_fiber ? AT803X_PAGE_FIBER :
1004                                                          AT803X_PAGE_COPPER);
1005                 phy_unlock_mdio_bus(phydev);
1006                 if (ret)
1007                         return ret;
1008
1009                 ret = at8031_pll_config(phydev);
1010                 if (ret < 0)
1011                         return ret;
1012         }
1013
1014         /* The RX and TX delay default is:
1015          *   after HW reset: RX delay enabled and TX delay disabled
1016          *   after SW reset: RX delay enabled, while TX delay retains the
1017          *   value before reset.
1018          */
1019         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1020             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1021                 ret = at803x_enable_rx_delay(phydev);
1022         else
1023                 ret = at803x_disable_rx_delay(phydev);
1024         if (ret < 0)
1025                 return ret;
1026
1027         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1028             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1029                 ret = at803x_enable_tx_delay(phydev);
1030         else
1031                 ret = at803x_disable_tx_delay(phydev);
1032         if (ret < 0)
1033                 return ret;
1034
1035         ret = at803x_smarteee_config(phydev);
1036         if (ret < 0)
1037                 return ret;
1038
1039         ret = at803x_clk_out_config(phydev);
1040         if (ret < 0)
1041                 return ret;
1042
1043         /* Ar803x extended next page bit is enabled by default. Cisco
1044          * multigig switches read this bit and attempt to negotiate 10Gbps
1045          * rates even if the next page bit is disabled. This is incorrect
1046          * behaviour but we still need to accommodate it. XNP is only needed
1047          * for 10Gbps support, so disable XNP.
1048          */
1049         return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
1050 }
1051
1052 static int at803x_ack_interrupt(struct phy_device *phydev)
1053 {
1054         int err;
1055
1056         err = phy_read(phydev, AT803X_INTR_STATUS);
1057
1058         return (err < 0) ? err : 0;
1059 }
1060
1061 static int at803x_config_intr(struct phy_device *phydev)
1062 {
1063         struct at803x_priv *priv = phydev->priv;
1064         int err;
1065         int value;
1066
1067         value = phy_read(phydev, AT803X_INTR_ENABLE);
1068
1069         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1070                 /* Clear any pending interrupts */
1071                 err = at803x_ack_interrupt(phydev);
1072                 if (err)
1073                         return err;
1074
1075                 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
1076                 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
1077                 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
1078                 value |= AT803X_INTR_ENABLE_LINK_FAIL;
1079                 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
1080                 if (priv->is_fiber) {
1081                         value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
1082                         value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
1083                 }
1084
1085                 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
1086         } else {
1087                 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
1088                 if (err)
1089                         return err;
1090
1091                 /* Clear any pending interrupts */
1092                 err = at803x_ack_interrupt(phydev);
1093         }
1094
1095         return err;
1096 }
1097
1098 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
1099 {
1100         int irq_status, int_enabled;
1101
1102         irq_status = phy_read(phydev, AT803X_INTR_STATUS);
1103         if (irq_status < 0) {
1104                 phy_error(phydev);
1105                 return IRQ_NONE;
1106         }
1107
1108         /* Read the current enabled interrupts */
1109         int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
1110         if (int_enabled < 0) {
1111                 phy_error(phydev);
1112                 return IRQ_NONE;
1113         }
1114
1115         /* See if this was one of our enabled interrupts */
1116         if (!(irq_status & int_enabled))
1117                 return IRQ_NONE;
1118
1119         phy_trigger_machine(phydev);
1120
1121         return IRQ_HANDLED;
1122 }
1123
1124 static void at803x_link_change_notify(struct phy_device *phydev)
1125 {
1126         /*
1127          * Conduct a hardware reset for AT8030 every time a link loss is
1128          * signalled. This is necessary to circumvent a hardware bug that
1129          * occurs when the cable is unplugged while TX packets are pending
1130          * in the FIFO. In such cases, the FIFO enters an error mode it
1131          * cannot recover from by software.
1132          */
1133         if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
1134                 struct at803x_context context;
1135
1136                 at803x_context_save(phydev, &context);
1137
1138                 phy_device_reset(phydev, 1);
1139                 msleep(1);
1140                 phy_device_reset(phydev, 0);
1141                 msleep(1);
1142
1143                 at803x_context_restore(phydev, &context);
1144
1145                 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
1146         }
1147 }
1148
1149 static int at803x_read_specific_status(struct phy_device *phydev)
1150 {
1151         int ss;
1152
1153         /* Read the AT8035 PHY-Specific Status register, which indicates the
1154          * speed and duplex that the PHY is actually using, irrespective of
1155          * whether we are in autoneg mode or not.
1156          */
1157         ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
1158         if (ss < 0)
1159                 return ss;
1160
1161         if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
1162                 int sfc, speed;
1163
1164                 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
1165                 if (sfc < 0)
1166                         return sfc;
1167
1168                 /* qca8081 takes the different bits for speed value from at803x */
1169                 if (phydev->drv->phy_id == QCA8081_PHY_ID)
1170                         speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss);
1171                 else
1172                         speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss);
1173
1174                 switch (speed) {
1175                 case AT803X_SS_SPEED_10:
1176                         phydev->speed = SPEED_10;
1177                         break;
1178                 case AT803X_SS_SPEED_100:
1179                         phydev->speed = SPEED_100;
1180                         break;
1181                 case AT803X_SS_SPEED_1000:
1182                         phydev->speed = SPEED_1000;
1183                         break;
1184                 case QCA808X_SS_SPEED_2500:
1185                         phydev->speed = SPEED_2500;
1186                         break;
1187                 }
1188                 if (ss & AT803X_SS_DUPLEX)
1189                         phydev->duplex = DUPLEX_FULL;
1190                 else
1191                         phydev->duplex = DUPLEX_HALF;
1192
1193                 if (ss & AT803X_SS_MDIX)
1194                         phydev->mdix = ETH_TP_MDI_X;
1195                 else
1196                         phydev->mdix = ETH_TP_MDI;
1197
1198                 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
1199                 case AT803X_SFC_MANUAL_MDI:
1200                         phydev->mdix_ctrl = ETH_TP_MDI;
1201                         break;
1202                 case AT803X_SFC_MANUAL_MDIX:
1203                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1204                         break;
1205                 case AT803X_SFC_AUTOMATIC_CROSSOVER:
1206                         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1207                         break;
1208                 }
1209         }
1210
1211         return 0;
1212 }
1213
1214 static int at803x_read_status(struct phy_device *phydev)
1215 {
1216         struct at803x_priv *priv = phydev->priv;
1217         int err, old_link = phydev->link;
1218
1219         if (priv->is_1000basex)
1220                 return genphy_c37_read_status(phydev);
1221
1222         /* Update the link, but return if there was an error */
1223         err = genphy_update_link(phydev);
1224         if (err)
1225                 return err;
1226
1227         /* why bother the PHY if nothing can have changed */
1228         if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
1229                 return 0;
1230
1231         phydev->speed = SPEED_UNKNOWN;
1232         phydev->duplex = DUPLEX_UNKNOWN;
1233         phydev->pause = 0;
1234         phydev->asym_pause = 0;
1235
1236         err = genphy_read_lpa(phydev);
1237         if (err < 0)
1238                 return err;
1239
1240         err = at803x_read_specific_status(phydev);
1241         if (err < 0)
1242                 return err;
1243
1244         if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1245                 phy_resolve_aneg_pause(phydev);
1246
1247         return 0;
1248 }
1249
1250 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1251 {
1252         u16 val;
1253
1254         switch (ctrl) {
1255         case ETH_TP_MDI:
1256                 val = AT803X_SFC_MANUAL_MDI;
1257                 break;
1258         case ETH_TP_MDI_X:
1259                 val = AT803X_SFC_MANUAL_MDIX;
1260                 break;
1261         case ETH_TP_MDI_AUTO:
1262                 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1263                 break;
1264         default:
1265                 return 0;
1266         }
1267
1268         return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1269                           AT803X_SFC_MDI_CROSSOVER_MODE_M,
1270                           FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1271 }
1272
1273 static int at803x_config_aneg(struct phy_device *phydev)
1274 {
1275         struct at803x_priv *priv = phydev->priv;
1276         int ret;
1277
1278         ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1279         if (ret < 0)
1280                 return ret;
1281
1282         /* Changes of the midx bits are disruptive to the normal operation;
1283          * therefore any changes to these registers must be followed by a
1284          * software reset to take effect.
1285          */
1286         if (ret == 1) {
1287                 ret = genphy_soft_reset(phydev);
1288                 if (ret < 0)
1289                         return ret;
1290         }
1291
1292         if (priv->is_1000basex)
1293                 return genphy_c37_config_aneg(phydev);
1294
1295         /* Do not restart auto-negotiation by setting ret to 0 defautly,
1296          * when calling __genphy_config_aneg later.
1297          */
1298         ret = 0;
1299
1300         if (phydev->drv->phy_id == QCA8081_PHY_ID) {
1301                 int phy_ctrl = 0;
1302
1303                 /* The reg MII_BMCR also needs to be configured for force mode, the
1304                  * genphy_config_aneg is also needed.
1305                  */
1306                 if (phydev->autoneg == AUTONEG_DISABLE)
1307                         genphy_c45_pma_setup_forced(phydev);
1308
1309                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
1310                         phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
1311
1312                 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1313                                 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
1314                 if (ret < 0)
1315                         return ret;
1316         }
1317
1318         return __genphy_config_aneg(phydev, ret);
1319 }
1320
1321 static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1322 {
1323         int val;
1324
1325         val = phy_read(phydev, AT803X_SMART_SPEED);
1326         if (val < 0)
1327                 return val;
1328
1329         if (val & AT803X_SMART_SPEED_ENABLE)
1330                 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1331         else
1332                 *d = DOWNSHIFT_DEV_DISABLE;
1333
1334         return 0;
1335 }
1336
1337 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1338 {
1339         u16 mask, set;
1340         int ret;
1341
1342         switch (cnt) {
1343         case DOWNSHIFT_DEV_DEFAULT_COUNT:
1344                 cnt = AT803X_DEFAULT_DOWNSHIFT;
1345                 fallthrough;
1346         case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1347                 set = AT803X_SMART_SPEED_ENABLE |
1348                       AT803X_SMART_SPEED_BYPASS_TIMER |
1349                       FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1350                 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1351                 break;
1352         case DOWNSHIFT_DEV_DISABLE:
1353                 set = 0;
1354                 mask = AT803X_SMART_SPEED_ENABLE |
1355                        AT803X_SMART_SPEED_BYPASS_TIMER;
1356                 break;
1357         default:
1358                 return -EINVAL;
1359         }
1360
1361         ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1362
1363         /* After changing the smart speed settings, we need to perform a
1364          * software reset, use phy_init_hw() to make sure we set the
1365          * reapply any values which might got lost during software reset.
1366          */
1367         if (ret == 1)
1368                 ret = phy_init_hw(phydev);
1369
1370         return ret;
1371 }
1372
1373 static int at803x_get_tunable(struct phy_device *phydev,
1374                               struct ethtool_tunable *tuna, void *data)
1375 {
1376         switch (tuna->id) {
1377         case ETHTOOL_PHY_DOWNSHIFT:
1378                 return at803x_get_downshift(phydev, data);
1379         default:
1380                 return -EOPNOTSUPP;
1381         }
1382 }
1383
1384 static int at803x_set_tunable(struct phy_device *phydev,
1385                               struct ethtool_tunable *tuna, const void *data)
1386 {
1387         switch (tuna->id) {
1388         case ETHTOOL_PHY_DOWNSHIFT:
1389                 return at803x_set_downshift(phydev, *(const u8 *)data);
1390         default:
1391                 return -EOPNOTSUPP;
1392         }
1393 }
1394
1395 static int at803x_cable_test_result_trans(u16 status)
1396 {
1397         switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1398         case AT803X_CDT_STATUS_STAT_NORMAL:
1399                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1400         case AT803X_CDT_STATUS_STAT_SHORT:
1401                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1402         case AT803X_CDT_STATUS_STAT_OPEN:
1403                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1404         case AT803X_CDT_STATUS_STAT_FAIL:
1405         default:
1406                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1407         }
1408 }
1409
1410 static bool at803x_cdt_test_failed(u16 status)
1411 {
1412         return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1413                 AT803X_CDT_STATUS_STAT_FAIL;
1414 }
1415
1416 static bool at803x_cdt_fault_length_valid(u16 status)
1417 {
1418         switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1419         case AT803X_CDT_STATUS_STAT_OPEN:
1420         case AT803X_CDT_STATUS_STAT_SHORT:
1421                 return true;
1422         }
1423         return false;
1424 }
1425
1426 static int at803x_cdt_fault_length(u16 status)
1427 {
1428         int dt;
1429
1430         /* According to the datasheet the distance to the fault is
1431          * DELTA_TIME * 0.824 meters.
1432          *
1433          * The author suspect the correct formula is:
1434          *
1435          *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1436          *
1437          * where c is the speed of light, VF is the velocity factor of
1438          * the twisted pair cable, 125MHz the counter frequency and
1439          * we need to divide by 2 because the hardware will measure the
1440          * round trip time to the fault and back to the PHY.
1441          *
1442          * With a VF of 0.69 we get the factor 0.824 mentioned in the
1443          * datasheet.
1444          */
1445         dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
1446
1447         return (dt * 824) / 10;
1448 }
1449
1450 static int at803x_cdt_start(struct phy_device *phydev, int pair)
1451 {
1452         u16 cdt;
1453
1454         /* qca8081 takes the different bit 15 to enable CDT test */
1455         if (phydev->drv->phy_id == QCA8081_PHY_ID)
1456                 cdt = QCA808X_CDT_ENABLE_TEST |
1457                         QCA808X_CDT_LENGTH_UNIT |
1458                         QCA808X_CDT_INTER_CHECK_DIS;
1459         else
1460                 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1461                         AT803X_CDT_ENABLE_TEST;
1462
1463         return phy_write(phydev, AT803X_CDT, cdt);
1464 }
1465
1466 static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
1467 {
1468         int val, ret;
1469         u16 cdt_en;
1470
1471         if (phydev->drv->phy_id == QCA8081_PHY_ID)
1472                 cdt_en = QCA808X_CDT_ENABLE_TEST;
1473         else
1474                 cdt_en = AT803X_CDT_ENABLE_TEST;
1475
1476         /* One test run takes about 25ms */
1477         ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1478                                     !(val & cdt_en),
1479                                     30000, 100000, true);
1480
1481         return ret < 0 ? ret : 0;
1482 }
1483
1484 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1485 {
1486         static const int ethtool_pair[] = {
1487                 ETHTOOL_A_CABLE_PAIR_A,
1488                 ETHTOOL_A_CABLE_PAIR_B,
1489                 ETHTOOL_A_CABLE_PAIR_C,
1490                 ETHTOOL_A_CABLE_PAIR_D,
1491         };
1492         int ret, val;
1493
1494         ret = at803x_cdt_start(phydev, pair);
1495         if (ret)
1496                 return ret;
1497
1498         ret = at803x_cdt_wait_for_completion(phydev);
1499         if (ret)
1500                 return ret;
1501
1502         val = phy_read(phydev, AT803X_CDT_STATUS);
1503         if (val < 0)
1504                 return val;
1505
1506         if (at803x_cdt_test_failed(val))
1507                 return 0;
1508
1509         ethnl_cable_test_result(phydev, ethtool_pair[pair],
1510                                 at803x_cable_test_result_trans(val));
1511
1512         if (at803x_cdt_fault_length_valid(val))
1513                 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1514                                               at803x_cdt_fault_length(val));
1515
1516         return 1;
1517 }
1518
1519 static int at803x_cable_test_get_status(struct phy_device *phydev,
1520                                         bool *finished)
1521 {
1522         unsigned long pair_mask;
1523         int retries = 20;
1524         int pair, ret;
1525
1526         if (phydev->phy_id == ATH9331_PHY_ID ||
1527             phydev->phy_id == ATH8032_PHY_ID ||
1528             phydev->phy_id == QCA9561_PHY_ID)
1529                 pair_mask = 0x3;
1530         else
1531                 pair_mask = 0xf;
1532
1533         *finished = false;
1534
1535         /* According to the datasheet the CDT can be performed when
1536          * there is no link partner or when the link partner is
1537          * auto-negotiating. Starting the test will restart the AN
1538          * automatically. It seems that doing this repeatedly we will
1539          * get a slot where our link partner won't disturb our
1540          * measurement.
1541          */
1542         while (pair_mask && retries--) {
1543                 for_each_set_bit(pair, &pair_mask, 4) {
1544                         ret = at803x_cable_test_one_pair(phydev, pair);
1545                         if (ret < 0)
1546                                 return ret;
1547                         if (ret)
1548                                 clear_bit(pair, &pair_mask);
1549                 }
1550                 if (pair_mask)
1551                         msleep(250);
1552         }
1553
1554         *finished = true;
1555
1556         return 0;
1557 }
1558
1559 static int at803x_cable_test_start(struct phy_device *phydev)
1560 {
1561         /* Enable auto-negotiation, but advertise no capabilities, no link
1562          * will be established. A restart of the auto-negotiation is not
1563          * required, because the cable test will automatically break the link.
1564          */
1565         phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1566         phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1567         if (phydev->phy_id != ATH9331_PHY_ID &&
1568             phydev->phy_id != ATH8032_PHY_ID &&
1569             phydev->phy_id != QCA9561_PHY_ID)
1570                 phy_write(phydev, MII_CTRL1000, 0);
1571
1572         /* we do all the (time consuming) work later */
1573         return 0;
1574 }
1575
1576 static int qca83xx_config_init(struct phy_device *phydev)
1577 {
1578         u8 switch_revision;
1579
1580         switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1581
1582         switch (switch_revision) {
1583         case 1:
1584                 /* For 100M waveform */
1585                 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
1586                 /* Turn on Gigabit clock */
1587                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
1588                 break;
1589
1590         case 2:
1591                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1592                 fallthrough;
1593         case 4:
1594                 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1595                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
1596                 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
1597                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1598                 break;
1599         }
1600
1601         /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
1602          * Disable on init and enable only with 100m speed following
1603          * qca original source code.
1604          */
1605         if (phydev->drv->phy_id == QCA8327_A_PHY_ID ||
1606             phydev->drv->phy_id == QCA8327_B_PHY_ID)
1607                 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1608                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
1609
1610         /* Following original QCA sourcecode set port to prefer master */
1611         phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
1612
1613         return 0;
1614 }
1615
1616 static void qca83xx_link_change_notify(struct phy_device *phydev)
1617 {
1618         /* QCA8337 doesn't require DAC Amplitude adjustement */
1619         if (phydev->drv->phy_id == QCA8337_PHY_ID)
1620                 return;
1621
1622         /* Set DAC Amplitude adjustment to +6% for 100m on link running */
1623         if (phydev->state == PHY_RUNNING) {
1624                 if (phydev->speed == SPEED_100)
1625                         at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1626                                               QCA8327_DEBUG_MANU_CTRL_EN,
1627                                               QCA8327_DEBUG_MANU_CTRL_EN);
1628         } else {
1629                 /* Reset DAC Amplitude adjustment */
1630                 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1631                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
1632         }
1633 }
1634
1635 static int qca83xx_resume(struct phy_device *phydev)
1636 {
1637         int ret, val;
1638
1639         /* Skip reset if not suspended */
1640         if (!phydev->suspended)
1641                 return 0;
1642
1643         /* Reinit the port, reset values set by suspend */
1644         qca83xx_config_init(phydev);
1645
1646         /* Reset the port on port resume */
1647         phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1648
1649         /* On resume from suspend the switch execute a reset and
1650          * restart auto-negotiation. Wait for reset to complete.
1651          */
1652         ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1653                                     50000, 600000, true);
1654         if (ret)
1655                 return ret;
1656
1657         msleep(1);
1658
1659         return 0;
1660 }
1661
1662 static int qca83xx_suspend(struct phy_device *phydev)
1663 {
1664         u16 mask = 0;
1665
1666         /* Only QCA8337 support actual suspend.
1667          * QCA8327 cause port unreliability when phy suspend
1668          * is set.
1669          */
1670         if (phydev->drv->phy_id == QCA8337_PHY_ID) {
1671                 genphy_suspend(phydev);
1672         } else {
1673                 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
1674                 phy_modify(phydev, MII_BMCR, mask, 0);
1675         }
1676
1677         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
1678                               AT803X_DEBUG_GATE_CLK_IN1000, 0);
1679
1680         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1681                               AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
1682                               AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
1683
1684         return 0;
1685 }
1686
1687 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
1688 {
1689         int ret;
1690
1691         /* Enable fast retrain */
1692         ret = genphy_c45_fast_retrain(phydev, true);
1693         if (ret)
1694                 return ret;
1695
1696         phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
1697                         QCA808X_TOP_OPTION1_DATA);
1698         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
1699                         QCA808X_MSE_THRESHOLD_20DB_VALUE);
1700         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
1701                         QCA808X_MSE_THRESHOLD_17DB_VALUE);
1702         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
1703                         QCA808X_MSE_THRESHOLD_27DB_VALUE);
1704         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
1705                         QCA808X_MSE_THRESHOLD_28DB_VALUE);
1706         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
1707                         QCA808X_MMD3_DEBUG_1_VALUE);
1708         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
1709                         QCA808X_MMD3_DEBUG_4_VALUE);
1710         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
1711                         QCA808X_MMD3_DEBUG_5_VALUE);
1712         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
1713                         QCA808X_MMD3_DEBUG_3_VALUE);
1714         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
1715                         QCA808X_MMD3_DEBUG_6_VALUE);
1716         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
1717                         QCA808X_MMD3_DEBUG_2_VALUE);
1718
1719         return 0;
1720 }
1721
1722 static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev)
1723 {
1724         u16 seed_value = (prandom_u32() % QCA808X_MASTER_SLAVE_SEED_RANGE);
1725
1726         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1727                         QCA808X_MASTER_SLAVE_SEED_CFG,
1728                         FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value));
1729 }
1730
1731 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
1732 {
1733         u16 seed_enable = 0;
1734
1735         if (enable)
1736                 seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE;
1737
1738         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1739                         QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable);
1740 }
1741
1742 static int qca808x_config_init(struct phy_device *phydev)
1743 {
1744         int ret;
1745
1746         /* Active adc&vga on 802.3az for the link 1000M and 100M */
1747         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
1748                         QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
1749         if (ret)
1750                 return ret;
1751
1752         /* Adjust the threshold on 802.3az for the link 1000M */
1753         ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
1754                         QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);
1755         if (ret)
1756                 return ret;
1757
1758         /* Config the fast retrain for the link 2500M */
1759         ret = qca808x_phy_fast_retrain_config(phydev);
1760         if (ret)
1761                 return ret;
1762
1763         /* Configure lower ramdom seed to make phy linked as slave mode */
1764         ret = qca808x_phy_ms_random_seed_set(phydev);
1765         if (ret)
1766                 return ret;
1767
1768         /* Enable seed */
1769         ret = qca808x_phy_ms_seed_enable(phydev, true);
1770         if (ret)
1771                 return ret;
1772
1773         /* Configure adc threshold as 100mv for the link 10M */
1774         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
1775                         QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);
1776 }
1777
1778 static int qca808x_read_status(struct phy_device *phydev)
1779 {
1780         int ret;
1781
1782         ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
1783         if (ret < 0)
1784                 return ret;
1785
1786         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
1787                         ret & MDIO_AN_10GBT_STAT_LP2_5G);
1788
1789         ret = genphy_read_status(phydev);
1790         if (ret)
1791                 return ret;
1792
1793         ret = at803x_read_specific_status(phydev);
1794         if (ret < 0)
1795                 return ret;
1796
1797         if (phydev->link) {
1798                 if (phydev->speed == SPEED_2500)
1799                         phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1800                 else
1801                         phydev->interface = PHY_INTERFACE_MODE_SGMII;
1802         } else {
1803                 /* generate seed as a lower random value to make PHY linked as SLAVE easily,
1804                  * except for master/slave configuration fault detected.
1805                  * the reason for not putting this code into the function link_change_notify is
1806                  * the corner case where the link partner is also the qca8081 PHY and the seed
1807                  * value is configured as the same value, the link can't be up and no link change
1808                  * occurs.
1809                  */
1810                 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) {
1811                         qca808x_phy_ms_seed_enable(phydev, false);
1812                 } else {
1813                         qca808x_phy_ms_random_seed_set(phydev);
1814                         qca808x_phy_ms_seed_enable(phydev, true);
1815                 }
1816         }
1817
1818         return 0;
1819 }
1820
1821 static int qca808x_soft_reset(struct phy_device *phydev)
1822 {
1823         int ret;
1824
1825         ret = genphy_soft_reset(phydev);
1826         if (ret < 0)
1827                 return ret;
1828
1829         return qca808x_phy_ms_seed_enable(phydev, true);
1830 }
1831
1832 static bool qca808x_cdt_fault_length_valid(int cdt_code)
1833 {
1834         switch (cdt_code) {
1835         case QCA808X_CDT_STATUS_STAT_SHORT:
1836         case QCA808X_CDT_STATUS_STAT_OPEN:
1837                 return true;
1838         default:
1839                 return false;
1840         }
1841 }
1842
1843 static int qca808x_cable_test_result_trans(int cdt_code)
1844 {
1845         switch (cdt_code) {
1846         case QCA808X_CDT_STATUS_STAT_NORMAL:
1847                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1848         case QCA808X_CDT_STATUS_STAT_SHORT:
1849                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1850         case QCA808X_CDT_STATUS_STAT_OPEN:
1851                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1852         case QCA808X_CDT_STATUS_STAT_FAIL:
1853         default:
1854                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1855         }
1856 }
1857
1858 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair)
1859 {
1860         int val;
1861         u32 cdt_length_reg = 0;
1862
1863         switch (pair) {
1864         case ETHTOOL_A_CABLE_PAIR_A:
1865                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
1866                 break;
1867         case ETHTOOL_A_CABLE_PAIR_B:
1868                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
1869                 break;
1870         case ETHTOOL_A_CABLE_PAIR_C:
1871                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
1872                 break;
1873         case ETHTOOL_A_CABLE_PAIR_D:
1874                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
1875                 break;
1876         default:
1877                 return -EINVAL;
1878         }
1879
1880         val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
1881         if (val < 0)
1882                 return val;
1883
1884         return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10;
1885 }
1886
1887 static int qca808x_cable_test_start(struct phy_device *phydev)
1888 {
1889         int ret;
1890
1891         /* perform CDT with the following configs:
1892          * 1. disable hibernation.
1893          * 2. force PHY working in MDI mode.
1894          * 3. for PHY working in 1000BaseT.
1895          * 4. configure the threshold.
1896          */
1897
1898         ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
1899         if (ret < 0)
1900                 return ret;
1901
1902         ret = at803x_config_mdix(phydev, ETH_TP_MDI);
1903         if (ret < 0)
1904                 return ret;
1905
1906         /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
1907         phydev->duplex = DUPLEX_FULL;
1908         phydev->speed = SPEED_1000;
1909         ret = genphy_c45_pma_setup_forced(phydev);
1910         if (ret < 0)
1911                 return ret;
1912
1913         ret = genphy_setup_forced(phydev);
1914         if (ret < 0)
1915                 return ret;
1916
1917         /* configure the thresholds for open, short, pair ok test */
1918         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
1919         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
1920         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
1921         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
1922         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
1923         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
1924
1925         return 0;
1926 }
1927
1928 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
1929 {
1930         int ret, val;
1931         int pair_a, pair_b, pair_c, pair_d;
1932
1933         *finished = false;
1934
1935         ret = at803x_cdt_start(phydev, 0);
1936         if (ret)
1937                 return ret;
1938
1939         ret = at803x_cdt_wait_for_completion(phydev);
1940         if (ret)
1941                 return ret;
1942
1943         val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
1944         if (val < 0)
1945                 return val;
1946
1947         pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val);
1948         pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val);
1949         pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val);
1950         pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val);
1951
1952         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1953                                 qca808x_cable_test_result_trans(pair_a));
1954         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
1955                                 qca808x_cable_test_result_trans(pair_b));
1956         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
1957                                 qca808x_cable_test_result_trans(pair_c));
1958         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
1959                                 qca808x_cable_test_result_trans(pair_d));
1960
1961         if (qca808x_cdt_fault_length_valid(pair_a))
1962                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,
1963                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A));
1964         if (qca808x_cdt_fault_length_valid(pair_b))
1965                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B,
1966                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B));
1967         if (qca808x_cdt_fault_length_valid(pair_c))
1968                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C,
1969                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C));
1970         if (qca808x_cdt_fault_length_valid(pair_d))
1971                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D,
1972                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D));
1973
1974         *finished = true;
1975
1976         return 0;
1977 }
1978
1979 static struct phy_driver at803x_driver[] = {
1980 {
1981         /* Qualcomm Atheros AR8035 */
1982         PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
1983         .name                   = "Qualcomm Atheros AR8035",
1984         .flags                  = PHY_POLL_CABLE_TEST,
1985         .probe                  = at803x_probe,
1986         .remove                 = at803x_remove,
1987         .config_aneg            = at803x_config_aneg,
1988         .config_init            = at803x_config_init,
1989         .soft_reset             = genphy_soft_reset,
1990         .set_wol                = at803x_set_wol,
1991         .get_wol                = at803x_get_wol,
1992         .suspend                = at803x_suspend,
1993         .resume                 = at803x_resume,
1994         /* PHY_GBIT_FEATURES */
1995         .read_status            = at803x_read_status,
1996         .config_intr            = at803x_config_intr,
1997         .handle_interrupt       = at803x_handle_interrupt,
1998         .get_tunable            = at803x_get_tunable,
1999         .set_tunable            = at803x_set_tunable,
2000         .cable_test_start       = at803x_cable_test_start,
2001         .cable_test_get_status  = at803x_cable_test_get_status,
2002 }, {
2003         /* Qualcomm Atheros AR8030 */
2004         .phy_id                 = ATH8030_PHY_ID,
2005         .name                   = "Qualcomm Atheros AR8030",
2006         .phy_id_mask            = AT8030_PHY_ID_MASK,
2007         .probe                  = at803x_probe,
2008         .remove                 = at803x_remove,
2009         .config_init            = at803x_config_init,
2010         .link_change_notify     = at803x_link_change_notify,
2011         .set_wol                = at803x_set_wol,
2012         .get_wol                = at803x_get_wol,
2013         .suspend                = at803x_suspend,
2014         .resume                 = at803x_resume,
2015         /* PHY_BASIC_FEATURES */
2016         .config_intr            = at803x_config_intr,
2017         .handle_interrupt       = at803x_handle_interrupt,
2018 }, {
2019         /* Qualcomm Atheros AR8031/AR8033 */
2020         PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
2021         .name                   = "Qualcomm Atheros AR8031/AR8033",
2022         .flags                  = PHY_POLL_CABLE_TEST,
2023         .probe                  = at803x_probe,
2024         .remove                 = at803x_remove,
2025         .config_init            = at803x_config_init,
2026         .config_aneg            = at803x_config_aneg,
2027         .soft_reset             = genphy_soft_reset,
2028         .set_wol                = at803x_set_wol,
2029         .get_wol                = at803x_get_wol,
2030         .suspend                = at803x_suspend,
2031         .resume                 = at803x_resume,
2032         .read_page              = at803x_read_page,
2033         .write_page             = at803x_write_page,
2034         .get_features           = at803x_get_features,
2035         .read_status            = at803x_read_status,
2036         .config_intr            = &at803x_config_intr,
2037         .handle_interrupt       = at803x_handle_interrupt,
2038         .get_tunable            = at803x_get_tunable,
2039         .set_tunable            = at803x_set_tunable,
2040         .cable_test_start       = at803x_cable_test_start,
2041         .cable_test_get_status  = at803x_cable_test_get_status,
2042 }, {
2043         /* Qualcomm Atheros AR8032 */
2044         PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
2045         .name                   = "Qualcomm Atheros AR8032",
2046         .probe                  = at803x_probe,
2047         .remove                 = at803x_remove,
2048         .flags                  = PHY_POLL_CABLE_TEST,
2049         .config_init            = at803x_config_init,
2050         .link_change_notify     = at803x_link_change_notify,
2051         .set_wol                = at803x_set_wol,
2052         .get_wol                = at803x_get_wol,
2053         .suspend                = at803x_suspend,
2054         .resume                 = at803x_resume,
2055         /* PHY_BASIC_FEATURES */
2056         .config_intr            = at803x_config_intr,
2057         .handle_interrupt       = at803x_handle_interrupt,
2058         .cable_test_start       = at803x_cable_test_start,
2059         .cable_test_get_status  = at803x_cable_test_get_status,
2060 }, {
2061         /* ATHEROS AR9331 */
2062         PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
2063         .name                   = "Qualcomm Atheros AR9331 built-in PHY",
2064         .suspend                = at803x_suspend,
2065         .resume                 = at803x_resume,
2066         .flags                  = PHY_POLL_CABLE_TEST,
2067         /* PHY_BASIC_FEATURES */
2068         .config_intr            = &at803x_config_intr,
2069         .handle_interrupt       = at803x_handle_interrupt,
2070         .cable_test_start       = at803x_cable_test_start,
2071         .cable_test_get_status  = at803x_cable_test_get_status,
2072         .read_status            = at803x_read_status,
2073         .soft_reset             = genphy_soft_reset,
2074         .config_aneg            = at803x_config_aneg,
2075 }, {
2076         /* Qualcomm Atheros QCA9561 */
2077         PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
2078         .name                   = "Qualcomm Atheros QCA9561 built-in PHY",
2079         .suspend                = at803x_suspend,
2080         .resume                 = at803x_resume,
2081         .flags                  = PHY_POLL_CABLE_TEST,
2082         /* PHY_BASIC_FEATURES */
2083         .config_intr            = &at803x_config_intr,
2084         .handle_interrupt       = at803x_handle_interrupt,
2085         .cable_test_start       = at803x_cable_test_start,
2086         .cable_test_get_status  = at803x_cable_test_get_status,
2087         .read_status            = at803x_read_status,
2088         .soft_reset             = genphy_soft_reset,
2089         .config_aneg            = at803x_config_aneg,
2090 }, {
2091         /* QCA8337 */
2092         .phy_id                 = QCA8337_PHY_ID,
2093         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2094         .name                   = "Qualcomm Atheros 8337 internal PHY",
2095         /* PHY_GBIT_FEATURES */
2096         .link_change_notify     = qca83xx_link_change_notify,
2097         .probe                  = at803x_probe,
2098         .flags                  = PHY_IS_INTERNAL,
2099         .config_init            = qca83xx_config_init,
2100         .soft_reset             = genphy_soft_reset,
2101         .get_sset_count         = at803x_get_sset_count,
2102         .get_strings            = at803x_get_strings,
2103         .get_stats              = at803x_get_stats,
2104         .suspend                = qca83xx_suspend,
2105         .resume                 = qca83xx_resume,
2106 }, {
2107         /* QCA8327-A from switch QCA8327-AL1A */
2108         .phy_id                 = QCA8327_A_PHY_ID,
2109         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2110         .name                   = "Qualcomm Atheros 8327-A internal PHY",
2111         /* PHY_GBIT_FEATURES */
2112         .link_change_notify     = qca83xx_link_change_notify,
2113         .probe                  = at803x_probe,
2114         .flags                  = PHY_IS_INTERNAL,
2115         .config_init            = qca83xx_config_init,
2116         .soft_reset             = genphy_soft_reset,
2117         .get_sset_count         = at803x_get_sset_count,
2118         .get_strings            = at803x_get_strings,
2119         .get_stats              = at803x_get_stats,
2120         .suspend                = qca83xx_suspend,
2121         .resume                 = qca83xx_resume,
2122 }, {
2123         /* QCA8327-B from switch QCA8327-BL1A */
2124         .phy_id                 = QCA8327_B_PHY_ID,
2125         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2126         .name                   = "Qualcomm Atheros 8327-B internal PHY",
2127         /* PHY_GBIT_FEATURES */
2128         .link_change_notify     = qca83xx_link_change_notify,
2129         .probe                  = at803x_probe,
2130         .flags                  = PHY_IS_INTERNAL,
2131         .config_init            = qca83xx_config_init,
2132         .soft_reset             = genphy_soft_reset,
2133         .get_sset_count         = at803x_get_sset_count,
2134         .get_strings            = at803x_get_strings,
2135         .get_stats              = at803x_get_stats,
2136         .suspend                = qca83xx_suspend,
2137         .resume                 = qca83xx_resume,
2138 }, {
2139         /* Qualcomm QCA8081 */
2140         PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
2141         .name                   = "Qualcomm QCA8081",
2142         .flags                  = PHY_POLL_CABLE_TEST,
2143         .config_intr            = at803x_config_intr,
2144         .handle_interrupt       = at803x_handle_interrupt,
2145         .get_tunable            = at803x_get_tunable,
2146         .set_tunable            = at803x_set_tunable,
2147         .set_wol                = at803x_set_wol,
2148         .get_wol                = at803x_get_wol,
2149         .get_features           = at803x_get_features,
2150         .config_aneg            = at803x_config_aneg,
2151         .suspend                = genphy_suspend,
2152         .resume                 = genphy_resume,
2153         .read_status            = qca808x_read_status,
2154         .config_init            = qca808x_config_init,
2155         .soft_reset             = qca808x_soft_reset,
2156         .cable_test_start       = qca808x_cable_test_start,
2157         .cable_test_get_status  = qca808x_cable_test_get_status,
2158 }, };
2159
2160 module_phy_driver(at803x_driver);
2161
2162 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
2163         { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
2164         { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
2165         { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
2166         { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
2167         { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
2168         { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
2169         { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
2170         { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
2171         { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
2172         { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
2173         { }
2174 };
2175
2176 MODULE_DEVICE_TABLE(mdio, atheros_tbl);