1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/at803x.c
5 * Driver for Qualcomm Atheros AR803x PHY
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
10 #include <linux/phy.h>
11 #include <linux/module.h>
12 #include <linux/string.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/of_gpio.h>
17 #include <linux/bitfield.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/regulator/of_regulator.h>
20 #include <linux/regulator/driver.h>
21 #include <linux/regulator/consumer.h>
22 #include <dt-bindings/net/qca-ar803x.h>
24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
25 #define AT803X_SFC_ASSERT_CRS BIT(11)
26 #define AT803X_SFC_FORCE_LINK BIT(10)
27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
29 #define AT803X_SFC_MANUAL_MDIX 0x1
30 #define AT803X_SFC_MANUAL_MDI 0x0
31 #define AT803X_SFC_SQE_TEST BIT(2)
32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1)
33 #define AT803X_SFC_DISABLE_JABBER BIT(0)
35 #define AT803X_SPECIFIC_STATUS 0x11
36 #define AT803X_SS_SPEED_MASK (3 << 14)
37 #define AT803X_SS_SPEED_1000 (2 << 14)
38 #define AT803X_SS_SPEED_100 (1 << 14)
39 #define AT803X_SS_SPEED_10 (0 << 14)
40 #define AT803X_SS_DUPLEX BIT(13)
41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
42 #define AT803X_SS_MDIX BIT(6)
44 #define AT803X_INTR_ENABLE 0x12
45 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
46 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
47 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
48 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
49 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
50 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
51 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
52 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
53 #define AT803X_INTR_ENABLE_WOL BIT(0)
55 #define AT803X_INTR_STATUS 0x13
57 #define AT803X_SMART_SPEED 0x14
58 #define AT803X_SMART_SPEED_ENABLE BIT(5)
59 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
60 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
61 #define AT803X_CDT 0x16
62 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
63 #define AT803X_CDT_ENABLE_TEST BIT(0)
64 #define AT803X_CDT_STATUS 0x1c
65 #define AT803X_CDT_STATUS_STAT_NORMAL 0
66 #define AT803X_CDT_STATUS_STAT_SHORT 1
67 #define AT803X_CDT_STATUS_STAT_OPEN 2
68 #define AT803X_CDT_STATUS_STAT_FAIL 3
69 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
70 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
71 #define AT803X_LED_CONTROL 0x18
73 #define AT803X_DEVICE_ADDR 0x03
74 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
75 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
76 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
77 #define AT803X_REG_CHIP_CONFIG 0x1f
78 #define AT803X_BT_BX_REG_SEL 0x8000
80 #define AT803X_DEBUG_ADDR 0x1D
81 #define AT803X_DEBUG_DATA 0x1E
83 #define AT803X_MODE_CFG_MASK 0x0F
84 #define AT803X_MODE_CFG_SGMII 0x01
86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
87 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
89 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
90 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
91 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
92 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
94 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
95 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
97 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b
98 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
99 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
101 #define AT803X_DEBUG_REG_3C 0x3C
103 #define AT803X_DEBUG_REG_GREEN 0x3D
104 #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
106 #define AT803X_DEBUG_REG_1F 0x1F
107 #define AT803X_DEBUG_PLL_ON BIT(2)
108 #define AT803X_DEBUG_RGMII_1V8 BIT(3)
110 #define MDIO_AZ_DEBUG 0x800D
112 /* AT803x supports either the XTAL input pad, an internal PLL or the
113 * DSP as clock reference for the clock output pad. The XTAL reference
114 * is only used for 25 MHz output, all other frequencies need the PLL.
115 * The DSP as a clock reference is used in synchronous ethernet
118 * By default the PLL is only enabled if there is a link. Otherwise
119 * the PHY will go into low power state and disabled the PLL. You can
120 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
123 #define AT803X_MMD7_CLK25M 0x8016
124 #define AT803X_CLK_OUT_MASK GENMASK(4, 2)
125 #define AT803X_CLK_OUT_25MHZ_XTAL 0
126 #define AT803X_CLK_OUT_25MHZ_DSP 1
127 #define AT803X_CLK_OUT_50MHZ_PLL 2
128 #define AT803X_CLK_OUT_50MHZ_DSP 3
129 #define AT803X_CLK_OUT_62_5MHZ_PLL 4
130 #define AT803X_CLK_OUT_62_5MHZ_DSP 5
131 #define AT803X_CLK_OUT_125MHZ_PLL 6
132 #define AT803X_CLK_OUT_125MHZ_DSP 7
134 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
135 * but doesn't support choosing between XTAL/PLL and DSP.
137 #define AT8035_CLK_OUT_MASK GENMASK(4, 3)
139 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
140 #define AT803X_CLK_OUT_STRENGTH_FULL 0
141 #define AT803X_CLK_OUT_STRENGTH_HALF 1
142 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2
144 #define AT803X_DEFAULT_DOWNSHIFT 5
145 #define AT803X_MIN_DOWNSHIFT 2
146 #define AT803X_MAX_DOWNSHIFT 9
148 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b
149 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c
150 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d
151 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
153 #define ATH9331_PHY_ID 0x004dd041
154 #define ATH8030_PHY_ID 0x004dd076
155 #define ATH8031_PHY_ID 0x004dd074
156 #define ATH8032_PHY_ID 0x004dd023
157 #define ATH8035_PHY_ID 0x004dd072
158 #define AT8030_PHY_ID_MASK 0xffffffef
160 #define QCA8327_A_PHY_ID 0x004dd033
161 #define QCA8327_B_PHY_ID 0x004dd034
162 #define QCA8337_PHY_ID 0x004dd036
163 #define QCA9561_PHY_ID 0x004dd042
164 #define QCA8K_PHY_ID_MASK 0xffffffff
166 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
168 #define AT803X_PAGE_FIBER 0
169 #define AT803X_PAGE_COPPER 1
171 /* don't turn off internal PLL */
172 #define AT803X_KEEP_PLL_ENABLED BIT(0)
173 #define AT803X_DISABLE_SMARTEEE BIT(1)
175 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
176 MODULE_AUTHOR("Matus Ujhelyi");
177 MODULE_LICENSE("GPL");
179 enum stat_access_type {
184 struct at803x_hw_stat {
188 enum stat_access_type access_type;
191 static struct at803x_hw_stat at803x_hw_stats[] = {
192 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
193 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
194 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
201 u8 smarteee_lpi_tw_1g;
202 u8 smarteee_lpi_tw_100m;
203 struct regulator_dev *vddio_rdev;
204 struct regulator_dev *vddh_rdev;
205 struct regulator *vddio;
206 u64 stats[ARRAY_SIZE(at803x_hw_stats)];
209 struct at803x_context {
218 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
222 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
226 return phy_write(phydev, AT803X_DEBUG_DATA, data);
229 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
233 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
237 return phy_read(phydev, AT803X_DEBUG_DATA);
240 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
246 ret = at803x_debug_reg_read(phydev, reg);
254 return phy_write(phydev, AT803X_DEBUG_DATA, val);
257 static int at803x_write_page(struct phy_device *phydev, int page)
262 if (page == AT803X_PAGE_COPPER) {
263 set = AT803X_BT_BX_REG_SEL;
267 mask = AT803X_BT_BX_REG_SEL;
270 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
273 static int at803x_read_page(struct phy_device *phydev)
275 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
280 if (ccr & AT803X_BT_BX_REG_SEL)
281 return AT803X_PAGE_COPPER;
283 return AT803X_PAGE_FIBER;
286 static int at803x_enable_rx_delay(struct phy_device *phydev)
288 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
289 AT803X_DEBUG_RX_CLK_DLY_EN);
292 static int at803x_enable_tx_delay(struct phy_device *phydev)
294 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
295 AT803X_DEBUG_TX_CLK_DLY_EN);
298 static int at803x_disable_rx_delay(struct phy_device *phydev)
300 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
301 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
304 static int at803x_disable_tx_delay(struct phy_device *phydev)
306 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
307 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
310 /* save relevant PHY registers to private copy */
311 static void at803x_context_save(struct phy_device *phydev,
312 struct at803x_context *context)
314 context->bmcr = phy_read(phydev, MII_BMCR);
315 context->advertise = phy_read(phydev, MII_ADVERTISE);
316 context->control1000 = phy_read(phydev, MII_CTRL1000);
317 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
318 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
319 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
322 /* restore relevant PHY registers from private copy */
323 static void at803x_context_restore(struct phy_device *phydev,
324 const struct at803x_context *context)
326 phy_write(phydev, MII_BMCR, context->bmcr);
327 phy_write(phydev, MII_ADVERTISE, context->advertise);
328 phy_write(phydev, MII_CTRL1000, context->control1000);
329 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
330 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
331 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
334 static int at803x_set_wol(struct phy_device *phydev,
335 struct ethtool_wolinfo *wol)
337 struct net_device *ndev = phydev->attached_dev;
341 unsigned int i, offsets[] = {
342 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
343 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
344 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
350 if (wol->wolopts & WAKE_MAGIC) {
351 mac = (const u8 *) ndev->dev_addr;
353 if (!is_valid_ether_addr(mac))
356 for (i = 0; i < 3; i++)
357 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
358 mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
360 value = phy_read(phydev, AT803X_INTR_ENABLE);
361 value |= AT803X_INTR_ENABLE_WOL;
362 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
365 value = phy_read(phydev, AT803X_INTR_STATUS);
367 value = phy_read(phydev, AT803X_INTR_ENABLE);
368 value &= (~AT803X_INTR_ENABLE_WOL);
369 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
372 value = phy_read(phydev, AT803X_INTR_STATUS);
378 static void at803x_get_wol(struct phy_device *phydev,
379 struct ethtool_wolinfo *wol)
383 wol->supported = WAKE_MAGIC;
386 value = phy_read(phydev, AT803X_INTR_ENABLE);
387 if (value & AT803X_INTR_ENABLE_WOL)
388 wol->wolopts |= WAKE_MAGIC;
391 static int at803x_get_sset_count(struct phy_device *phydev)
393 return ARRAY_SIZE(at803x_hw_stats);
396 static void at803x_get_strings(struct phy_device *phydev, u8 *data)
400 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
401 strscpy(data + i * ETH_GSTRING_LEN,
402 at803x_hw_stats[i].string, ETH_GSTRING_LEN);
406 static u64 at803x_get_stat(struct phy_device *phydev, int i)
408 struct at803x_hw_stat stat = at803x_hw_stats[i];
409 struct at803x_priv *priv = phydev->priv;
413 if (stat.access_type == MMD)
414 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
416 val = phy_read(phydev, stat.reg);
421 val = val & stat.mask;
422 priv->stats[i] += val;
423 ret = priv->stats[i];
429 static void at803x_get_stats(struct phy_device *phydev,
430 struct ethtool_stats *stats, u64 *data)
434 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
435 data[i] = at803x_get_stat(phydev, i);
438 static int at803x_suspend(struct phy_device *phydev)
443 value = phy_read(phydev, AT803X_INTR_ENABLE);
444 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
447 value = BMCR_ISOLATE;
451 phy_modify(phydev, MII_BMCR, 0, value);
456 static int at803x_resume(struct phy_device *phydev)
458 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
461 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
462 unsigned int selector)
464 struct phy_device *phydev = rdev_get_drvdata(rdev);
467 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
468 0, AT803X_DEBUG_RGMII_1V8);
470 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
471 AT803X_DEBUG_RGMII_1V8, 0);
474 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
476 struct phy_device *phydev = rdev_get_drvdata(rdev);
479 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
483 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
486 static const struct regulator_ops vddio_regulator_ops = {
487 .list_voltage = regulator_list_voltage_table,
488 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
489 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
492 static const unsigned int vddio_voltage_table[] = {
497 static const struct regulator_desc vddio_desc = {
499 .of_match = of_match_ptr("vddio-regulator"),
500 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
501 .volt_table = vddio_voltage_table,
502 .ops = &vddio_regulator_ops,
503 .type = REGULATOR_VOLTAGE,
504 .owner = THIS_MODULE,
507 static const struct regulator_ops vddh_regulator_ops = {
510 static const struct regulator_desc vddh_desc = {
512 .of_match = of_match_ptr("vddh-regulator"),
515 .ops = &vddh_regulator_ops,
516 .type = REGULATOR_VOLTAGE,
517 .owner = THIS_MODULE,
520 static int at8031_register_regulators(struct phy_device *phydev)
522 struct at803x_priv *priv = phydev->priv;
523 struct device *dev = &phydev->mdio.dev;
524 struct regulator_config config = { };
527 config.driver_data = phydev;
529 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
530 if (IS_ERR(priv->vddio_rdev)) {
531 phydev_err(phydev, "failed to register VDDIO regulator\n");
532 return PTR_ERR(priv->vddio_rdev);
535 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
536 if (IS_ERR(priv->vddh_rdev)) {
537 phydev_err(phydev, "failed to register VDDH regulator\n");
538 return PTR_ERR(priv->vddh_rdev);
544 static int at803x_parse_dt(struct phy_device *phydev)
546 struct device_node *node = phydev->mdio.dev.of_node;
547 struct at803x_priv *priv = phydev->priv;
548 u32 freq, strength, tw;
552 if (!IS_ENABLED(CONFIG_OF_MDIO))
555 if (of_property_read_bool(node, "qca,disable-smarteee"))
556 priv->flags |= AT803X_DISABLE_SMARTEEE;
558 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
559 if (!tw || tw > 255) {
560 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
563 priv->smarteee_lpi_tw_1g = tw;
566 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
567 if (!tw || tw > 255) {
568 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
571 priv->smarteee_lpi_tw_100m = tw;
574 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
578 sel = AT803X_CLK_OUT_25MHZ_XTAL;
581 sel = AT803X_CLK_OUT_50MHZ_PLL;
584 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
587 sel = AT803X_CLK_OUT_125MHZ_PLL;
590 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
594 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
595 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
597 /* Fixup for the AR8030/AR8035. This chip has another mask and
598 * doesn't support the DSP reference. Eg. the lowest bit of the
599 * mask. The upper two bits select the same frequencies. Mask
600 * the lowest bit here.
603 * There was no datasheet for the AR8030 available so this is
604 * just a guess. But the AR8035 is listed as pin compatible
605 * to the AR8030 so there might be a good chance it works on
608 if (phydev->drv->phy_id == ATH8030_PHY_ID ||
609 phydev->drv->phy_id == ATH8035_PHY_ID) {
610 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
611 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
615 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
617 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
619 case AR803X_STRENGTH_FULL:
620 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
622 case AR803X_STRENGTH_HALF:
623 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
625 case AR803X_STRENGTH_QUARTER:
626 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
629 phydev_err(phydev, "invalid qca,clk-out-strength\n");
634 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
637 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
638 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
639 priv->flags |= AT803X_KEEP_PLL_ENABLED;
641 ret = at8031_register_regulators(phydev);
645 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
647 if (IS_ERR(priv->vddio)) {
648 phydev_err(phydev, "failed to get VDDIO regulator\n");
649 return PTR_ERR(priv->vddio);
656 static int at803x_probe(struct phy_device *phydev)
658 struct device *dev = &phydev->mdio.dev;
659 struct at803x_priv *priv;
662 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
668 ret = at803x_parse_dt(phydev);
673 ret = regulator_enable(priv->vddio);
678 /* Some bootloaders leave the fiber page selected.
679 * Switch to the copper page, as otherwise we read
680 * the PHY capabilities from the fiber side.
682 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
683 phy_lock_mdio_bus(phydev);
684 ret = at803x_write_page(phydev, AT803X_PAGE_COPPER);
685 phy_unlock_mdio_bus(phydev);
694 regulator_disable(priv->vddio);
699 static void at803x_remove(struct phy_device *phydev)
701 struct at803x_priv *priv = phydev->priv;
704 regulator_disable(priv->vddio);
707 static int at803x_get_features(struct phy_device *phydev)
711 err = genphy_read_abilities(phydev);
715 if (phydev->drv->phy_id != ATH8031_PHY_ID)
718 /* AR8031/AR8033 have different status registers
719 * for copper and fiber operation. However, the
720 * extended status register is the same for both
723 * As a result of that, ESTATUS_1000_XFULL is set
724 * to 1 even when operating in copper TP mode.
726 * Remove this mode from the supported link modes,
727 * as this driver currently only supports copper
730 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
735 static int at803x_smarteee_config(struct phy_device *phydev)
737 struct at803x_priv *priv = phydev->priv;
738 u16 mask = 0, val = 0;
741 if (priv->flags & AT803X_DISABLE_SMARTEEE)
742 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
743 AT803X_MMD3_SMARTEEE_CTL3,
744 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
746 if (priv->smarteee_lpi_tw_1g) {
748 val |= priv->smarteee_lpi_tw_1g << 8;
750 if (priv->smarteee_lpi_tw_100m) {
752 val |= priv->smarteee_lpi_tw_100m;
757 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
762 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
763 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
764 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
767 static int at803x_clk_out_config(struct phy_device *phydev)
769 struct at803x_priv *priv = phydev->priv;
771 if (!priv->clk_25m_mask)
774 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
775 priv->clk_25m_mask, priv->clk_25m_reg);
778 static int at8031_pll_config(struct phy_device *phydev)
780 struct at803x_priv *priv = phydev->priv;
782 /* The default after hardware reset is PLL OFF. After a soft reset, the
783 * values are retained.
785 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
786 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
787 0, AT803X_DEBUG_PLL_ON);
789 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
790 AT803X_DEBUG_PLL_ON, 0);
793 static int at803x_config_init(struct phy_device *phydev)
797 /* The RX and TX delay default is:
798 * after HW reset: RX delay enabled and TX delay disabled
799 * after SW reset: RX delay enabled, while TX delay retains the
800 * value before reset.
802 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
803 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
804 ret = at803x_enable_rx_delay(phydev);
806 ret = at803x_disable_rx_delay(phydev);
810 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
811 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
812 ret = at803x_enable_tx_delay(phydev);
814 ret = at803x_disable_tx_delay(phydev);
818 ret = at803x_smarteee_config(phydev);
822 ret = at803x_clk_out_config(phydev);
826 if (phydev->drv->phy_id == ATH8031_PHY_ID) {
827 ret = at8031_pll_config(phydev);
832 /* Ar803x extended next page bit is enabled by default. Cisco
833 * multigig switches read this bit and attempt to negotiate 10Gbps
834 * rates even if the next page bit is disabled. This is incorrect
835 * behaviour but we still need to accommodate it. XNP is only needed
836 * for 10Gbps support, so disable XNP.
838 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
841 static int at803x_ack_interrupt(struct phy_device *phydev)
845 err = phy_read(phydev, AT803X_INTR_STATUS);
847 return (err < 0) ? err : 0;
850 static int at803x_config_intr(struct phy_device *phydev)
855 value = phy_read(phydev, AT803X_INTR_ENABLE);
857 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
858 /* Clear any pending interrupts */
859 err = at803x_ack_interrupt(phydev);
863 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
864 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
865 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
866 value |= AT803X_INTR_ENABLE_LINK_FAIL;
867 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
869 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
871 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
875 /* Clear any pending interrupts */
876 err = at803x_ack_interrupt(phydev);
882 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
884 int irq_status, int_enabled;
886 irq_status = phy_read(phydev, AT803X_INTR_STATUS);
887 if (irq_status < 0) {
892 /* Read the current enabled interrupts */
893 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
894 if (int_enabled < 0) {
899 /* See if this was one of our enabled interrupts */
900 if (!(irq_status & int_enabled))
903 phy_trigger_machine(phydev);
908 static void at803x_link_change_notify(struct phy_device *phydev)
911 * Conduct a hardware reset for AT8030 every time a link loss is
912 * signalled. This is necessary to circumvent a hardware bug that
913 * occurs when the cable is unplugged while TX packets are pending
914 * in the FIFO. In such cases, the FIFO enters an error mode it
915 * cannot recover from by software.
917 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
918 struct at803x_context context;
920 at803x_context_save(phydev, &context);
922 phy_device_reset(phydev, 1);
924 phy_device_reset(phydev, 0);
927 at803x_context_restore(phydev, &context);
929 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
933 static int at803x_read_status(struct phy_device *phydev)
935 int ss, err, old_link = phydev->link;
937 /* Update the link, but return if there was an error */
938 err = genphy_update_link(phydev);
942 /* why bother the PHY if nothing can have changed */
943 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
946 phydev->speed = SPEED_UNKNOWN;
947 phydev->duplex = DUPLEX_UNKNOWN;
949 phydev->asym_pause = 0;
951 err = genphy_read_lpa(phydev);
955 /* Read the AT8035 PHY-Specific Status register, which indicates the
956 * speed and duplex that the PHY is actually using, irrespective of
957 * whether we are in autoneg mode or not.
959 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
963 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
966 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
970 switch (ss & AT803X_SS_SPEED_MASK) {
971 case AT803X_SS_SPEED_10:
972 phydev->speed = SPEED_10;
974 case AT803X_SS_SPEED_100:
975 phydev->speed = SPEED_100;
977 case AT803X_SS_SPEED_1000:
978 phydev->speed = SPEED_1000;
981 if (ss & AT803X_SS_DUPLEX)
982 phydev->duplex = DUPLEX_FULL;
984 phydev->duplex = DUPLEX_HALF;
986 if (ss & AT803X_SS_MDIX)
987 phydev->mdix = ETH_TP_MDI_X;
989 phydev->mdix = ETH_TP_MDI;
991 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
992 case AT803X_SFC_MANUAL_MDI:
993 phydev->mdix_ctrl = ETH_TP_MDI;
995 case AT803X_SFC_MANUAL_MDIX:
996 phydev->mdix_ctrl = ETH_TP_MDI_X;
998 case AT803X_SFC_AUTOMATIC_CROSSOVER:
999 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1004 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1005 phy_resolve_aneg_pause(phydev);
1010 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1016 val = AT803X_SFC_MANUAL_MDI;
1019 val = AT803X_SFC_MANUAL_MDIX;
1021 case ETH_TP_MDI_AUTO:
1022 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1028 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1029 AT803X_SFC_MDI_CROSSOVER_MODE_M,
1030 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1033 static int at803x_config_aneg(struct phy_device *phydev)
1037 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1041 /* Changes of the midx bits are disruptive to the normal operation;
1042 * therefore any changes to these registers must be followed by a
1043 * software reset to take effect.
1046 ret = genphy_soft_reset(phydev);
1051 return genphy_config_aneg(phydev);
1054 static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1058 val = phy_read(phydev, AT803X_SMART_SPEED);
1062 if (val & AT803X_SMART_SPEED_ENABLE)
1063 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1065 *d = DOWNSHIFT_DEV_DISABLE;
1070 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1076 case DOWNSHIFT_DEV_DEFAULT_COUNT:
1077 cnt = AT803X_DEFAULT_DOWNSHIFT;
1079 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1080 set = AT803X_SMART_SPEED_ENABLE |
1081 AT803X_SMART_SPEED_BYPASS_TIMER |
1082 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1083 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1085 case DOWNSHIFT_DEV_DISABLE:
1087 mask = AT803X_SMART_SPEED_ENABLE |
1088 AT803X_SMART_SPEED_BYPASS_TIMER;
1094 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1096 /* After changing the smart speed settings, we need to perform a
1097 * software reset, use phy_init_hw() to make sure we set the
1098 * reapply any values which might got lost during software reset.
1101 ret = phy_init_hw(phydev);
1106 static int at803x_get_tunable(struct phy_device *phydev,
1107 struct ethtool_tunable *tuna, void *data)
1110 case ETHTOOL_PHY_DOWNSHIFT:
1111 return at803x_get_downshift(phydev, data);
1117 static int at803x_set_tunable(struct phy_device *phydev,
1118 struct ethtool_tunable *tuna, const void *data)
1121 case ETHTOOL_PHY_DOWNSHIFT:
1122 return at803x_set_downshift(phydev, *(const u8 *)data);
1128 static int at803x_cable_test_result_trans(u16 status)
1130 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1131 case AT803X_CDT_STATUS_STAT_NORMAL:
1132 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1133 case AT803X_CDT_STATUS_STAT_SHORT:
1134 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1135 case AT803X_CDT_STATUS_STAT_OPEN:
1136 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1137 case AT803X_CDT_STATUS_STAT_FAIL:
1139 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1143 static bool at803x_cdt_test_failed(u16 status)
1145 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1146 AT803X_CDT_STATUS_STAT_FAIL;
1149 static bool at803x_cdt_fault_length_valid(u16 status)
1151 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1152 case AT803X_CDT_STATUS_STAT_OPEN:
1153 case AT803X_CDT_STATUS_STAT_SHORT:
1159 static int at803x_cdt_fault_length(u16 status)
1163 /* According to the datasheet the distance to the fault is
1164 * DELTA_TIME * 0.824 meters.
1166 * The author suspect the correct formula is:
1168 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1170 * where c is the speed of light, VF is the velocity factor of
1171 * the twisted pair cable, 125MHz the counter frequency and
1172 * we need to divide by 2 because the hardware will measure the
1173 * round trip time to the fault and back to the PHY.
1175 * With a VF of 0.69 we get the factor 0.824 mentioned in the
1178 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
1180 return (dt * 824) / 10;
1183 static int at803x_cdt_start(struct phy_device *phydev, int pair)
1187 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1188 AT803X_CDT_ENABLE_TEST;
1190 return phy_write(phydev, AT803X_CDT, cdt);
1193 static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
1197 /* One test run takes about 25ms */
1198 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1199 !(val & AT803X_CDT_ENABLE_TEST),
1200 30000, 100000, true);
1202 return ret < 0 ? ret : 0;
1205 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1207 static const int ethtool_pair[] = {
1208 ETHTOOL_A_CABLE_PAIR_A,
1209 ETHTOOL_A_CABLE_PAIR_B,
1210 ETHTOOL_A_CABLE_PAIR_C,
1211 ETHTOOL_A_CABLE_PAIR_D,
1215 ret = at803x_cdt_start(phydev, pair);
1219 ret = at803x_cdt_wait_for_completion(phydev);
1223 val = phy_read(phydev, AT803X_CDT_STATUS);
1227 if (at803x_cdt_test_failed(val))
1230 ethnl_cable_test_result(phydev, ethtool_pair[pair],
1231 at803x_cable_test_result_trans(val));
1233 if (at803x_cdt_fault_length_valid(val))
1234 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1235 at803x_cdt_fault_length(val));
1240 static int at803x_cable_test_get_status(struct phy_device *phydev,
1243 unsigned long pair_mask;
1247 if (phydev->phy_id == ATH9331_PHY_ID ||
1248 phydev->phy_id == ATH8032_PHY_ID ||
1249 phydev->phy_id == QCA9561_PHY_ID)
1256 /* According to the datasheet the CDT can be performed when
1257 * there is no link partner or when the link partner is
1258 * auto-negotiating. Starting the test will restart the AN
1259 * automatically. It seems that doing this repeatedly we will
1260 * get a slot where our link partner won't disturb our
1263 while (pair_mask && retries--) {
1264 for_each_set_bit(pair, &pair_mask, 4) {
1265 ret = at803x_cable_test_one_pair(phydev, pair);
1269 clear_bit(pair, &pair_mask);
1280 static int at803x_cable_test_start(struct phy_device *phydev)
1282 /* Enable auto-negotiation, but advertise no capabilities, no link
1283 * will be established. A restart of the auto-negotiation is not
1284 * required, because the cable test will automatically break the link.
1286 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1287 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1288 if (phydev->phy_id != ATH9331_PHY_ID &&
1289 phydev->phy_id != ATH8032_PHY_ID &&
1290 phydev->phy_id != QCA9561_PHY_ID)
1291 phy_write(phydev, MII_CTRL1000, 0);
1293 /* we do all the (time consuming) work later */
1297 static int qca83xx_config_init(struct phy_device *phydev)
1301 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1303 switch (switch_revision) {
1305 /* For 100M waveform */
1306 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
1307 /* Turn on Gigabit clock */
1308 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
1312 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1315 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1316 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
1317 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
1318 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1322 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
1323 * Disable on init and enable only with 100m speed following
1324 * qca original source code.
1326 if (phydev->drv->phy_id == QCA8327_A_PHY_ID ||
1327 phydev->drv->phy_id == QCA8327_B_PHY_ID)
1328 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1329 QCA8327_DEBUG_MANU_CTRL_EN, 0);
1331 /* Following original QCA sourcecode set port to prefer master */
1332 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
1337 static void qca83xx_link_change_notify(struct phy_device *phydev)
1339 /* QCA8337 doesn't require DAC Amplitude adjustement */
1340 if (phydev->drv->phy_id == QCA8337_PHY_ID)
1343 /* Set DAC Amplitude adjustment to +6% for 100m on link running */
1344 if (phydev->state == PHY_RUNNING) {
1345 if (phydev->speed == SPEED_100)
1346 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1347 QCA8327_DEBUG_MANU_CTRL_EN,
1348 QCA8327_DEBUG_MANU_CTRL_EN);
1350 /* Reset DAC Amplitude adjustment */
1351 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1352 QCA8327_DEBUG_MANU_CTRL_EN, 0);
1356 static int qca83xx_resume(struct phy_device *phydev)
1360 /* Skip reset if not suspended */
1361 if (!phydev->suspended)
1364 /* Reinit the port, reset values set by suspend */
1365 qca83xx_config_init(phydev);
1367 /* Reset the port on port resume */
1368 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1370 /* On resume from suspend the switch execute a reset and
1371 * restart auto-negotiation. Wait for reset to complete.
1373 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1374 50000, 600000, true);
1383 static int qca83xx_suspend(struct phy_device *phydev)
1387 /* Only QCA8337 support actual suspend.
1388 * QCA8327 cause port unreliability when phy suspend
1391 if (phydev->drv->phy_id == QCA8337_PHY_ID) {
1392 genphy_suspend(phydev);
1394 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
1395 phy_modify(phydev, MII_BMCR, mask, 0);
1398 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
1399 AT803X_DEBUG_GATE_CLK_IN1000, 0);
1401 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1402 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
1403 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
1408 static struct phy_driver at803x_driver[] = {
1410 /* Qualcomm Atheros AR8035 */
1411 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
1412 .name = "Qualcomm Atheros AR8035",
1413 .flags = PHY_POLL_CABLE_TEST,
1414 .probe = at803x_probe,
1415 .remove = at803x_remove,
1416 .config_aneg = at803x_config_aneg,
1417 .config_init = at803x_config_init,
1418 .soft_reset = genphy_soft_reset,
1419 .set_wol = at803x_set_wol,
1420 .get_wol = at803x_get_wol,
1421 .suspend = at803x_suspend,
1422 .resume = at803x_resume,
1423 /* PHY_GBIT_FEATURES */
1424 .read_status = at803x_read_status,
1425 .config_intr = at803x_config_intr,
1426 .handle_interrupt = at803x_handle_interrupt,
1427 .get_tunable = at803x_get_tunable,
1428 .set_tunable = at803x_set_tunable,
1429 .cable_test_start = at803x_cable_test_start,
1430 .cable_test_get_status = at803x_cable_test_get_status,
1432 /* Qualcomm Atheros AR8030 */
1433 .phy_id = ATH8030_PHY_ID,
1434 .name = "Qualcomm Atheros AR8030",
1435 .phy_id_mask = AT8030_PHY_ID_MASK,
1436 .probe = at803x_probe,
1437 .remove = at803x_remove,
1438 .config_init = at803x_config_init,
1439 .link_change_notify = at803x_link_change_notify,
1440 .set_wol = at803x_set_wol,
1441 .get_wol = at803x_get_wol,
1442 .suspend = at803x_suspend,
1443 .resume = at803x_resume,
1444 /* PHY_BASIC_FEATURES */
1445 .config_intr = at803x_config_intr,
1446 .handle_interrupt = at803x_handle_interrupt,
1448 /* Qualcomm Atheros AR8031/AR8033 */
1449 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1450 .name = "Qualcomm Atheros AR8031/AR8033",
1451 .flags = PHY_POLL_CABLE_TEST,
1452 .probe = at803x_probe,
1453 .remove = at803x_remove,
1454 .config_init = at803x_config_init,
1455 .config_aneg = at803x_config_aneg,
1456 .soft_reset = genphy_soft_reset,
1457 .set_wol = at803x_set_wol,
1458 .get_wol = at803x_get_wol,
1459 .suspend = at803x_suspend,
1460 .resume = at803x_resume,
1461 .read_page = at803x_read_page,
1462 .write_page = at803x_write_page,
1463 .get_features = at803x_get_features,
1464 .read_status = at803x_read_status,
1465 .config_intr = &at803x_config_intr,
1466 .handle_interrupt = at803x_handle_interrupt,
1467 .get_tunable = at803x_get_tunable,
1468 .set_tunable = at803x_set_tunable,
1469 .cable_test_start = at803x_cable_test_start,
1470 .cable_test_get_status = at803x_cable_test_get_status,
1472 /* Qualcomm Atheros AR8032 */
1473 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1474 .name = "Qualcomm Atheros AR8032",
1475 .probe = at803x_probe,
1476 .remove = at803x_remove,
1477 .flags = PHY_POLL_CABLE_TEST,
1478 .config_init = at803x_config_init,
1479 .link_change_notify = at803x_link_change_notify,
1480 .set_wol = at803x_set_wol,
1481 .get_wol = at803x_get_wol,
1482 .suspend = at803x_suspend,
1483 .resume = at803x_resume,
1484 /* PHY_BASIC_FEATURES */
1485 .config_intr = at803x_config_intr,
1486 .handle_interrupt = at803x_handle_interrupt,
1487 .cable_test_start = at803x_cable_test_start,
1488 .cable_test_get_status = at803x_cable_test_get_status,
1490 /* ATHEROS AR9331 */
1491 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1492 .name = "Qualcomm Atheros AR9331 built-in PHY",
1493 .suspend = at803x_suspend,
1494 .resume = at803x_resume,
1495 .flags = PHY_POLL_CABLE_TEST,
1496 /* PHY_BASIC_FEATURES */
1497 .config_intr = &at803x_config_intr,
1498 .handle_interrupt = at803x_handle_interrupt,
1499 .cable_test_start = at803x_cable_test_start,
1500 .cable_test_get_status = at803x_cable_test_get_status,
1501 .read_status = at803x_read_status,
1502 .soft_reset = genphy_soft_reset,
1503 .config_aneg = at803x_config_aneg,
1505 /* Qualcomm Atheros QCA9561 */
1506 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
1507 .name = "Qualcomm Atheros QCA9561 built-in PHY",
1508 .suspend = at803x_suspend,
1509 .resume = at803x_resume,
1510 .flags = PHY_POLL_CABLE_TEST,
1511 /* PHY_BASIC_FEATURES */
1512 .config_intr = &at803x_config_intr,
1513 .handle_interrupt = at803x_handle_interrupt,
1514 .cable_test_start = at803x_cable_test_start,
1515 .cable_test_get_status = at803x_cable_test_get_status,
1516 .read_status = at803x_read_status,
1517 .soft_reset = genphy_soft_reset,
1518 .config_aneg = at803x_config_aneg,
1521 .phy_id = QCA8337_PHY_ID,
1522 .phy_id_mask = QCA8K_PHY_ID_MASK,
1523 .name = "Qualcomm Atheros 8337 internal PHY",
1524 /* PHY_GBIT_FEATURES */
1525 .link_change_notify = qca83xx_link_change_notify,
1526 .probe = at803x_probe,
1527 .flags = PHY_IS_INTERNAL,
1528 .config_init = qca83xx_config_init,
1529 .soft_reset = genphy_soft_reset,
1530 .get_sset_count = at803x_get_sset_count,
1531 .get_strings = at803x_get_strings,
1532 .get_stats = at803x_get_stats,
1533 .suspend = qca83xx_suspend,
1534 .resume = qca83xx_resume,
1536 /* QCA8327-A from switch QCA8327-AL1A */
1537 .phy_id = QCA8327_A_PHY_ID,
1538 .phy_id_mask = QCA8K_PHY_ID_MASK,
1539 .name = "Qualcomm Atheros 8327-A internal PHY",
1540 /* PHY_GBIT_FEATURES */
1541 .link_change_notify = qca83xx_link_change_notify,
1542 .probe = at803x_probe,
1543 .flags = PHY_IS_INTERNAL,
1544 .config_init = qca83xx_config_init,
1545 .soft_reset = genphy_soft_reset,
1546 .get_sset_count = at803x_get_sset_count,
1547 .get_strings = at803x_get_strings,
1548 .get_stats = at803x_get_stats,
1549 .suspend = qca83xx_suspend,
1550 .resume = qca83xx_resume,
1552 /* QCA8327-B from switch QCA8327-BL1A */
1553 .phy_id = QCA8327_B_PHY_ID,
1554 .phy_id_mask = QCA8K_PHY_ID_MASK,
1555 .name = "Qualcomm Atheros 8327-B internal PHY",
1556 /* PHY_GBIT_FEATURES */
1557 .link_change_notify = qca83xx_link_change_notify,
1558 .probe = at803x_probe,
1559 .flags = PHY_IS_INTERNAL,
1560 .config_init = qca83xx_config_init,
1561 .soft_reset = genphy_soft_reset,
1562 .get_sset_count = at803x_get_sset_count,
1563 .get_strings = at803x_get_strings,
1564 .get_stats = at803x_get_stats,
1565 .suspend = qca83xx_suspend,
1566 .resume = qca83xx_resume,
1569 module_phy_driver(at803x_driver);
1571 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
1572 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1573 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1574 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1575 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1576 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1577 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
1578 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
1579 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
1580 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
1584 MODULE_DEVICE_TABLE(mdio, atheros_tbl);