drivers/net/phy/aquantia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Aquantia PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  */
   8 #include <config.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <phy.h>
  12 #include <u-boot/crc.h>
  13 #include <malloc.h>
  14 #include <asm/byteorder.h>
  15 #include <fs.h>
  16
  17 #define AQUNTIA_10G_CTL         0x20
  18 #define AQUNTIA_VENDOR_P1       0xc400
  19
  20 #define AQUNTIA_SPEED_LSB_MASK  0x2000
  21 #define AQUNTIA_SPEED_MSB_MASK  0x40
  22
  23 #define AQUANTIA_SYSTEM_INTERFACE_SR     0xe812
  24 #define  AQUANTIA_SYSTEM_INTERFACE_SR_READY     BIT(0)
  25 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
  26 #define AQUANTIA_FIRMWARE_ID             0x20
  27 #define AQUANTIA_RESERVED_STATUS         0xc885
  28 #define AQUANTIA_FIRMWARE_MAJOR_MASK     0xff00
  29 #define AQUANTIA_FIRMWARE_MINOR_MASK     0xff
  30 #define AQUANTIA_FIRMWARE_BUILD_MASK     0xf0
  31
  32 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
  33 #define AQUANTIA_SI_IN_USE_MASK          0x0078
  34 #define AQUANTIA_SI_USXGMII              0x0018
  35
  36 /* registers in MDIO_MMD_VEND1 region */
  37 #define AQUANTIA_VND1_GLOBAL_SC                 0x000
  38 #define  AQUANTIA_VND1_GLOBAL_SC_LP             BIT(0xb)
  39
  40 #define GLOBAL_FIRMWARE_ID 0x20
  41 #define GLOBAL_FAULT 0xc850
  42 #define GLOBAL_RSTATUS_1 0xc885
  43
  44 #define GLOBAL_ALARM_1 0xcc00
  45 #define SYSTEM_READY_BIT 0x40
  46
  47 #define GLOBAL_STANDARD_CONTROL 0x0
  48 #define SOFT_RESET BIT(15)
  49 #define LOW_POWER BIT(11)
  50
  51 #define MAILBOX_CONTROL 0x0200
  52 #define MAILBOX_EXECUTE BIT(15)
  53 #define MAILBOX_WRITE BIT(14)
  54 #define MAILBOX_RESET_CRC BIT(12)
  55 #define MAILBOX_BUSY BIT(8)
  56
  57 #define MAILBOX_CRC 0x0201
  58
  59 #define MAILBOX_ADDR_MSW 0x0202
  60 #define MAILBOX_ADDR_LSW 0x0203
  61
  62 #define MAILBOX_DATA_MSW 0x0204
  63 #define MAILBOX_DATA_LSW 0x0205
  64
  65 #define UP_CONTROL 0xc001
  66 #define UP_RESET BIT(15)
  67 #define UP_RUN_STALL_OVERRIDE BIT(6)
  68 #define UP_RUN_STALL BIT(0)
  69
  70 #define AQUANTIA_PMA_RX_VENDOR_P1               0xe400
  71 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK      GENMASK(1, 0)
  72 /* MDI reversal configured through registers */
  73 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG      BIT(1)
  74 /* MDI reversal enabled */
  75 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV      BIT(0)
  76
  77 /*
  78  * global start rate, the protocol associated with this speed is used by default
  79  * on SI.
  80  */
  81 #define AQUANTIA_VND1_GSTART_RATE               0x31a
  82 #define  AQUANTIA_VND1_GSTART_RATE_OFF          0
  83 #define  AQUANTIA_VND1_GSTART_RATE_100M         1
  84 #define  AQUANTIA_VND1_GSTART_RATE_1G           2
  85 #define  AQUANTIA_VND1_GSTART_RATE_10G          3
  86 #define  AQUANTIA_VND1_GSTART_RATE_2_5G         4
  87 #define  AQUANTIA_VND1_GSTART_RATE_5G           5
  88
  89 /* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
  90 #define AQUANTIA_VND1_GSYSCFG_BASE              0x31b
  91 #define AQUANTIA_VND1_GSYSCFG_100M              0
  92 #define AQUANTIA_VND1_GSYSCFG_1G                1
  93 #define AQUANTIA_VND1_GSYSCFG_2_5G              2
  94 #define AQUANTIA_VND1_GSYSCFG_5G                3
  95 #define AQUANTIA_VND1_GSYSCFG_10G               4
  96
  97 #define AQUANTIA_VND1_SMBUS0                    0xc485
  98 #define AQUANTIA_VND1_SMBUS1                    0xc495
  99
 100 /* addresses of memory segments in the phy */
 101 #define DRAM_BASE_ADDR 0x3FFE0000
 102 #define IRAM_BASE_ADDR 0x40000000
 103
 104 /* firmware image format constants */
 105 #define VERSION_STRING_SIZE 0x40
 106 #define VERSION_STRING_OFFSET 0x0200
 107 #define HEADER_OFFSET 0x300
 108
 109 /* driver private data */
 110 #define AQUANTIA_NA             0
 111 #define AQUANTIA_GEN1           1
 112 #define AQUANTIA_GEN2           2
 113 #define AQUANTIA_GEN3           3
 114
 115 #pragma pack(1)
 116 struct fw_header {
 117         u8 padding[4];
 118         u8 iram_offset[3];
 119         u8 iram_size[3];
 120         u8 dram_offset[3];
 121         u8 dram_size[3];
 122 };
 123
 124 #pragma pack()
 125
 126 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
 127 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
 128 {
 129         loff_t length, read;
 130         int ret;
 131         void *addr = NULL;
 132
 133         *fw_addr = NULL;
 134         *fw_length = 0;
 135         debug("Loading Acquantia microcode from %s %s\n",
 136               CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
 137         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 138         if (ret < 0)
 139                 goto cleanup;
 140
 141         ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
 142         if (ret < 0)
 143                 goto cleanup;
 144
 145         addr = malloc(length);
 146         if (!addr) {
 147                 ret = -ENOMEM;
 148                 goto cleanup;
 149         }
 150
 151         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 152         if (ret < 0)
 153                 goto cleanup;
 154
 155         ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
 156                       &read);
 157         if (ret < 0)
 158                 goto cleanup;
 159
 160         *fw_addr = addr;
 161         *fw_length = length;
 162         debug("Found Acquantia microcode.\n");
 163
 164 cleanup:
 165         if (ret < 0) {
 166                 printf("loading firmware file %s %s failed with error %d\n",
 167                        CONFIG_PHY_AQUANTIA_FW_PART,
 168                        CONFIG_PHY_AQUANTIA_FW_NAME, ret);
 169                 free(addr);
 170         }
 171         return ret;
 172 }
 173
 174 /* load data into the phy's memory */
 175 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
 176                                 const u8 *data, size_t len)
 177 {
 178         size_t pos;
 179         u16 crc = 0, up_crc;
 180
 181         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
 182         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
 183         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
 184
 185         for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
 186                 u32 word = 0;
 187
 188                 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
 189
 190                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
 191                           (word >> 16));
 192                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
 193                           word & 0xffff);
 194
 195                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
 196                           MAILBOX_EXECUTE | MAILBOX_WRITE);
 197
 198                 /* keep a big endian CRC to match the phy processor */
 199                 word = cpu_to_be32(word);
 200                 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
 201         }
 202
 203         up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
 204         if (crc != up_crc) {
 205                 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
 206                        phydev->dev->name, crc, up_crc);
 207                 return -EINVAL;
 208         }
 209         return 0;
 210 }
 211
 212 static u32 unpack_u24(const u8 *data)
 213 {
 214         return (data[2] << 16) + (data[1] << 8) + data[0];
 215 }
 216
 217 static int aquantia_upload_firmware(struct phy_device *phydev)
 218 {
 219         int ret;
 220         u8 *addr = NULL;
 221         size_t fw_length = 0;
 222         u16 calculated_crc, read_crc;
 223         char version[VERSION_STRING_SIZE];
 224         u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
 225         const struct fw_header *header;
 226
 227         ret = aquantia_read_fw(&addr, &fw_length);
 228         if (ret != 0)
 229                 return ret;
 230
 231         read_crc = (addr[fw_length - 2] << 8)  | addr[fw_length - 1];
 232         calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
 233         if (read_crc != calculated_crc) {
 234                 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
 235                        phydev->dev->name, read_crc, calculated_crc);
 236                 ret = -EINVAL;
 237                 goto done;
 238         }
 239
 240         /* Find the DRAM and IRAM sections within the firmware file. */
 241         primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
 242
 243         header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
 244
 245         iram_offset = primary_offset + unpack_u24(header->iram_offset);
 246         iram_size = unpack_u24(header->iram_size);
 247
 248         dram_offset = primary_offset + unpack_u24(header->dram_offset);
 249         dram_size = unpack_u24(header->dram_size);
 250
 251         debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
 252               primary_offset, iram_offset, iram_size, dram_offset, dram_size);
 253
 254         strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
 255                 VERSION_STRING_SIZE);
 256         printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
 257
 258         /* stall the microcprocessor */
 259         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 260                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
 261
 262         debug("loading dram 0x%08x from offset=%d size=%d\n",
 263               DRAM_BASE_ADDR, dram_offset, dram_size);
 264         ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
 265                                    dram_size);
 266         if (ret != 0)
 267                 goto done;
 268
 269         debug("loading iram 0x%08x from offset=%d size=%d\n",
 270               IRAM_BASE_ADDR, iram_offset, iram_size);
 271         ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
 272                                    iram_size);
 273         if (ret != 0)
 274                 goto done;
 275
 276         /* make sure soft reset and low power mode are clear */
 277         phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
 278
 279         /* Release the microprocessor. UP_RESET must be held for 100 usec. */
 280         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 281                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
 282
 283         udelay(100);
 284
 285         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
 286
 287         printf("%s firmare loading done.\n", phydev->dev->name);
 288 done:
 289         free(addr);
 290         return ret;
 291 }
 292 #else
 293 static int aquantia_upload_firmware(struct phy_device *phydev)
 294 {
 295         printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
 296         return -1;
 297 }
 298 #endif
 299
 300 struct {
 301         u16 syscfg;
 302         int cnt;
 303         u16 start_rate;
 304 } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
 305         [PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
 306                                            AQUANTIA_VND1_GSTART_RATE_1G},
 307         [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
 308                                            AQUANTIA_VND1_GSTART_RATE_2_5G},
 309         [PHY_INTERFACE_MODE_XFI] =        {0x100, AQUANTIA_VND1_GSYSCFG_10G,
 310                                            AQUANTIA_VND1_GSTART_RATE_10G},
 311         [PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,
 312                                            AQUANTIA_VND1_GSTART_RATE_10G},
 313 };
 314
 315 static int aquantia_set_proto(struct phy_device *phydev,
 316                               phy_interface_t interface)
 317 {
 318         int i;
 319
 320         if (!aquantia_syscfg[interface].cnt)
 321                 return 0;
 322
 323         /* set the default rate to enable the SI link */
 324         phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
 325                   aquantia_syscfg[interface].start_rate);
 326
 327         /* set selected protocol for all relevant line side link speeds */
 328         for (i = 0; i <= aquantia_syscfg[interface].cnt; i++)
 329                 phy_write(phydev, MDIO_MMD_VEND1,
 330                           AQUANTIA_VND1_GSYSCFG_BASE + i,
 331                           aquantia_syscfg[interface].syscfg);
 332         return 0;
 333 }
 334
 335 static int aquantia_dts_config(struct phy_device *phydev)
 336 {
 337 #ifdef CONFIG_DM_ETH
 338         ofnode node = phydev->node;
 339         u32 prop;
 340         u16 reg;
 341
 342         /* this code only works on gen2 and gen3 PHYs */
 343         if (phydev->drv->data != AQUANTIA_GEN2 &&
 344             phydev->drv->data != AQUANTIA_GEN3)
 345                 return -ENOTSUPP;
 346
 347         if (!ofnode_valid(node))
 348                 return 0;
 349
 350         if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
 351                 debug("mdi-reversal = %d\n", (int)prop);
 352                 reg =  phy_read(phydev, MDIO_MMD_PMAPMD,
 353                                 AQUANTIA_PMA_RX_VENDOR_P1);
 354                 reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
 355                 reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
 356                 reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
 357                 phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
 358                           reg);
 359         }
 360         if (!ofnode_read_u32(node, "smb-addr", &prop)) {
 361                 debug("smb-addr = %x\n", (int)prop);
 362                 /*
 363                  * there are two addresses here, normally just one bus would
 364                  * be in use so we're setting both regs using the same DT
 365                  * property.
 366                  */
 367                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
 368                           (u16)(prop << 1));
 369                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
 370                           (u16)(prop << 1));
 371         }
 372
 373 #endif
 374         return 0;
 375 }
 376
 377 static bool aquantia_link_is_up(struct phy_device *phydev)
 378 {
 379         u16 reg, regmask;
 380         int devad, regnum;
 381
 382         /*
 383          * On Gen 2 and 3 we have a bit that indicates that both system and
 384          * line side are ready for data, use that if possible.
 385          */
 386         if (phydev->drv->data == AQUANTIA_GEN2 ||
 387             phydev->drv->data == AQUANTIA_GEN3) {
 388                 devad = MDIO_MMD_PHYXS;
 389                 regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
 390                 regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
 391         } else {
 392                 devad = MDIO_MMD_AN;
 393                 regnum = MDIO_STAT1;
 394                 regmask = MDIO_AN_STAT1_COMPLETE;
 395         }
 396         /* the register should be latched, do a double read */
 397         phy_read(phydev, devad, regnum);
 398         reg = phy_read(phydev, devad, regnum);
 399
 400         return !!(reg & regmask);
 401 }
 402
 403 int aquantia_config(struct phy_device *phydev)
 404 {
 405         int interface = phydev->interface;
 406         u32 val, id, rstatus, fault;
 407         u32 reg_val1 = 0;
 408         int num_retries = 5;
 409         int usx_an = 0;
 410
 411         /*
 412          * check if the system is out of reset and init sequence completed.
 413          * chip-wide reset for gen1 quad phys takes longer
 414          */
 415         while (--num_retries) {
 416                 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
 417                 if (rstatus & SYSTEM_READY_BIT)
 418                         break;
 419                 mdelay(10);
 420         }
 421
 422         id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
 423         rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
 424         fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
 425
 426         if (id != 0)
 427                 debug("%s running firmware version %X.%X.%X\n",
 428                       phydev->dev->name, (id >> 8), id & 0xff,
 429                       (rstatus >> 4) & 0xf);
 430
 431         if (fault != 0)
 432                 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
 433
 434         if (id == 0 || fault != 0) {
 435                 int ret;
 436
 437                 ret = aquantia_upload_firmware(phydev);
 438                 if (ret != 0)
 439                         return ret;
 440         }
 441         /*
 442          * for backward compatibility convert XGMII into either XFI or USX based
 443          * on FW config
 444          */
 445         if (interface == PHY_INTERFACE_MODE_XGMII) {
 446                 debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
 447
 448                 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
 449                                     AQUANTIA_SYSTEM_INTERFACE_SR);
 450                 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
 451                         interface = PHY_INTERFACE_MODE_USXGMII;
 452                 else
 453                         interface = PHY_INTERFACE_MODE_XFI;
 454         }
 455
 456         /*
 457          * if link is up already we can just use it, otherwise configure
 458          * the protocols in the PHY.  If link is down set the system
 459          * interface protocol to use based on phydev->interface
 460          */
 461         if (!aquantia_link_is_up(phydev) &&
 462             (phydev->drv->data == AQUANTIA_GEN2 ||
 463              phydev->drv->data == AQUANTIA_GEN3)) {
 464                 /* set PHY in low power mode so we can configure protocols */
 465                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
 466                           AQUANTIA_VND1_GLOBAL_SC_LP);
 467                 mdelay(10);
 468
 469                 /* configure protocol based on phydev->interface */
 470                 aquantia_set_proto(phydev, interface);
 471                 /* apply custom configuration based on DT */
 472                 aquantia_dts_config(phydev);
 473
 474                 /* wake PHY back up */
 475                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
 476                 mdelay(10);
 477         }
 478
 479         val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 480
 481         switch (interface) {
 482         case PHY_INTERFACE_MODE_SGMII:
 483                 /* 1000BASE-T mode */
 484                 phydev->advertising = SUPPORTED_1000baseT_Full;
 485                 phydev->supported = phydev->advertising;
 486
 487                 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
 488                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 489                 break;
 490         case PHY_INTERFACE_MODE_USXGMII:
 491                 usx_an = 1;
 492                 /* FALLTHROUGH */
 493         case PHY_INTERFACE_MODE_XFI:
 494                 /* 10GBASE-T mode */
 495                 phydev->advertising = SUPPORTED_10000baseT_Full;
 496                 phydev->supported = phydev->advertising;
 497
 498                 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
 499                     !(val & AQUNTIA_SPEED_MSB_MASK))
 500                         phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
 501                                   AQUNTIA_SPEED_LSB_MASK |
 502                                   AQUNTIA_SPEED_MSB_MASK);
 503
 504                 /* If SI is USXGMII then start USXGMII autoneg */
 505                 reg_val1 =  phy_read(phydev, MDIO_MMD_PHYXS,
 506                                      AQUANTIA_VENDOR_PROVISIONING_REG);
 507
 508                 if (usx_an) {
 509                         reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 510                         debug("%s: system interface USXGMII\n",
 511                               phydev->dev->name);
 512                 } else {
 513                         reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 514                         debug("%s: system interface XFI\n",
 515                               phydev->dev->name);
 516                 }
 517
 518                 phy_write(phydev, MDIO_MMD_PHYXS,
 519                           AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
 520                 break;
 521         case PHY_INTERFACE_MODE_SGMII_2500:
 522                 /* 2.5GBASE-T mode */
 523                 phydev->advertising = SUPPORTED_1000baseT_Full;
 524                 phydev->supported = phydev->advertising;
 525
 526                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
 527                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
 528                 break;
 529         case PHY_INTERFACE_MODE_MII:
 530                 /* 100BASE-TX mode */
 531                 phydev->advertising = SUPPORTED_100baseT_Full;
 532                 phydev->supported = phydev->advertising;
 533
 534                 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
 535                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 536                 break;
 537         };
 538
 539         val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
 540         reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
 541
 542         debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
 543               phydev->drv->name,
 544               (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
 545               reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
 546               (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
 547
 548         return 0;
 549 }
 550
 551 int aquantia_startup(struct phy_device *phydev)
 552 {
 553         u32 reg, speed;
 554         int i = 0;
 555
 556         phydev->duplex = DUPLEX_FULL;
 557
 558         /* if the AN is still in progress, wait till timeout. */
 559         if (!aquantia_link_is_up(phydev)) {
 560                 printf("%s Waiting for PHY auto negotiation to complete",
 561                        phydev->dev->name);
 562                 do {
 563                         udelay(1000);
 564                         if ((i++ % 500) == 0)
 565                                 printf(".");
 566                 } while (!aquantia_link_is_up(phydev) &&
 567                          i < (4 * PHY_ANEG_TIMEOUT));
 568
 569                 if (i > PHY_ANEG_TIMEOUT)
 570                         printf(" TIMEOUT !\n");
 571         }
 572
 573         /* Read twice because link state is latched and a
 574          * read moves the current state into the register */
 575         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 576         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 577         if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
 578                 phydev->link = 0;
 579         else
 580                 phydev->link = 1;
 581
 582         speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 583         if (speed & AQUNTIA_SPEED_MSB_MASK) {
 584                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 585                         phydev->speed = SPEED_10000;
 586                 else
 587                         phydev->speed = SPEED_1000;
 588         } else {
 589                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 590                         phydev->speed = SPEED_100;
 591                 else
 592                         phydev->speed = SPEED_10;
 593         }
 594
 595         return 0;
 596 }
 597
 598 struct phy_driver aq1202_driver = {
 599         .name = "Aquantia AQ1202",
 600         .uid = 0x3a1b445,
 601         .mask = 0xfffffff0,
 602         .features = PHY_10G_FEATURES,
 603         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 604                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 605                         MDIO_MMD_VEND1),
 606         .config = &aquantia_config,
 607         .startup = &aquantia_startup,
 608         .shutdown = &gen10g_shutdown,
 609 };
 610
 611 struct phy_driver aq2104_driver = {
 612         .name = "Aquantia AQ2104",
 613         .uid = 0x3a1b460,
 614         .mask = 0xfffffff0,
 615         .features = PHY_10G_FEATURES,
 616         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 617                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 618                         MDIO_MMD_VEND1),
 619         .config = &aquantia_config,
 620         .startup = &aquantia_startup,
 621         .shutdown = &gen10g_shutdown,
 622 };
 623
 624 struct phy_driver aqr105_driver = {
 625         .name = "Aquantia AQR105",
 626         .uid = 0x3a1b4a2,
 627         .mask = 0xfffffff0,
 628         .features = PHY_10G_FEATURES,
 629         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 630                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 631                         MDIO_MMD_VEND1),
 632         .config = &aquantia_config,
 633         .startup = &aquantia_startup,
 634         .shutdown = &gen10g_shutdown,
 635         .data = AQUANTIA_GEN1,
 636 };
 637
 638 struct phy_driver aqr106_driver = {
 639         .name = "Aquantia AQR106",
 640         .uid = 0x3a1b4d0,
 641         .mask = 0xfffffff0,
 642         .features = PHY_10G_FEATURES,
 643         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 644                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 645                         MDIO_MMD_VEND1),
 646         .config = &aquantia_config,
 647         .startup = &aquantia_startup,
 648         .shutdown = &gen10g_shutdown,
 649 };
 650
 651 struct phy_driver aqr107_driver = {
 652         .name = "Aquantia AQR107",
 653         .uid = 0x3a1b4e0,
 654         .mask = 0xfffffff0,
 655         .features = PHY_10G_FEATURES,
 656         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 657                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 658                         MDIO_MMD_VEND1),
 659         .config = &aquantia_config,
 660         .startup = &aquantia_startup,
 661         .shutdown = &gen10g_shutdown,
 662         .data = AQUANTIA_GEN2,
 663 };
 664
 665 struct phy_driver aqr112_driver = {
 666         .name = "Aquantia AQR112",
 667         .uid = 0x3a1b660,
 668         .mask = 0xfffffff0,
 669         .features = PHY_10G_FEATURES,
 670         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 671                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 672                  MDIO_MMD_VEND1),
 673         .config = &aquantia_config,
 674         .startup = &aquantia_startup,
 675         .shutdown = &gen10g_shutdown,
 676         .data = AQUANTIA_GEN3,
 677 };
 678
 679 struct phy_driver aqr405_driver = {
 680         .name = "Aquantia AQR405",
 681         .uid = 0x3a1b4b2,
 682         .mask = 0xfffffff0,
 683         .features = PHY_10G_FEATURES,
 684         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 685                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 686                  MDIO_MMD_VEND1),
 687         .config = &aquantia_config,
 688         .startup = &aquantia_startup,
 689         .shutdown = &gen10g_shutdown,
 690         .data = AQUANTIA_GEN1,
 691 };
 692
 693 struct phy_driver aqr412_driver = {
 694         .name = "Aquantia AQR412",
 695         .uid = 0x3a1b710,
 696         .mask = 0xfffffff0,
 697         .features = PHY_10G_FEATURES,
 698         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 699                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 700                  MDIO_MMD_VEND1),
 701         .config = &aquantia_config,
 702         .startup = &aquantia_startup,
 703         .shutdown = &gen10g_shutdown,
 704         .data = AQUANTIA_GEN3,
 705 };
 706
 707 int phy_aquantia_init(void)
 708 {
 709         phy_register(&aq1202_driver);
 710         phy_register(&aq2104_driver);
 711         phy_register(&aqr105_driver);
 712         phy_register(&aqr106_driver);
 713         phy_register(&aqr107_driver);
 714         phy_register(&aqr112_driver);
 715         phy_register(&aqr405_driver);
 716         phy_register(&aqr412_driver);
 717
 718         return 0;
 719 }