drivers/net/phy/aquantia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Aquantia PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  */
   8 #include <config.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <phy.h>
  12 #include <u-boot/crc.h>
  13 #include <malloc.h>
  14 #include <asm/byteorder.h>
  15 #include <fs.h>
  16
  17 #define AQUNTIA_10G_CTL         0x20
  18 #define AQUNTIA_VENDOR_P1       0xc400
  19
  20 #define AQUNTIA_SPEED_LSB_MASK  0x2000
  21 #define AQUNTIA_SPEED_MSB_MASK  0x40
  22
  23 #define AQUANTIA_SYSTEM_INTERFACE_SR     0xe812
  24 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
  25 #define AQUANTIA_FIRMWARE_ID             0x20
  26 #define AQUANTIA_RESERVED_STATUS         0xc885
  27 #define AQUANTIA_FIRMWARE_MAJOR_MASK     0xff00
  28 #define AQUANTIA_FIRMWARE_MINOR_MASK     0xff
  29 #define AQUANTIA_FIRMWARE_BUILD_MASK     0xf0
  30
  31 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
  32 #define AQUANTIA_SI_IN_USE_MASK          0x0078
  33 #define AQUANTIA_SI_USXGMII              0x0018
  34
  35 /* registers in MDIO_MMD_VEND1 region */
  36 #define GLOBAL_FIRMWARE_ID 0x20
  37 #define GLOBAL_FAULT 0xc850
  38 #define GLOBAL_RSTATUS_1 0xc885
  39
  40 #define GLOBAL_ALARM_1 0xcc00
  41 #define SYSTEM_READY_BIT 0x40
  42
  43 #define GLOBAL_STANDARD_CONTROL 0x0
  44 #define SOFT_RESET BIT(15)
  45 #define LOW_POWER BIT(11)
  46
  47 #define MAILBOX_CONTROL 0x0200
  48 #define MAILBOX_EXECUTE BIT(15)
  49 #define MAILBOX_WRITE BIT(14)
  50 #define MAILBOX_RESET_CRC BIT(12)
  51 #define MAILBOX_BUSY BIT(8)
  52
  53 #define MAILBOX_CRC 0x0201
  54
  55 #define MAILBOX_ADDR_MSW 0x0202
  56 #define MAILBOX_ADDR_LSW 0x0203
  57
  58 #define MAILBOX_DATA_MSW 0x0204
  59 #define MAILBOX_DATA_LSW 0x0205
  60
  61 #define UP_CONTROL 0xc001
  62 #define UP_RESET BIT(15)
  63 #define UP_RUN_STALL_OVERRIDE BIT(6)
  64 #define UP_RUN_STALL BIT(0)
  65
  66 /* addresses of memory segments in the phy */
  67 #define DRAM_BASE_ADDR 0x3FFE0000
  68 #define IRAM_BASE_ADDR 0x40000000
  69
  70 /* firmware image format constants */
  71 #define VERSION_STRING_SIZE 0x40
  72 #define VERSION_STRING_OFFSET 0x0200
  73 #define HEADER_OFFSET 0x300
  74
  75 /* driver private data */
  76 #define AQUANTIA_NA             0
  77 #define AQUANTIA_GEN1           1
  78 #define AQUANTIA_GEN2           2
  79 #define AQUANTIA_GEN3           3
  80
  81 #pragma pack(1)
  82 struct fw_header {
  83         u8 padding[4];
  84         u8 iram_offset[3];
  85         u8 iram_size[3];
  86         u8 dram_offset[3];
  87         u8 dram_size[3];
  88 };
  89
  90 #pragma pack()
  91
  92 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
  93 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
  94 {
  95         loff_t length, read;
  96         int ret;
  97         void *addr = NULL;
  98
  99         *fw_addr = NULL;
 100         *fw_length = 0;
 101         debug("Loading Acquantia microcode from %s %s\n",
 102               CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
 103         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 104         if (ret < 0)
 105                 goto cleanup;
 106
 107         ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
 108         if (ret < 0)
 109                 goto cleanup;
 110
 111         addr = malloc(length);
 112         if (!addr) {
 113                 ret = -ENOMEM;
 114                 goto cleanup;
 115         }
 116
 117         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 118         if (ret < 0)
 119                 goto cleanup;
 120
 121         ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
 122                       &read);
 123         if (ret < 0)
 124                 goto cleanup;
 125
 126         *fw_addr = addr;
 127         *fw_length = length;
 128         debug("Found Acquantia microcode.\n");
 129
 130 cleanup:
 131         if (ret < 0) {
 132                 printf("loading firmware file %s %s failed with error %d\n",
 133                        CONFIG_PHY_AQUANTIA_FW_PART,
 134                        CONFIG_PHY_AQUANTIA_FW_NAME, ret);
 135                 free(addr);
 136         }
 137         return ret;
 138 }
 139
 140 /* load data into the phy's memory */
 141 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
 142                                 const u8 *data, size_t len)
 143 {
 144         size_t pos;
 145         u16 crc = 0, up_crc;
 146
 147         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
 148         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
 149         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
 150
 151         for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
 152                 u32 word = 0;
 153
 154                 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
 155
 156                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
 157                           (word >> 16));
 158                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
 159                           word & 0xffff);
 160
 161                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
 162                           MAILBOX_EXECUTE | MAILBOX_WRITE);
 163
 164                 /* keep a big endian CRC to match the phy processor */
 165                 word = cpu_to_be32(word);
 166                 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
 167         }
 168
 169         up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
 170         if (crc != up_crc) {
 171                 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
 172                        phydev->dev->name, crc, up_crc);
 173                 return -EINVAL;
 174         }
 175         return 0;
 176 }
 177
 178 static u32 unpack_u24(const u8 *data)
 179 {
 180         return (data[2] << 16) + (data[1] << 8) + data[0];
 181 }
 182
 183 static int aquantia_upload_firmware(struct phy_device *phydev)
 184 {
 185         int ret;
 186         u8 *addr = NULL;
 187         size_t fw_length = 0;
 188         u16 calculated_crc, read_crc;
 189         char version[VERSION_STRING_SIZE];
 190         u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
 191         const struct fw_header *header;
 192
 193         ret = aquantia_read_fw(&addr, &fw_length);
 194         if (ret != 0)
 195                 return ret;
 196
 197         read_crc = (addr[fw_length - 2] << 8)  | addr[fw_length - 1];
 198         calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
 199         if (read_crc != calculated_crc) {
 200                 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
 201                        phydev->dev->name, read_crc, calculated_crc);
 202                 ret = -EINVAL;
 203                 goto done;
 204         }
 205
 206         /* Find the DRAM and IRAM sections within the firmware file. */
 207         primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
 208
 209         header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
 210
 211         iram_offset = primary_offset + unpack_u24(header->iram_offset);
 212         iram_size = unpack_u24(header->iram_size);
 213
 214         dram_offset = primary_offset + unpack_u24(header->dram_offset);
 215         dram_size = unpack_u24(header->dram_size);
 216
 217         debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
 218               primary_offset, iram_offset, iram_size, dram_offset, dram_size);
 219
 220         strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
 221                 VERSION_STRING_SIZE);
 222         printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
 223
 224         /* stall the microcprocessor */
 225         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 226                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
 227
 228         debug("loading dram 0x%08x from offset=%d size=%d\n",
 229               DRAM_BASE_ADDR, dram_offset, dram_size);
 230         ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
 231                                    dram_size);
 232         if (ret != 0)
 233                 goto done;
 234
 235         debug("loading iram 0x%08x from offset=%d size=%d\n",
 236               IRAM_BASE_ADDR, iram_offset, iram_size);
 237         ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
 238                                    iram_size);
 239         if (ret != 0)
 240                 goto done;
 241
 242         /* make sure soft reset and low power mode are clear */
 243         phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
 244
 245         /* Release the microprocessor. UP_RESET must be held for 100 usec. */
 246         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 247                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
 248
 249         udelay(100);
 250
 251         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
 252
 253         printf("%s firmare loading done.\n", phydev->dev->name);
 254 done:
 255         free(addr);
 256         return ret;
 257 }
 258 #else
 259 static int aquantia_upload_firmware(struct phy_device *phydev)
 260 {
 261         printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
 262         return -1;
 263 }
 264 #endif
 265
 266 int aquantia_config(struct phy_device *phydev)
 267 {
 268         int interface = phydev->interface;
 269         u32 val, id, rstatus, fault;
 270         u32 reg_val1 = 0;
 271         int num_retries = 5;
 272         int usx_an = 0;
 273
 274         /*
 275          * check if the system is out of reset and init sequence completed.
 276          * chip-wide reset for gen1 quad phys takes longer
 277          */
 278         while (--num_retries) {
 279                 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
 280                 if (rstatus & SYSTEM_READY_BIT)
 281                         break;
 282                 mdelay(10);
 283         }
 284
 285         id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
 286         rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
 287         fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
 288
 289         if (id != 0)
 290                 printf("%s running firmware version %X.%X.%X\n",
 291                        phydev->dev->name, (id >> 8), id & 0xff,
 292                        (rstatus >> 4) & 0xf);
 293
 294         if (fault != 0)
 295                 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
 296
 297         if (id == 0 || fault != 0) {
 298                 int ret;
 299
 300                 ret = aquantia_upload_firmware(phydev);
 301                 if (ret != 0)
 302                         return ret;
 303         }
 304         /*
 305          * for backward compatibility convert XGMII into either XFI or USX based
 306          * on FW config
 307          */
 308         if (interface == PHY_INTERFACE_MODE_XGMII) {
 309                 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
 310                                     AQUANTIA_SYSTEM_INTERFACE_SR);
 311                 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
 312                         interface = PHY_INTERFACE_MODE_USXGMII;
 313                 else
 314                         interface = PHY_INTERFACE_MODE_XFI;
 315         }
 316
 317         val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 318
 319         switch (interface) {
 320         case PHY_INTERFACE_MODE_SGMII:
 321                 /* 1000BASE-T mode */
 322                 phydev->advertising = SUPPORTED_1000baseT_Full;
 323                 phydev->supported = phydev->advertising;
 324
 325                 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
 326                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 327                 break;
 328         case PHY_INTERFACE_MODE_USXGMII:
 329                 usx_an = 1;
 330                 /* FALLTHROUGH */
 331         case PHY_INTERFACE_MODE_XFI:
 332                 /* 10GBASE-T mode */
 333                 phydev->advertising = SUPPORTED_10000baseT_Full;
 334                 phydev->supported = phydev->advertising;
 335
 336                 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
 337                     !(val & AQUNTIA_SPEED_MSB_MASK))
 338                         phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
 339                                   AQUNTIA_SPEED_LSB_MASK |
 340                                   AQUNTIA_SPEED_MSB_MASK);
 341
 342                 /* If SI is USXGMII then start USXGMII autoneg */
 343                 reg_val1 =  phy_read(phydev, MDIO_MMD_PHYXS,
 344                                      AQUANTIA_VENDOR_PROVISIONING_REG);
 345
 346                 if (usx_an) {
 347                         reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 348                         printf("%s: system interface USXGMII\n",
 349                                phydev->dev->name);
 350                 } else {
 351                         reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 352                         printf("%s: system interface XFI\n",
 353                                phydev->dev->name);
 354                 }
 355
 356                 phy_write(phydev, MDIO_MMD_PHYXS,
 357                           AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
 358                 break;
 359         case PHY_INTERFACE_MODE_SGMII_2500:
 360                 /* 2.5GBASE-T mode */
 361                 phydev->advertising = SUPPORTED_1000baseT_Full;
 362                 phydev->supported = phydev->advertising;
 363
 364                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
 365                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
 366                 break;
 367         case PHY_INTERFACE_MODE_MII:
 368                 /* 100BASE-TX mode */
 369                 phydev->advertising = SUPPORTED_100baseT_Full;
 370                 phydev->supported = phydev->advertising;
 371
 372                 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
 373                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 374                 break;
 375         };
 376
 377         val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
 378         reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
 379
 380         printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
 381                phydev->drv->name,
 382                (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
 383                reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
 384                (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
 385
 386         return 0;
 387 }
 388
 389 int aquantia_startup(struct phy_device *phydev)
 390 {
 391         u32 reg, speed;
 392         int i = 0;
 393
 394         phydev->duplex = DUPLEX_FULL;
 395
 396         /* if the AN is still in progress, wait till timeout. */
 397         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 398         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 399         if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
 400                 printf("%s Waiting for PHY auto negotiation to complete",
 401                        phydev->dev->name);
 402                 do {
 403                         udelay(1000);
 404                         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 405                         if ((i++ % 500) == 0)
 406                                 printf(".");
 407                 } while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
 408                          i < (4 * PHY_ANEG_TIMEOUT));
 409
 410                 if (i > PHY_ANEG_TIMEOUT)
 411                         printf(" TIMEOUT !\n");
 412         }
 413
 414         /* Read twice because link state is latched and a
 415          * read moves the current state into the register */
 416         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 417         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 418         if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
 419                 phydev->link = 0;
 420         else
 421                 phydev->link = 1;
 422
 423         speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 424         if (speed & AQUNTIA_SPEED_MSB_MASK) {
 425                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 426                         phydev->speed = SPEED_10000;
 427                 else
 428                         phydev->speed = SPEED_1000;
 429         } else {
 430                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 431                         phydev->speed = SPEED_100;
 432                 else
 433                         phydev->speed = SPEED_10;
 434         }
 435
 436         return 0;
 437 }
 438
 439 struct phy_driver aq1202_driver = {
 440         .name = "Aquantia AQ1202",
 441         .uid = 0x3a1b445,
 442         .mask = 0xfffffff0,
 443         .features = PHY_10G_FEATURES,
 444         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 445                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 446                         MDIO_MMD_VEND1),
 447         .config = &aquantia_config,
 448         .startup = &aquantia_startup,
 449         .shutdown = &gen10g_shutdown,
 450 };
 451
 452 struct phy_driver aq2104_driver = {
 453         .name = "Aquantia AQ2104",
 454         .uid = 0x3a1b460,
 455         .mask = 0xfffffff0,
 456         .features = PHY_10G_FEATURES,
 457         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 458                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 459                         MDIO_MMD_VEND1),
 460         .config = &aquantia_config,
 461         .startup = &aquantia_startup,
 462         .shutdown = &gen10g_shutdown,
 463 };
 464
 465 struct phy_driver aqr105_driver = {
 466         .name = "Aquantia AQR105",
 467         .uid = 0x3a1b4a2,
 468         .mask = 0xfffffff0,
 469         .features = PHY_10G_FEATURES,
 470         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 471                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 472                         MDIO_MMD_VEND1),
 473         .config = &aquantia_config,
 474         .startup = &aquantia_startup,
 475         .shutdown = &gen10g_shutdown,
 476         .data = AQUANTIA_GEN1,
 477 };
 478
 479 struct phy_driver aqr106_driver = {
 480         .name = "Aquantia AQR106",
 481         .uid = 0x3a1b4d0,
 482         .mask = 0xfffffff0,
 483         .features = PHY_10G_FEATURES,
 484         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 485                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 486                         MDIO_MMD_VEND1),
 487         .config = &aquantia_config,
 488         .startup = &aquantia_startup,
 489         .shutdown = &gen10g_shutdown,
 490 };
 491
 492 struct phy_driver aqr107_driver = {
 493         .name = "Aquantia AQR107",
 494         .uid = 0x3a1b4e0,
 495         .mask = 0xfffffff0,
 496         .features = PHY_10G_FEATURES,
 497         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 498                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 499                         MDIO_MMD_VEND1),
 500         .config = &aquantia_config,
 501         .startup = &aquantia_startup,
 502         .shutdown = &gen10g_shutdown,
 503         .data = AQUANTIA_GEN2,
 504 };
 505
 506 struct phy_driver aqr112_driver = {
 507         .name = "Aquantia AQR112",
 508         .uid = 0x3a1b660,
 509         .mask = 0xfffffff0,
 510         .features = PHY_10G_FEATURES,
 511         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 512                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 513                  MDIO_MMD_VEND1),
 514         .config = &aquantia_config,
 515         .startup = &aquantia_startup,
 516         .shutdown = &gen10g_shutdown,
 517         .data = AQUANTIA_GEN3,
 518 };
 519
 520 struct phy_driver aqr405_driver = {
 521         .name = "Aquantia AQR405",
 522         .uid = 0x3a1b4b2,
 523         .mask = 0xfffffff0,
 524         .features = PHY_10G_FEATURES,
 525         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 526                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 527                  MDIO_MMD_VEND1),
 528         .config = &aquantia_config,
 529         .startup = &aquantia_startup,
 530         .shutdown = &gen10g_shutdown,
 531         .data = AQUANTIA_GEN1,
 532 };
 533
 534 struct phy_driver aqr412_driver = {
 535         .name = "Aquantia AQR412",
 536         .uid = 0x3a1b710,
 537         .mask = 0xfffffff0,
 538         .features = PHY_10G_FEATURES,
 539         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 540                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 541                  MDIO_MMD_VEND1),
 542         .config = &aquantia_config,
 543         .startup = &aquantia_startup,
 544         .shutdown = &gen10g_shutdown,
 545         .data = AQUANTIA_GEN3,
 546 };
 547
 548 int phy_aquantia_init(void)
 549 {
 550         phy_register(&aq1202_driver);
 551         phy_register(&aq2104_driver);
 552         phy_register(&aqr105_driver);
 553         phy_register(&aqr106_driver);
 554         phy_register(&aqr107_driver);
 555         phy_register(&aqr112_driver);
 556         phy_register(&aqr405_driver);
 557         phy_register(&aqr412_driver);
 558
 559         return 0;
 560 }