drivers/net/phy/aquantia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Aquantia PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  */
   8 #include <config.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <phy.h>
  12 #include <u-boot/crc.h>
  13 #include <malloc.h>
  14 #include <asm/byteorder.h>
  15 #include <fs.h>
  16
  17 #define AQUNTIA_10G_CTL         0x20
  18 #define AQUNTIA_VENDOR_P1       0xc400
  19
  20 #define AQUNTIA_SPEED_LSB_MASK  0x2000
  21 #define AQUNTIA_SPEED_MSB_MASK  0x40
  22
  23 #define AQUANTIA_SYSTEM_INTERFACE_SR     0xe812
  24 #define  AQUANTIA_SYSTEM_INTERFACE_SR_READY     BIT(0)
  25 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
  26 #define AQUANTIA_FIRMWARE_ID             0x20
  27 #define AQUANTIA_RESERVED_STATUS         0xc885
  28 #define AQUANTIA_FIRMWARE_MAJOR_MASK     0xff00
  29 #define AQUANTIA_FIRMWARE_MINOR_MASK     0xff
  30 #define AQUANTIA_FIRMWARE_BUILD_MASK     0xf0
  31
  32 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
  33 #define AQUANTIA_SI_IN_USE_MASK          0x0078
  34 #define AQUANTIA_SI_USXGMII              0x0018
  35
  36 /* registers in MDIO_MMD_VEND1 region */
  37 #define AQUANTIA_VND1_GLOBAL_SC                 0x000
  38 #define  AQUANTIA_VND1_GLOBAL_SC_LP             BIT(0xb)
  39
  40 #define GLOBAL_FIRMWARE_ID 0x20
  41 #define GLOBAL_FAULT 0xc850
  42 #define GLOBAL_RSTATUS_1 0xc885
  43
  44 #define GLOBAL_ALARM_1 0xcc00
  45 #define SYSTEM_READY_BIT 0x40
  46
  47 #define GLOBAL_STANDARD_CONTROL 0x0
  48 #define SOFT_RESET BIT(15)
  49 #define LOW_POWER BIT(11)
  50
  51 #define MAILBOX_CONTROL 0x0200
  52 #define MAILBOX_EXECUTE BIT(15)
  53 #define MAILBOX_WRITE BIT(14)
  54 #define MAILBOX_RESET_CRC BIT(12)
  55 #define MAILBOX_BUSY BIT(8)
  56
  57 #define MAILBOX_CRC 0x0201
  58
  59 #define MAILBOX_ADDR_MSW 0x0202
  60 #define MAILBOX_ADDR_LSW 0x0203
  61
  62 #define MAILBOX_DATA_MSW 0x0204
  63 #define MAILBOX_DATA_LSW 0x0205
  64
  65 #define UP_CONTROL 0xc001
  66 #define UP_RESET BIT(15)
  67 #define UP_RUN_STALL_OVERRIDE BIT(6)
  68 #define UP_RUN_STALL BIT(0)
  69
  70 /*
  71  * global start rate, the protocol associated with this speed is used by default
  72  * on SI.
  73  */
  74 #define AQUANTIA_VND1_GSTART_RATE               0x31a
  75 #define  AQUANTIA_VND1_GSTART_RATE_OFF          0
  76 #define  AQUANTIA_VND1_GSTART_RATE_100M         1
  77 #define  AQUANTIA_VND1_GSTART_RATE_1G           2
  78 #define  AQUANTIA_VND1_GSTART_RATE_10G          3
  79 #define  AQUANTIA_VND1_GSTART_RATE_2_5G         4
  80 #define  AQUANTIA_VND1_GSTART_RATE_5G           5
  81
  82 /* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
  83 #define AQUANTIA_VND1_GSYSCFG_BASE              0x31b
  84 #define AQUANTIA_VND1_GSYSCFG_100M              0
  85 #define AQUANTIA_VND1_GSYSCFG_1G                1
  86 #define AQUANTIA_VND1_GSYSCFG_2_5G              2
  87 #define AQUANTIA_VND1_GSYSCFG_5G                3
  88 #define AQUANTIA_VND1_GSYSCFG_10G               4
  89
  90 /* addresses of memory segments in the phy */
  91 #define DRAM_BASE_ADDR 0x3FFE0000
  92 #define IRAM_BASE_ADDR 0x40000000
  93
  94 /* firmware image format constants */
  95 #define VERSION_STRING_SIZE 0x40
  96 #define VERSION_STRING_OFFSET 0x0200
  97 #define HEADER_OFFSET 0x300
  98
  99 /* driver private data */
 100 #define AQUANTIA_NA             0
 101 #define AQUANTIA_GEN1           1
 102 #define AQUANTIA_GEN2           2
 103 #define AQUANTIA_GEN3           3
 104
 105 #pragma pack(1)
 106 struct fw_header {
 107         u8 padding[4];
 108         u8 iram_offset[3];
 109         u8 iram_size[3];
 110         u8 dram_offset[3];
 111         u8 dram_size[3];
 112 };
 113
 114 #pragma pack()
 115
 116 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
 117 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
 118 {
 119         loff_t length, read;
 120         int ret;
 121         void *addr = NULL;
 122
 123         *fw_addr = NULL;
 124         *fw_length = 0;
 125         debug("Loading Acquantia microcode from %s %s\n",
 126               CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
 127         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 128         if (ret < 0)
 129                 goto cleanup;
 130
 131         ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
 132         if (ret < 0)
 133                 goto cleanup;
 134
 135         addr = malloc(length);
 136         if (!addr) {
 137                 ret = -ENOMEM;
 138                 goto cleanup;
 139         }
 140
 141         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 142         if (ret < 0)
 143                 goto cleanup;
 144
 145         ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
 146                       &read);
 147         if (ret < 0)
 148                 goto cleanup;
 149
 150         *fw_addr = addr;
 151         *fw_length = length;
 152         debug("Found Acquantia microcode.\n");
 153
 154 cleanup:
 155         if (ret < 0) {
 156                 printf("loading firmware file %s %s failed with error %d\n",
 157                        CONFIG_PHY_AQUANTIA_FW_PART,
 158                        CONFIG_PHY_AQUANTIA_FW_NAME, ret);
 159                 free(addr);
 160         }
 161         return ret;
 162 }
 163
 164 /* load data into the phy's memory */
 165 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
 166                                 const u8 *data, size_t len)
 167 {
 168         size_t pos;
 169         u16 crc = 0, up_crc;
 170
 171         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
 172         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
 173         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
 174
 175         for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
 176                 u32 word = 0;
 177
 178                 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
 179
 180                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
 181                           (word >> 16));
 182                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
 183                           word & 0xffff);
 184
 185                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
 186                           MAILBOX_EXECUTE | MAILBOX_WRITE);
 187
 188                 /* keep a big endian CRC to match the phy processor */
 189                 word = cpu_to_be32(word);
 190                 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
 191         }
 192
 193         up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
 194         if (crc != up_crc) {
 195                 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
 196                        phydev->dev->name, crc, up_crc);
 197                 return -EINVAL;
 198         }
 199         return 0;
 200 }
 201
 202 static u32 unpack_u24(const u8 *data)
 203 {
 204         return (data[2] << 16) + (data[1] << 8) + data[0];
 205 }
 206
 207 static int aquantia_upload_firmware(struct phy_device *phydev)
 208 {
 209         int ret;
 210         u8 *addr = NULL;
 211         size_t fw_length = 0;
 212         u16 calculated_crc, read_crc;
 213         char version[VERSION_STRING_SIZE];
 214         u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
 215         const struct fw_header *header;
 216
 217         ret = aquantia_read_fw(&addr, &fw_length);
 218         if (ret != 0)
 219                 return ret;
 220
 221         read_crc = (addr[fw_length - 2] << 8)  | addr[fw_length - 1];
 222         calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
 223         if (read_crc != calculated_crc) {
 224                 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
 225                        phydev->dev->name, read_crc, calculated_crc);
 226                 ret = -EINVAL;
 227                 goto done;
 228         }
 229
 230         /* Find the DRAM and IRAM sections within the firmware file. */
 231         primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
 232
 233         header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
 234
 235         iram_offset = primary_offset + unpack_u24(header->iram_offset);
 236         iram_size = unpack_u24(header->iram_size);
 237
 238         dram_offset = primary_offset + unpack_u24(header->dram_offset);
 239         dram_size = unpack_u24(header->dram_size);
 240
 241         debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
 242               primary_offset, iram_offset, iram_size, dram_offset, dram_size);
 243
 244         strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
 245                 VERSION_STRING_SIZE);
 246         printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
 247
 248         /* stall the microcprocessor */
 249         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 250                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
 251
 252         debug("loading dram 0x%08x from offset=%d size=%d\n",
 253               DRAM_BASE_ADDR, dram_offset, dram_size);
 254         ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
 255                                    dram_size);
 256         if (ret != 0)
 257                 goto done;
 258
 259         debug("loading iram 0x%08x from offset=%d size=%d\n",
 260               IRAM_BASE_ADDR, iram_offset, iram_size);
 261         ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
 262                                    iram_size);
 263         if (ret != 0)
 264                 goto done;
 265
 266         /* make sure soft reset and low power mode are clear */
 267         phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
 268
 269         /* Release the microprocessor. UP_RESET must be held for 100 usec. */
 270         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 271                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
 272
 273         udelay(100);
 274
 275         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
 276
 277         printf("%s firmare loading done.\n", phydev->dev->name);
 278 done:
 279         free(addr);
 280         return ret;
 281 }
 282 #else
 283 static int aquantia_upload_firmware(struct phy_device *phydev)
 284 {
 285         printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
 286         return -1;
 287 }
 288 #endif
 289
 290 struct {
 291         u16 syscfg;
 292         int cnt;
 293         u16 start_rate;
 294 } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
 295         [PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
 296                                            AQUANTIA_VND1_GSTART_RATE_1G},
 297         [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
 298                                            AQUANTIA_VND1_GSTART_RATE_2_5G},
 299         [PHY_INTERFACE_MODE_XGMII] =      {0x100, AQUANTIA_VND1_GSYSCFG_10G,
 300                                            AQUANTIA_VND1_GSTART_RATE_10G},
 301         [PHY_INTERFACE_MODE_XFI] =        {0x100, AQUANTIA_VND1_GSYSCFG_10G,
 302                                            AQUANTIA_VND1_GSTART_RATE_10G},
 303         [PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,
 304                                            AQUANTIA_VND1_GSTART_RATE_10G},
 305 };
 306
 307 static int aquantia_set_proto(struct phy_device *phydev)
 308 {
 309         int i;
 310
 311         if (!aquantia_syscfg[phydev->interface].cnt)
 312                 return 0;
 313
 314         /* set the default rate to enable the SI link */
 315         phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
 316                   aquantia_syscfg[phydev->interface].start_rate);
 317
 318         /* set selected protocol for all relevant line side link speeds */
 319         for (i = 0; i <= aquantia_syscfg[phydev->interface].cnt; i++)
 320                 phy_write(phydev, MDIO_MMD_VEND1,
 321                           AQUANTIA_VND1_GSYSCFG_BASE + i,
 322                           aquantia_syscfg[phydev->interface].syscfg);
 323         return 0;
 324 }
 325
 326 static bool aquantia_link_is_up(struct phy_device *phydev)
 327 {
 328         u16 reg, regmask;
 329         int devad, regnum;
 330
 331         /*
 332          * On Gen 2 and 3 we have a bit that indicates that both system and
 333          * line side are ready for data, use that if possible.
 334          */
 335         if (phydev->drv->data == AQUANTIA_GEN2 ||
 336             phydev->drv->data == AQUANTIA_GEN3) {
 337                 devad = MDIO_MMD_PHYXS;
 338                 regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
 339                 regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
 340         } else {
 341                 devad = MDIO_MMD_AN;
 342                 regnum = MDIO_STAT1;
 343                 regmask = MDIO_AN_STAT1_COMPLETE;
 344         }
 345         /* the register should be latched, do a double read */
 346         phy_read(phydev, devad, regnum);
 347         reg = phy_read(phydev, devad, regnum);
 348
 349         return !!(reg & regmask);
 350 }
 351
 352 int aquantia_config(struct phy_device *phydev)
 353 {
 354         int interface = phydev->interface;
 355         u32 val, id, rstatus, fault;
 356         u32 reg_val1 = 0;
 357         int num_retries = 5;
 358         int usx_an = 0;
 359
 360         /*
 361          * check if the system is out of reset and init sequence completed.
 362          * chip-wide reset for gen1 quad phys takes longer
 363          */
 364         while (--num_retries) {
 365                 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
 366                 if (rstatus & SYSTEM_READY_BIT)
 367                         break;
 368                 mdelay(10);
 369         }
 370
 371         id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
 372         rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
 373         fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
 374
 375         if (id != 0)
 376                 printf("%s running firmware version %X.%X.%X\n",
 377                        phydev->dev->name, (id >> 8), id & 0xff,
 378                        (rstatus >> 4) & 0xf);
 379
 380         if (fault != 0)
 381                 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
 382
 383         if (id == 0 || fault != 0) {
 384                 int ret;
 385
 386                 ret = aquantia_upload_firmware(phydev);
 387                 if (ret != 0)
 388                         return ret;
 389         }
 390         /*
 391          * for backward compatibility convert XGMII into either XFI or USX based
 392          * on FW config
 393          */
 394         if (interface == PHY_INTERFACE_MODE_XGMII) {
 395                 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
 396                                     AQUANTIA_SYSTEM_INTERFACE_SR);
 397                 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
 398                         interface = PHY_INTERFACE_MODE_USXGMII;
 399                 else
 400                         interface = PHY_INTERFACE_MODE_XFI;
 401         }
 402
 403         /*
 404          * if link is up already we can just use it, otherwise configure
 405          * the protocols in the PHY.  If link is down set the system
 406          * interface protocol to use based on phydev->interface
 407          */
 408         if (!aquantia_link_is_up(phydev) &&
 409             (phydev->drv->data == AQUANTIA_GEN2 ||
 410              phydev->drv->data == AQUANTIA_GEN3)) {
 411                 /* set PHY in low power mode so we can configure protocols */
 412                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
 413                           AQUANTIA_VND1_GLOBAL_SC_LP);
 414                 mdelay(10);
 415
 416                 /* configure protocol based on phydev->interface */
 417                 aquantia_set_proto(phydev);
 418
 419                 /* wake PHY back up */
 420                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
 421                 mdelay(10);
 422         }
 423
 424         val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 425
 426         switch (interface) {
 427         case PHY_INTERFACE_MODE_SGMII:
 428                 /* 1000BASE-T mode */
 429                 phydev->advertising = SUPPORTED_1000baseT_Full;
 430                 phydev->supported = phydev->advertising;
 431
 432                 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
 433                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 434                 break;
 435         case PHY_INTERFACE_MODE_USXGMII:
 436                 usx_an = 1;
 437                 /* FALLTHROUGH */
 438         case PHY_INTERFACE_MODE_XFI:
 439                 /* 10GBASE-T mode */
 440                 phydev->advertising = SUPPORTED_10000baseT_Full;
 441                 phydev->supported = phydev->advertising;
 442
 443                 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
 444                     !(val & AQUNTIA_SPEED_MSB_MASK))
 445                         phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
 446                                   AQUNTIA_SPEED_LSB_MASK |
 447                                   AQUNTIA_SPEED_MSB_MASK);
 448
 449                 /* If SI is USXGMII then start USXGMII autoneg */
 450                 reg_val1 =  phy_read(phydev, MDIO_MMD_PHYXS,
 451                                      AQUANTIA_VENDOR_PROVISIONING_REG);
 452
 453                 if (usx_an) {
 454                         reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 455                         printf("%s: system interface USXGMII\n",
 456                                phydev->dev->name);
 457                 } else {
 458                         reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 459                         printf("%s: system interface XFI\n",
 460                                phydev->dev->name);
 461                 }
 462
 463                 phy_write(phydev, MDIO_MMD_PHYXS,
 464                           AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
 465                 break;
 466         case PHY_INTERFACE_MODE_SGMII_2500:
 467                 /* 2.5GBASE-T mode */
 468                 phydev->advertising = SUPPORTED_1000baseT_Full;
 469                 phydev->supported = phydev->advertising;
 470
 471                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
 472                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
 473                 break;
 474         case PHY_INTERFACE_MODE_MII:
 475                 /* 100BASE-TX mode */
 476                 phydev->advertising = SUPPORTED_100baseT_Full;
 477                 phydev->supported = phydev->advertising;
 478
 479                 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
 480                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 481                 break;
 482         };
 483
 484         val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
 485         reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
 486
 487         printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
 488                phydev->drv->name,
 489                (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
 490                reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
 491                (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
 492
 493         return 0;
 494 }
 495
 496 int aquantia_startup(struct phy_device *phydev)
 497 {
 498         u32 reg, speed;
 499         int i = 0;
 500
 501         phydev->duplex = DUPLEX_FULL;
 502
 503         /* if the AN is still in progress, wait till timeout. */
 504         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 505         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 506         if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
 507                 printf("%s Waiting for PHY auto negotiation to complete",
 508                        phydev->dev->name);
 509                 do {
 510                         udelay(1000);
 511                         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 512                         if ((i++ % 500) == 0)
 513                                 printf(".");
 514                 } while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
 515                          i < (4 * PHY_ANEG_TIMEOUT));
 516
 517                 if (i > PHY_ANEG_TIMEOUT)
 518                         printf(" TIMEOUT !\n");
 519         }
 520
 521         /* Read twice because link state is latched and a
 522          * read moves the current state into the register */
 523         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 524         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 525         if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
 526                 phydev->link = 0;
 527         else
 528                 phydev->link = 1;
 529
 530         speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 531         if (speed & AQUNTIA_SPEED_MSB_MASK) {
 532                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 533                         phydev->speed = SPEED_10000;
 534                 else
 535                         phydev->speed = SPEED_1000;
 536         } else {
 537                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 538                         phydev->speed = SPEED_100;
 539                 else
 540                         phydev->speed = SPEED_10;
 541         }
 542
 543         return 0;
 544 }
 545
 546 struct phy_driver aq1202_driver = {
 547         .name = "Aquantia AQ1202",
 548         .uid = 0x3a1b445,
 549         .mask = 0xfffffff0,
 550         .features = PHY_10G_FEATURES,
 551         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 552                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 553                         MDIO_MMD_VEND1),
 554         .config = &aquantia_config,
 555         .startup = &aquantia_startup,
 556         .shutdown = &gen10g_shutdown,
 557 };
 558
 559 struct phy_driver aq2104_driver = {
 560         .name = "Aquantia AQ2104",
 561         .uid = 0x3a1b460,
 562         .mask = 0xfffffff0,
 563         .features = PHY_10G_FEATURES,
 564         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 565                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 566                         MDIO_MMD_VEND1),
 567         .config = &aquantia_config,
 568         .startup = &aquantia_startup,
 569         .shutdown = &gen10g_shutdown,
 570 };
 571
 572 struct phy_driver aqr105_driver = {
 573         .name = "Aquantia AQR105",
 574         .uid = 0x3a1b4a2,
 575         .mask = 0xfffffff0,
 576         .features = PHY_10G_FEATURES,
 577         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 578                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 579                         MDIO_MMD_VEND1),
 580         .config = &aquantia_config,
 581         .startup = &aquantia_startup,
 582         .shutdown = &gen10g_shutdown,
 583         .data = AQUANTIA_GEN1,
 584 };
 585
 586 struct phy_driver aqr106_driver = {
 587         .name = "Aquantia AQR106",
 588         .uid = 0x3a1b4d0,
 589         .mask = 0xfffffff0,
 590         .features = PHY_10G_FEATURES,
 591         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 592                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 593                         MDIO_MMD_VEND1),
 594         .config = &aquantia_config,
 595         .startup = &aquantia_startup,
 596         .shutdown = &gen10g_shutdown,
 597 };
 598
 599 struct phy_driver aqr107_driver = {
 600         .name = "Aquantia AQR107",
 601         .uid = 0x3a1b4e0,
 602         .mask = 0xfffffff0,
 603         .features = PHY_10G_FEATURES,
 604         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 605                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 606                         MDIO_MMD_VEND1),
 607         .config = &aquantia_config,
 608         .startup = &aquantia_startup,
 609         .shutdown = &gen10g_shutdown,
 610         .data = AQUANTIA_GEN2,
 611 };
 612
 613 struct phy_driver aqr112_driver = {
 614         .name = "Aquantia AQR112",
 615         .uid = 0x3a1b660,
 616         .mask = 0xfffffff0,
 617         .features = PHY_10G_FEATURES,
 618         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 619                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 620                  MDIO_MMD_VEND1),
 621         .config = &aquantia_config,
 622         .startup = &aquantia_startup,
 623         .shutdown = &gen10g_shutdown,
 624         .data = AQUANTIA_GEN3,
 625 };
 626
 627 struct phy_driver aqr405_driver = {
 628         .name = "Aquantia AQR405",
 629         .uid = 0x3a1b4b2,
 630         .mask = 0xfffffff0,
 631         .features = PHY_10G_FEATURES,
 632         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 633                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 634                  MDIO_MMD_VEND1),
 635         .config = &aquantia_config,
 636         .startup = &aquantia_startup,
 637         .shutdown = &gen10g_shutdown,
 638         .data = AQUANTIA_GEN1,
 639 };
 640
 641 struct phy_driver aqr412_driver = {
 642         .name = "Aquantia AQR412",
 643         .uid = 0x3a1b710,
 644         .mask = 0xfffffff0,
 645         .features = PHY_10G_FEATURES,
 646         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 647                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 648                  MDIO_MMD_VEND1),
 649         .config = &aquantia_config,
 650         .startup = &aquantia_startup,
 651         .shutdown = &gen10g_shutdown,
 652         .data = AQUANTIA_GEN3,
 653 };
 654
 655 int phy_aquantia_init(void)
 656 {
 657         phy_register(&aq1202_driver);
 658         phy_register(&aq2104_driver);
 659         phy_register(&aqr105_driver);
 660         phy_register(&aqr106_driver);
 661         phy_register(&aqr107_driver);
 662         phy_register(&aqr112_driver);
 663         phy_register(&aqr405_driver);
 664         phy_register(&aqr412_driver);
 665
 666         return 0;
 667 }