1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices Industrial Ethernet PHYs
5 * Copyright 2019 Analog Devices Inc.
7 #include <linux/kernel.h>
8 #include <linux/bitfield.h>
9 #include <linux/delay.h>
10 #include <linux/errno.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/mii.h>
14 #include <linux/phy.h>
15 #include <linux/property.h>
17 #define PHY_ID_ADIN1200 0x0283bc20
18 #define PHY_ID_ADIN1300 0x0283bc30
20 #define ADIN1300_MII_EXT_REG_PTR 0x0010
21 #define ADIN1300_MII_EXT_REG_DATA 0x0011
23 #define ADIN1300_PHY_CTRL1 0x0012
24 #define ADIN1300_AUTO_MDI_EN BIT(10)
25 #define ADIN1300_MAN_MDIX_EN BIT(9)
27 #define ADIN1300_RX_ERR_CNT 0x0014
29 #define ADIN1300_PHY_CTRL2 0x0016
30 #define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
31 #define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
32 #define ADIN1300_GROUP_MDIO_EN BIT(6)
33 #define ADIN1300_DOWNSPEEDS_EN \
34 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
36 #define ADIN1300_PHY_CTRL3 0x0017
37 #define ADIN1300_LINKING_EN BIT(13)
38 #define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)
40 #define ADIN1300_INT_MASK_REG 0x0018
41 #define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
42 #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
43 #define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
44 #define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
45 #define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
46 #define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
47 #define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
48 #define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
49 #define ADIN1300_INT_HW_IRQ_EN BIT(0)
50 #define ADIN1300_INT_MASK_EN \
51 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
52 #define ADIN1300_INT_STATUS_REG 0x0019
54 #define ADIN1300_PHY_STATUS1 0x001a
55 #define ADIN1300_PAIR_01_SWAP BIT(11)
57 /* EEE register addresses, accessible via Clause 22 access using
58 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA.
59 * The bit-fields are the same as specified by IEEE for EEE.
61 #define ADIN1300_EEE_CAP_REG 0x8000
62 #define ADIN1300_EEE_ADV_REG 0x8001
63 #define ADIN1300_EEE_LPABLE_REG 0x8002
64 #define ADIN1300_CLOCK_STOP_REG 0x9400
65 #define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
67 #define ADIN1300_GE_SOFT_RESET_REG 0xff0c
68 #define ADIN1300_GE_SOFT_RESET BIT(0)
70 #define ADIN1300_GE_RGMII_CFG_REG 0xff23
71 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
72 #define ADIN1300_GE_RGMII_RX_SEL(x) \
73 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
74 #define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
75 #define ADIN1300_GE_RGMII_GTX_SEL(x) \
76 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
77 #define ADIN1300_GE_RGMII_RXID_EN BIT(2)
78 #define ADIN1300_GE_RGMII_TXID_EN BIT(1)
79 #define ADIN1300_GE_RGMII_EN BIT(0)
81 /* RGMII internal delay settings for rx and tx for ADIN1300 */
82 #define ADIN1300_RGMII_1_60_NS 0x0001
83 #define ADIN1300_RGMII_1_80_NS 0x0002
84 #define ADIN1300_RGMII_2_00_NS 0x0000
85 #define ADIN1300_RGMII_2_20_NS 0x0006
86 #define ADIN1300_RGMII_2_40_NS 0x0007
88 #define ADIN1300_GE_RMII_CFG_REG 0xff24
89 #define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
90 #define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
91 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
92 #define ADIN1300_GE_RMII_EN BIT(0)
94 /* RMII fifo depth values */
95 #define ADIN1300_RMII_4_BITS 0x0000
96 #define ADIN1300_RMII_8_BITS 0x0001
97 #define ADIN1300_RMII_12_BITS 0x0002
98 #define ADIN1300_RMII_16_BITS 0x0003
99 #define ADIN1300_RMII_20_BITS 0x0004
100 #define ADIN1300_RMII_24_BITS 0x0005
103 * struct adin_cfg_reg_map - map a config value to aregister value
104 * @cfg value in device configuration
105 * @reg value in the register
107 struct adin_cfg_reg_map {
112 static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
113 { 1600, ADIN1300_RGMII_1_60_NS },
114 { 1800, ADIN1300_RGMII_1_80_NS },
115 { 2000, ADIN1300_RGMII_2_00_NS },
116 { 2200, ADIN1300_RGMII_2_20_NS },
117 { 2400, ADIN1300_RGMII_2_40_NS },
121 static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
122 { 4, ADIN1300_RMII_4_BITS },
123 { 8, ADIN1300_RMII_8_BITS },
124 { 12, ADIN1300_RMII_12_BITS },
125 { 16, ADIN1300_RMII_16_BITS },
126 { 20, ADIN1300_RMII_20_BITS },
127 { 24, ADIN1300_RMII_24_BITS },
132 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22
133 * @devad device address used in Clause 45 access
134 * @cl45_regnum register address defined by Clause 45
135 * @adin_regnum equivalent register address accessible via Clause 22
137 struct adin_clause45_mmd_map {
143 static struct adin_clause45_mmd_map adin_clause45_mmd_map[] = {
144 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
145 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
146 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
147 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
148 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
151 struct adin_hw_stat {
157 static struct adin_hw_stat adin_hw_stats[] = {
158 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */
159 { "length_error_frames_count", 0x940C },
160 { "alignment_error_frames_count", 0x940D },
161 { "symbol_error_count", 0x940E },
162 { "oversized_frames_count", 0x940F },
163 { "undersized_frames_count", 0x9410 },
164 { "odd_nibble_frames_count", 0x9411 },
165 { "odd_preamble_packet_count", 0x9412 },
166 { "dribble_bits_frames_count", 0x9413 },
167 { "false_carrier_events_count", 0x9414 },
171 * struct adin_priv - ADIN PHY driver private data
172 * stats statistic counters for the PHY
175 u64 stats[ARRAY_SIZE(adin_hw_stats)];
178 static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
182 for (i = 0; tbl[i].cfg; i++) {
183 if (tbl[i].cfg == cfg)
190 static u32 adin_get_reg_value(struct phy_device *phydev,
191 const char *prop_name,
192 const struct adin_cfg_reg_map *tbl,
195 struct device *dev = &phydev->mdio.dev;
199 if (device_property_read_u32(dev, prop_name, &val))
202 rc = adin_lookup_reg_value(tbl, val);
205 "Unsupported value %u for %s using default (%u)\n",
206 val, prop_name, dflt);
213 static int adin_config_rgmii_mode(struct phy_device *phydev)
218 if (!phy_interface_is_rgmii(phydev))
219 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
220 ADIN1300_GE_RGMII_CFG_REG,
221 ADIN1300_GE_RGMII_EN);
223 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
227 reg |= ADIN1300_GE_RGMII_EN;
229 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
230 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
231 reg |= ADIN1300_GE_RGMII_RXID_EN;
233 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
235 ADIN1300_RGMII_2_00_NS);
236 reg &= ~ADIN1300_GE_RGMII_RX_MSK;
237 reg |= ADIN1300_GE_RGMII_RX_SEL(val);
239 reg &= ~ADIN1300_GE_RGMII_RXID_EN;
242 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
243 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
244 reg |= ADIN1300_GE_RGMII_TXID_EN;
246 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
248 ADIN1300_RGMII_2_00_NS);
249 reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
250 reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
252 reg &= ~ADIN1300_GE_RGMII_TXID_EN;
255 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
256 ADIN1300_GE_RGMII_CFG_REG, reg);
259 static int adin_config_rmii_mode(struct phy_device *phydev)
264 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
265 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
266 ADIN1300_GE_RMII_CFG_REG,
267 ADIN1300_GE_RMII_EN);
269 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
273 reg |= ADIN1300_GE_RMII_EN;
275 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
276 adin_rmii_fifo_depths,
277 ADIN1300_RMII_8_BITS);
279 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
280 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
282 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
283 ADIN1300_GE_RMII_CFG_REG, reg);
286 static int adin_get_downshift(struct phy_device *phydev, u8 *data)
288 int val, cnt, enable;
290 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
294 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
298 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val);
299 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
301 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE;
306 static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
311 if (cnt == DOWNSHIFT_DEV_DISABLE)
312 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
313 ADIN1300_DOWNSPEEDS_EN);
318 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
319 val |= ADIN1300_LINKING_EN;
321 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
322 ADIN1300_LINKING_EN | ADIN1300_DOWNSPEED_RETRIES_MSK,
327 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
328 ADIN1300_DOWNSPEEDS_EN);
331 static int adin_get_tunable(struct phy_device *phydev,
332 struct ethtool_tunable *tuna, void *data)
335 case ETHTOOL_PHY_DOWNSHIFT:
336 return adin_get_downshift(phydev, data);
342 static int adin_set_tunable(struct phy_device *phydev,
343 struct ethtool_tunable *tuna, const void *data)
346 case ETHTOOL_PHY_DOWNSHIFT:
347 return adin_set_downshift(phydev, *(const u8 *)data);
353 static int adin_config_init(struct phy_device *phydev)
357 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
359 rc = adin_config_rgmii_mode(phydev);
363 rc = adin_config_rmii_mode(phydev);
367 rc = adin_set_downshift(phydev, 4);
371 phydev_dbg(phydev, "PHY is using mode '%s'\n",
372 phy_modes(phydev->interface));
377 static int adin_phy_ack_intr(struct phy_device *phydev)
379 /* Clear pending interrupts */
380 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
382 return rc < 0 ? rc : 0;
385 static int adin_phy_config_intr(struct phy_device *phydev)
387 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
388 return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
389 ADIN1300_INT_MASK_EN);
391 return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
392 ADIN1300_INT_MASK_EN);
395 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
398 struct adin_clause45_mmd_map *m;
401 if (devad == MDIO_MMD_VEND1)
404 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) {
405 m = &adin_clause45_mmd_map[i];
406 if (m->devad == devad && m->cl45_regnum == cl45_regnum)
407 return m->adin_regnum;
411 "No translation available for devad: %d reg: %04x\n",
417 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
419 struct mii_bus *bus = phydev->mdio.bus;
420 int phy_addr = phydev->mdio.addr;
424 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
428 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
433 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
436 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
439 struct mii_bus *bus = phydev->mdio.bus;
440 int phy_addr = phydev->mdio.addr;
444 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
448 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
453 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
456 static int adin_config_mdix(struct phy_device *phydev)
458 bool auto_en, mdix_en;
463 switch (phydev->mdix_ctrl) {
469 case ETH_TP_MDI_AUTO:
476 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
481 reg |= ADIN1300_MAN_MDIX_EN;
483 reg &= ~ADIN1300_MAN_MDIX_EN;
486 reg |= ADIN1300_AUTO_MDI_EN;
488 reg &= ~ADIN1300_AUTO_MDI_EN;
490 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
493 static int adin_config_aneg(struct phy_device *phydev)
497 ret = adin_config_mdix(phydev);
501 return genphy_config_aneg(phydev);
504 static int adin_mdix_update(struct phy_device *phydev)
506 bool auto_en, mdix_en;
510 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
514 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
515 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
517 /* If MDI/MDIX is forced, just read it from the control reg */
520 phydev->mdix = ETH_TP_MDI_X;
522 phydev->mdix = ETH_TP_MDI;
527 * Otherwise, we need to deduce it from the PHY status2 reg.
528 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies
529 * a preference for MDIX when it is set.
531 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
535 swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
537 if (mdix_en != swapped)
538 phydev->mdix = ETH_TP_MDI_X;
540 phydev->mdix = ETH_TP_MDI;
545 static int adin_read_status(struct phy_device *phydev)
549 ret = adin_mdix_update(phydev);
553 return genphy_read_status(phydev);
556 static int adin_soft_reset(struct phy_device *phydev)
560 /* The reset bit is self-clearing, set it and wait */
561 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
562 ADIN1300_GE_SOFT_RESET_REG,
563 ADIN1300_GE_SOFT_RESET);
569 /* If we get a read error something may be wrong */
570 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
571 ADIN1300_GE_SOFT_RESET_REG);
573 return rc < 0 ? rc : 0;
576 static int adin_get_sset_count(struct phy_device *phydev)
578 return ARRAY_SIZE(adin_hw_stats);
581 static void adin_get_strings(struct phy_device *phydev, u8 *data)
585 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
586 strlcpy(&data[i * ETH_GSTRING_LEN],
587 adin_hw_stats[i].string, ETH_GSTRING_LEN);
591 static int adin_read_mmd_stat_regs(struct phy_device *phydev,
592 struct adin_hw_stat *stat,
597 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
601 *val = (ret & 0xffff);
606 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
611 *val |= (ret & 0xffff);
616 static u64 adin_get_stat(struct phy_device *phydev, int i)
618 struct adin_hw_stat *stat = &adin_hw_stats[i];
619 struct adin_priv *priv = phydev->priv;
623 if (stat->reg1 > 0x1f) {
624 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
628 ret = phy_read(phydev, stat->reg1);
631 val = (ret & 0xffff);
634 priv->stats[i] += val;
636 return priv->stats[i];
639 static void adin_get_stats(struct phy_device *phydev,
640 struct ethtool_stats *stats, u64 *data)
644 /* latch copies of all the frame-checker counters */
645 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
649 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
650 data[i] = adin_get_stat(phydev, i);
653 static int adin_probe(struct phy_device *phydev)
655 struct device *dev = &phydev->mdio.dev;
656 struct adin_priv *priv;
658 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
667 static struct phy_driver adin_driver[] = {
669 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
672 .config_init = adin_config_init,
673 .soft_reset = adin_soft_reset,
674 .config_aneg = adin_config_aneg,
675 .read_status = adin_read_status,
676 .get_tunable = adin_get_tunable,
677 .set_tunable = adin_set_tunable,
678 .ack_interrupt = adin_phy_ack_intr,
679 .config_intr = adin_phy_config_intr,
680 .get_sset_count = adin_get_sset_count,
681 .get_strings = adin_get_strings,
682 .get_stats = adin_get_stats,
683 .resume = genphy_resume,
684 .suspend = genphy_suspend,
685 .read_mmd = adin_read_mmd,
686 .write_mmd = adin_write_mmd,
689 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
692 .config_init = adin_config_init,
693 .soft_reset = adin_soft_reset,
694 .config_aneg = adin_config_aneg,
695 .read_status = adin_read_status,
696 .get_tunable = adin_get_tunable,
697 .set_tunable = adin_set_tunable,
698 .ack_interrupt = adin_phy_ack_intr,
699 .config_intr = adin_phy_config_intr,
700 .get_sset_count = adin_get_sset_count,
701 .get_strings = adin_get_strings,
702 .get_stats = adin_get_stats,
703 .resume = genphy_resume,
704 .suspend = genphy_suspend,
705 .read_mmd = adin_read_mmd,
706 .write_mmd = adin_write_mmd,
710 module_phy_driver(adin_driver);
712 static struct mdio_device_id __maybe_unused adin_tbl[] = {
713 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
714 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
718 MODULE_DEVICE_TABLE(mdio, adin_tbl);
719 MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
720 MODULE_LICENSE("GPL");